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IronPort-SDR: 0mHhU6xW5jYa0gqmqanFE4tSK3UAVzOjw5acDrYaN7LBhfWb2ovNjS/kDasbC4xXs5LIKWQPh7 8VSh2K2JUOckp2khKniaon5rvj0lFIvNq5rOIALJkLXowIIMQo/lZPgHk/IbxioFj2GCqVHYfj llBltPxhXq8/XnDfoeXkdyfMjQJK0Mwbl7jVzwCjx/rUvLttPnllJTXPH0C71xPls41rQ12wz5 v4nt8j/10W4Aq2dXuHy4RIPGYSd4HOHEm2rez52b+GOKYzJeHFon/tyBOShuntwjlA+gA+FipR 3Jc= X-IronPort-AV: E=Sophos;i="5.72,395,1580799600"; d="scan'208";a="9536051" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Apr 2020 05:57:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 17 Apr 2020 05:57:37 -0700 Received: from [10.205.29.56] (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Fri, 17 Apr 2020 05:57:12 -0700 Subject: Re: [PATCH 4/5] net: macb: WoL support for GEM type of Ethernet controller To: Florian Fainelli , , , "Claudiu Beznea" , References: <56bb7a742093cec160c4465c808778a14b2607e7.1587058078.git.nicolas.ferre@microchip.com> <6fc99e01-6d64-4248-3627-aa14a914df72@gmail.com> From: Nicolas Ferre Organization: microchip Message-ID: Date: Fri, 17 Apr 2020 14:57:31 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <6fc99e01-6d64-4248-3627-aa14a914df72@gmail.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200417_055738_945687_BEF748E0 X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@lunn.ch, Alexandre Belloni , sergio.prado@e-labworks.com, pthombar@cadence.com, antoine.tenart@bootlin.com, michal.simek@xilinx.com, linux-kernel@vger.kernel.org, linux@armlinux.org.uk, "David S. Miller" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Florian, Thank you for your review of the series! On 16/04/2020 at 21:25, Florian Fainelli wrote: > On 4/16/2020 10:44 AM, nicolas.ferre@microchip.com wrote: >> From: Nicolas Ferre >> >> Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller. >> This controller has different register layout and cannot be handled by >> previous code. >> We disable completely interrupts on all the queues but the queue 0. >> Handling of WoL interrupt is done in another interrupt handler >> positioned depending on the controller version used, just between >> suspend() and resume() calls. >> It allows to lower pressure on the generic interrupt hot path by >> removing the need to handle 2 tests for each IRQ: the first figuring out >> the controller revision, the second for actually knowing if the WoL bit >> is set. >> >> Queue management in suspend()/resume() functions inspired from RFC patch >> by Harini Katakam , thanks! >> >> Signed-off-by: Nicolas Ferre >> --- > > [snip] > >> >> +static irqreturn_t gem_wol_interrupt(int irq, void *dev_id) >> +{ >> + struct macb_queue *queue = dev_id; >> + struct macb *bp = queue->bp; >> + u32 status; >> + >> + status = queue_readl(queue, ISR); >> + >> + if (unlikely(!status)) >> + return IRQ_NONE; >> + >> + spin_lock(&bp->lock); >> + >> + if (status & GEM_BIT(WOL)) { >> + queue_writel(queue, IDR, GEM_BIT(WOL)); >> + gem_writel(bp, WOL, 0); >> + netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n", >> + (unsigned int)(queue - bp->queues), >> + (unsigned long)status); >> + if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) >> + queue_writel(queue, ISR, GEM_BIT(WOL)); > > You would also need a pm_wakeup_event() call here to record that this > device did wake-up the system. Oh yes, indeed that's missing. I'll add it to my v2. Thanks. Best regards, Nicolas -- Nicolas Ferre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel