* [PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list
[not found] <1575385543-11290-1-git-send-email-smasetty@codeaurora.org>
@ 2019-12-03 15:06 ` Sharat Masetty
2019-12-03 15:06 ` [PATCH 2/5] drm: msm: a6xx: Add support for A618 Sharat Masetty
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sharat Masetty @ 2019-12-03 15:06 UTC (permalink / raw)
To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty
This patch adds Adreno 618 entry and its associated properties
to the gpulist entries.
Change-Id: Ie14ba09f32513ba6a6c882fda0d98ee1742b46d5
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 0888e0d..e728ea5 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -152,6 +152,17 @@
.init = a5xx_gpu_init,
.zapfw = "a540_zap.mdt",
}, {
+ .rev = ADRENO_REV(6, 1, 8, ANY_ID),
+ .revn = 618,
+ .name = "A618",
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a630_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .init = a6xx_gpu_init,
+ }, {
.rev = ADRENO_REV(6, 3, 0, ANY_ID),
.revn = 630,
.name = "A630",
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/5] drm: msm: a6xx: Add support for A618
[not found] <1575385543-11290-1-git-send-email-smasetty@codeaurora.org>
2019-12-03 15:06 ` [PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list Sharat Masetty
@ 2019-12-03 15:06 ` Sharat Masetty
2019-12-03 15:06 ` [PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state Sharat Masetty
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sharat Masetty @ 2019-12-03 15:06 UTC (permalink / raw)
To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty
This patch adds support for enabling Graphics Bus Interface(GBIF)
used in multiple A6xx series chipets. Also makes changes to the
PDC/RSC sequencing specifically required for A618. This is needed
for proper interfacing with RPMH.
Change-Id: I0e7a314b0ae0d562f602512ad978f5d1ced5fb26
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 52 +++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 24 +++++++++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 ++++++++++++++++++++++++++++++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 +++++-
5 files changed, 154 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index f44553e..ed78fee 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -16,11 +16,11 @@
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
+- /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
-Copyright (C) 2013-2018 by the following authors:
+Copyright (C) 2013-2019 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -2519,6 +2519,54 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
+#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
+
+#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
+
+#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
+
+#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
+
+#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
+
+#define REG_A6XX_GBIF_HALT 0x00003c45
+
+#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
+
+#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
+
+#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
+
+#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
+
+#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
+
+#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
+
+#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
+
+#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
+
+#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
+
+#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
+
+#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
+
+#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
+
+#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
+
+#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
+
+#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
+
+#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
+
+#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
+
+#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
+
#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
#define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 85f14fe..158a74c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
#include <linux/clk.h>
#include <linux/interconnect.h>
@@ -433,6 +433,8 @@ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
{
+ struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
+ struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
struct platform_device *pdev = to_platform_device(gmu->dev);
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
@@ -480,20 +482,34 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
- pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
+ if (adreno_is_a618(adreno_gpu))
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
+ else
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
- pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
+ if (adreno_is_a618(adreno_gpu))
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
+ else
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
+
+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
- pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
+ if (adreno_is_a618(adreno_gpu))
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
+ else
+ pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
/* Setup GPU PDC */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index dc8ec2c..6fdffae 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
#include "msm_gem.h"
@@ -378,6 +378,18 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
int ret;
+ /*
+ * During a previous slumber, GBIF halt is asserted to ensure
+ * no further transaction can go through GPU before GPU
+ * headswitch is turned off.
+ *
+ * This halt is deasserted once headswitch goes off but
+ * incase headswitch doesn't goes off clear GBIF halt
+ * here to ensure GPU wake-up doesn't fail because of
+ * halted GPU transactions.
+ */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
+
/* Make sure the GMU keeps the GPU on while we set it up */
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
@@ -406,12 +418,17 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
- /* enable hardware clockgating */
- a6xx_set_hwcg(gpu, true);
+ /*
+ * enable hardware clockgating
+ * For now enable clock gating only for a630
+ */
+ if (adreno_is_a630(adreno_gpu))
+ a6xx_set_hwcg(gpu, true);
- /* VBIF start */
- gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
+ /* VBIF/GBIF start*/
gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
+ if (adreno_is_a630(adreno_gpu))
+ gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
/* Make all blocks contribute to the GPU BUSY perf counter */
gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
@@ -724,6 +741,39 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
};
+#define GBIF_CLIENT_HALT_MASK BIT(0)
+#define GBIF_ARB_HALT_MASK BIT(1)
+
+static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
+{
+ struct msm_gpu *gpu = &adreno_gpu->base;
+
+ if(!a6xx_has_gbif(adreno_gpu)){
+ gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
+ spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
+ 0xf) == 0xf);
+ gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
+
+ return;
+ }
+
+ /* Halt new client requests on GBIF */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
+ spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
+ (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
+
+ /* Halt all AXI requests on GBIF */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
+ spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
+ (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
+
+ /*
+ * GMU needs DDR access in slumber path. Deassert GBIF halt now
+ * to allow for GMU to access system memory.
+ */
+ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
+}
+
static int a6xx_pm_resume(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -748,6 +798,16 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
devfreq_suspend_device(gpu->devfreq.devfreq);
+ /*
+ * Make sure the GMU is idle before continuing (because some transitions
+ * may use VBIF
+ */
+ a6xx_gmu_wait_for_idle(&a6xx_gpu->gmu);
+
+ /* Clear the VBIF pipe before shutting down */
+ /* FIXME: This accesses the GPU - do we need to make sure it is on? */
+ a6xx_bus_clear_pending_transactions(adreno_gpu);
+
return a6xx_gmu_stop(a6xx_gpu);
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 6439955..7239b8b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
#ifndef __A6XX_GPU_H__
#define __A6XX_GPU_H__
@@ -42,6 +42,13 @@ struct a6xx_gpu {
#define A6XX_PROTECT_RDONLY(_reg, _len) \
((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
+static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
+{
+ if(adreno_is_a630(gpu))
+ return false;
+
+ return true;
+}
int a6xx_gmu_resume(struct a6xx_gpu *gpu);
int a6xx_gmu_stop(struct a6xx_gpu *gpu);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index c7441fb..e12d5a9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -3,7 +3,7 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
- * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
*/
#ifndef __ADRENO_GPU_H__
@@ -216,6 +216,16 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
return gpu->revn == 540;
}
+static inline int adreno_is_a618(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 618;
+}
+
+static inline int adreno_is_a630(struct adreno_gpu *gpu)
+{
+ return gpu->revn == 630;
+}
+
int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
const char *fwname);
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state
[not found] <1575385543-11290-1-git-send-email-smasetty@codeaurora.org>
2019-12-03 15:06 ` [PATCH 1/5] drm: msm: Add 618 gpu to the adreno gpu list Sharat Masetty
2019-12-03 15:06 ` [PATCH 2/5] drm: msm: a6xx: Add support for A618 Sharat Masetty
@ 2019-12-03 15:06 ` Sharat Masetty
2019-12-03 15:06 ` [PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration Sharat Masetty
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Sharat Masetty @ 2019-12-03 15:06 UTC (permalink / raw)
To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty
Add the relevant GBIF registers and the debug bus to the a6xx gpu
state. This comes in pretty handy when debugging GPU bus related
issues.
Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++++++++++++++++++++++------
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 16 +++++++--
2 files changed, 55 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index e686331..99b5a41 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
#include <linux/ascii85.h>
#include "msm_gem.h"
@@ -320,6 +320,7 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
{
struct resource *res;
void __iomem *cxdbg = NULL;
+ int nr_debugbus_blocks;
/* Set up the GX debug bus */
@@ -374,9 +375,11 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
}
- a6xx_state->debugbus = state_kcalloc(a6xx_state,
- ARRAY_SIZE(a6xx_debugbus_blocks),
- sizeof(*a6xx_state->debugbus));
+ nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
+ (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
+
+ a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
+ sizeof(*a6xx_state->debugbus));
if (a6xx_state->debugbus) {
int i;
@@ -388,15 +391,31 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
&a6xx_state->debugbus[i]);
a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
+
+ /*
+ * GBIF has same debugbus as of other GPU blocks, fall back to
+ * default path if GPU uses GBIF, also GBIF uses exactly same
+ * ID as of VBIF.
+ */
+ if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
+ a6xx_get_debugbus_block(gpu, a6xx_state,
+ &a6xx_gbif_debugbus_block,
+ &a6xx_state->debugbus[i]);
+
+ a6xx_state->nr_debugbus += 1;
+ }
}
- a6xx_state->vbif_debugbus =
- state_kcalloc(a6xx_state, 1,
- sizeof(*a6xx_state->vbif_debugbus));
+ /* Dump the VBIF debugbus on applicable targets */
+ if (!a6xx_has_gbif(to_adreno_gpu(gpu))) {
+ a6xx_state->vbif_debugbus =
+ state_kcalloc(a6xx_state, 1,
+ sizeof(*a6xx_state->vbif_debugbus));
- if (a6xx_state->vbif_debugbus)
- a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
- a6xx_state->vbif_debugbus);
+ if (a6xx_state->vbif_debugbus)
+ a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
+ a6xx_state->vbif_debugbus);
+ }
if (cxdbg) {
a6xx_state->cx_debugbus =
@@ -770,14 +789,16 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
&a6xx_state->gmu_registers[1]);
}
+#define A6XX_GBIF_REGLIST_SIZE 1
static void a6xx_get_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
int i, count = ARRAY_SIZE(a6xx_ahb_reglist) +
ARRAY_SIZE(a6xx_reglist) +
- ARRAY_SIZE(a6xx_hlsq_reglist);
+ ARRAY_SIZE(a6xx_hlsq_reglist) + A6XX_GBIF_REGLIST_SIZE;
int index = 0;
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
a6xx_state->registers = state_kcalloc(a6xx_state,
count, sizeof(*a6xx_state->registers));
@@ -792,6 +813,15 @@ static void a6xx_get_registers(struct msm_gpu *gpu,
a6xx_state, &a6xx_ahb_reglist[i],
&a6xx_state->registers[index++]);
+ if (a6xx_has_gbif(adreno_gpu))
+ a6xx_get_ahb_gpu_registers(gpu,
+ a6xx_state, &a6xx_gbif_reglist,
+ &a6xx_state->registers[index++]);
+ else
+ a6xx_get_ahb_gpu_registers(gpu,
+ a6xx_state, &a6xx_vbif_reglist,
+ &a6xx_state->registers[index++]);
+
for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
a6xx_get_crashdumper_registers(gpu,
a6xx_state, &a6xx_reglist[i],
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index 68cccfa..e67c20c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
#ifndef _A6XX_CRASH_DUMP_H_
#define _A6XX_CRASH_DUMP_H_
@@ -307,11 +307,20 @@ struct a6xx_registers {
0x3410, 0x3410, 0x3800, 0x3801,
};
+static const u32 a6xx_gbif_registers[] = {
+ 0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
+};
+
static const struct a6xx_registers a6xx_ahb_reglist[] = {
REGS(a6xx_ahb_registers, 0, 0),
- REGS(a6xx_vbif_registers, 0, 0),
};
+static const struct a6xx_registers a6xx_vbif_reglist =
+ REGS(a6xx_vbif_registers, 0, 0);
+
+static const struct a6xx_registers a6xx_gbif_reglist =
+ REGS(a6xx_gbif_registers, 0, 0);
+
static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
@@ -422,6 +431,9 @@ struct a6xx_registers {
DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
};
+static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
+ DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
+
static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration
[not found] <1575385543-11290-1-git-send-email-smasetty@codeaurora.org>
` (2 preceding siblings ...)
2019-12-03 15:06 ` [PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state Sharat Masetty
@ 2019-12-03 15:06 ` Sharat Masetty
2019-12-16 16:27 ` Jordan Crouse
2019-12-03 15:06 ` [PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob Sharat Masetty
` (2 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Sharat Masetty @ 2019-12-03 15:06 UTC (permalink / raw)
To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty
Fix the cx debugbus related register configuration, to collect accurate
bus data during gpu snapshot. This helps with complete snapshot dump
and also complete proper GPU recovery.
Change-Id: I4f0ae3eb2dd5d24a88d805277fad212dda2d735e
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index 99b5a41..d6023ba 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -353,26 +353,26 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
cxdbg = ioremap(res->start, resource_size(res));
if (cxdbg) {
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT,
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT,
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf));
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM,
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM,
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf));
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0,
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0,
0x76543210);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1,
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1,
0xFEDCBA98);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0);
- cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2, 0);
+ cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
}
nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration
2019-12-03 15:06 ` [PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration Sharat Masetty
@ 2019-12-16 16:27 ` Jordan Crouse
0 siblings, 0 replies; 9+ messages in thread
From: Jordan Crouse @ 2019-12-16 16:27 UTC (permalink / raw)
To: Sharat Masetty; +Cc: freedreno, dri-devel, linux-arm-msm
On Tue, Dec 03, 2019 at 03:06:15PM +0000, Sharat Masetty wrote:
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
This guy should be flagged for stable.
> Change-Id: I4f0ae3eb2dd5d24a88d805277fad212dda2d735e
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index 99b5a41..d6023ba 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> @@ -353,26 +353,26 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
> cxdbg = ioremap(res->start, resource_size(res));
>
> if (cxdbg) {
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT,
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT,
> A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf));
>
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM,
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM,
> A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf));
>
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3, 0);
>
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0,
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0,
> 0x76543210);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1,
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1,
> 0xFEDCBA98);
>
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0);
> - cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2, 0);
> + cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
> }
>
> nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
> --
> 1.9.1
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
[not found] <1575385543-11290-1-git-send-email-smasetty@codeaurora.org>
` (3 preceding siblings ...)
2019-12-03 15:06 ` [PATCH 4/5] drm: msm: a6xx: fix debug bus register configuration Sharat Masetty
@ 2019-12-03 15:06 ` Sharat Masetty
[not found] ` <0101016ecc4c2621-178923ff-2100-4c3d-95e2-71bdf6f61c0f-000000@us-west-2.amazonses.com>
[not found] ` <0101016ecc4c1ef2-50d18bb8-19c3-4bdb-a980-9192e402aea5-000000@us-west-2.amazonses.com>
6 siblings, 0 replies; 9+ messages in thread
From: Sharat Masetty @ 2019-12-03 15:06 UTC (permalink / raw)
To: freedreno; +Cc: dri-devel, linux-arm-msm, Sharat Masetty
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Change-Id: I7491c4de654c4b84d03dbcf703532448b27d4147
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c3db2e5..31223d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -18,6 +18,8 @@
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
/ {
interrupt-parent = <&intc>;
@@ -733,6 +735,120 @@
#power-domain-cells = <1>;
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-618.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>,
+ <0 0x5061000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ interconnects = <&gem_noc 35 &mc_virt 512>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-565000000 {
+ opp-hz = /bits/ 64 <565000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-355000000 {
+ opp-hz = /bits/ 64 <355000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@5040000 {
+ compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+ reg = <0 0x5040000 0 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+
+ clock-names = "bus", "iface", "mem_iface_clk";
+ power-domains = <&gpucc CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
+
+ reg = <0 0x506a000 0 0x31000>,
+ <0 0xb290000 0 0x10000>,
+ <0 0xb490000 0 0x10000>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc CX_GDSC>;
+
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
[parent not found: <0101016ecc4c2621-178923ff-2100-4c3d-95e2-71bdf6f61c0f-000000@us-west-2.amazonses.com>]
* Re: [PATCH 3/5] drm: msm: a6xx: Dump GBIF registers, debugbus in gpu state
[not found] ` <0101016ecc4c2621-178923ff-2100-4c3d-95e2-71bdf6f61c0f-000000@us-west-2.amazonses.com>
@ 2019-12-16 16:17 ` Jordan Crouse
0 siblings, 0 replies; 9+ messages in thread
From: Jordan Crouse @ 2019-12-16 16:17 UTC (permalink / raw)
To: Sharat Masetty; +Cc: freedreno, linux-arm-msm, dri-devel
On Tue, Dec 03, 2019 at 03:06:12PM +0000, Sharat Masetty wrote:
> Add the relevant GBIF registers and the debug bus to the a6xx gpu
> state. This comes in pretty handy when debugging GPU bus related
> issues.
>
> Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +++++++++++++++++++++++------
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 16 +++++++--
> 2 files changed, 55 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index e686331..99b5a41 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: GPL-2.0
> -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
>
> #include <linux/ascii85.h>
> #include "msm_gem.h"
> @@ -320,6 +320,7 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
> {
> struct resource *res;
> void __iomem *cxdbg = NULL;
> + int nr_debugbus_blocks;
>
> /* Set up the GX debug bus */
>
> @@ -374,9 +375,11 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
> cxdbg_write(cxdbg, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
> }
>
> - a6xx_state->debugbus = state_kcalloc(a6xx_state,
> - ARRAY_SIZE(a6xx_debugbus_blocks),
> - sizeof(*a6xx_state->debugbus));
> + nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
> + (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
> +
> + a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
> + sizeof(*a6xx_state->debugbus));
>
> if (a6xx_state->debugbus) {
> int i;
VBIF died with the A630, never to return. Instead of a single function that
uses if statements all over the place we should split this into two functions -
a630_get_debugbus and a6xx_get_debugbus and treat GBIF as the default and VBIF
as the exception. It might result in a bit more code duplication but IMO is
better than forcing all future targets through a half dozen logic checks that
will always be true.
> @@ -388,15 +391,31 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
> &a6xx_state->debugbus[i]);
>
> a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
> +
> + /*
> + * GBIF has same debugbus as of other GPU blocks, fall back to
> + * default path if GPU uses GBIF, also GBIF uses exactly same
> + * ID as of VBIF.
> + */
> + if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
> + a6xx_get_debugbus_block(gpu, a6xx_state,
> + &a6xx_gbif_debugbus_block,
> + &a6xx_state->debugbus[i]);
> +
> + a6xx_state->nr_debugbus += 1;
> + }
> }
>
> - a6xx_state->vbif_debugbus =
> - state_kcalloc(a6xx_state, 1,
> - sizeof(*a6xx_state->vbif_debugbus));
> + /* Dump the VBIF debugbus on applicable targets */
> + if (!a6xx_has_gbif(to_adreno_gpu(gpu))) {
> + a6xx_state->vbif_debugbus =
> + state_kcalloc(a6xx_state, 1,
> + sizeof(*a6xx_state->vbif_debugbus));
>
> - if (a6xx_state->vbif_debugbus)
> - a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
> - a6xx_state->vbif_debugbus);
> + if (a6xx_state->vbif_debugbus)
> + a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
> + a6xx_state->vbif_debugbus);
> + }
>
> if (cxdbg) {
> a6xx_state->cx_debugbus =
> @@ -770,14 +789,16 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
> &a6xx_state->gmu_registers[1]);
> }
>
> +#define A6XX_GBIF_REGLIST_SIZE 1
> static void a6xx_get_registers(struct msm_gpu *gpu,
> struct a6xx_gpu_state *a6xx_state,
> struct a6xx_crashdumper *dumper)
> {
> int i, count = ARRAY_SIZE(a6xx_ahb_reglist) +
> ARRAY_SIZE(a6xx_reglist) +
> - ARRAY_SIZE(a6xx_hlsq_reglist);
> + ARRAY_SIZE(a6xx_hlsq_reglist) + A6XX_GBIF_REGLIST_SIZE;
> int index = 0;
> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>
> a6xx_state->registers = state_kcalloc(a6xx_state,
> count, sizeof(*a6xx_state->registers));
> @@ -792,6 +813,15 @@ static void a6xx_get_registers(struct msm_gpu *gpu,
> a6xx_state, &a6xx_ahb_reglist[i],
> &a6xx_state->registers[index++]);
>
> + if (a6xx_has_gbif(adreno_gpu))
> + a6xx_get_ahb_gpu_registers(gpu,
> + a6xx_state, &a6xx_gbif_reglist,
> + &a6xx_state->registers[index++]);
> + else
> + a6xx_get_ahb_gpu_registers(gpu,
> + a6xx_state, &a6xx_vbif_reglist,
> + &a6xx_state->registers[index++]);
> +
> for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++)
> a6xx_get_crashdumper_registers(gpu,
> a6xx_state, &a6xx_reglist[i],
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> index 68cccfa..e67c20c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: GPL-2.0
> -/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
>
> #ifndef _A6XX_CRASH_DUMP_H_
> #define _A6XX_CRASH_DUMP_H_
> @@ -307,11 +307,20 @@ struct a6xx_registers {
> 0x3410, 0x3410, 0x3800, 0x3801,
> };
>
> +static const u32 a6xx_gbif_registers[] = {
> + 0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
Lower case hex, please.
> +};
> +
> static const struct a6xx_registers a6xx_ahb_reglist[] = {
> REGS(a6xx_ahb_registers, 0, 0),
> - REGS(a6xx_vbif_registers, 0, 0),
> };
>
> +static const struct a6xx_registers a6xx_vbif_reglist =
> + REGS(a6xx_vbif_registers, 0, 0);
> +
> +static const struct a6xx_registers a6xx_gbif_reglist =
> + REGS(a6xx_gbif_registers, 0, 0);
> +
> static const u32 a6xx_gmu_gx_registers[] = {
> /* GMU GX */
> 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
> @@ -422,6 +431,9 @@ struct a6xx_registers {
> DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
> };
>
> +static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
> + DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
> +
> static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
> DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
> DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread
[parent not found: <0101016ecc4c1ef2-50d18bb8-19c3-4bdb-a980-9192e402aea5-000000@us-west-2.amazonses.com>]
* Re: [PATCH 2/5] drm: msm: a6xx: Add support for A618
[not found] ` <0101016ecc4c1ef2-50d18bb8-19c3-4bdb-a980-9192e402aea5-000000@us-west-2.amazonses.com>
@ 2019-12-16 16:26 ` Jordan Crouse
0 siblings, 0 replies; 9+ messages in thread
From: Jordan Crouse @ 2019-12-16 16:26 UTC (permalink / raw)
To: Sharat Masetty; +Cc: freedreno, linux-arm-msm, dri-devel
On Tue, Dec 03, 2019 at 03:06:11PM +0000, Sharat Masetty wrote:
> This patch adds support for enabling Graphics Bus Interface(GBIF)
> used in multiple A6xx series chipets. Also makes changes to the
> PDC/RSC sequencing specifically required for A618. This is needed
> for proper interfacing with RPMH.
>
> Change-Id: I0e7a314b0ae0d562f602512ad978f5d1ced5fb26
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 52 +++++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 24 +++++++++--
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 ++++++++++++++++++++++++++++++---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 +++++-
> 5 files changed, 154 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> index f44553e..ed78fee 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
> @@ -16,11 +16,11 @@
> - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
> - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
> -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
> +- /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16)
> - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
> - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
>
> -Copyright (C) 2013-2018 by the following authors:
> +Copyright (C) 2013-2019 by the following authors:
> - Rob Clark <robdclark@gmail.com> (robclark)
> - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
>
> @@ -2519,6 +2519,54 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
>
> #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
>
> +#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
> +
> +#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
> +
> +#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
> +
> +#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
> +
> +#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
> +
> +#define REG_A6XX_GBIF_HALT 0x00003c45
> +
> +#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
> +
> +#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
> +
> +#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
> +
> +#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
> +
> +#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
> +
> +#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
> +
> +#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
> +
> +#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
> +
> +#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
> +
> +#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
> +
> +#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
> +
> +#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
> +
> +#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
> +
> +#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
> +
> +#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
> +
> +#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
> +
> +#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
> +
> +#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
> +
> #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
> #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
> #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 85f14fe..158a74c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: GPL-2.0
> -/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
>
> #include <linux/clk.h>
> #include <linux/interconnect.h>
> @@ -433,6 +433,8 @@ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
>
> static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> {
> + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> struct platform_device *pdev = to_platform_device(gmu->dev);
> void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
> void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
> @@ -480,20 +482,34 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
> +
Unneeded whitespace change.
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
> + if (adreno_is_a618(adreno_gpu))
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
> + else
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
> +
Unneeded whitespace change.
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
> +
Also an uneeded whitespace change
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
> + if (adreno_is_a618(adreno_gpu))
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
> + else
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
> +
> +
Extra blank line here
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
> - pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
> + if (adreno_is_a618(adreno_gpu))
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
> + else
> + pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
> pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
>
> /* Setup GPU PDC */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index dc8ec2c..6fdffae 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: GPL-2.0
> -/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
>
>
> #include "msm_gem.h"
> @@ -378,6 +378,18 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> int ret;
>
> + /*
> + * During a previous slumber, GBIF halt is asserted to ensure
> + * no further transaction can go through GPU before GPU
> + * headswitch is turned off.
> + *
> + * This halt is deasserted once headswitch goes off but
> + * incase headswitch doesn't goes off clear GBIF halt
> + * here to ensure GPU wake-up doesn't fail because of
> + * halted GPU transactions.
> + */
> + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
> +
> /* Make sure the GMU keeps the GPU on while we set it up */
> a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
>
> @@ -406,12 +418,17 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
> gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
>
> - /* enable hardware clockgating */
> - a6xx_set_hwcg(gpu, true);
> + /*
> + * enable hardware clockgating
> + * For now enable clock gating only for a630
Why?
> + */
> + if (adreno_is_a630(adreno_gpu))
If you are going to skip clock gating, do it inside the function to avoid a
branch here and to avoid having two distinct locations to change to enable
HWCG for a given target.
> + a6xx_set_hwcg(gpu, true);
>
> - /* VBIF start */
> - gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
> + /* VBIF/GBIF start*/
> gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
> + if (adreno_is_a630(adreno_gpu))
> + gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
>
> /* Make all blocks contribute to the GPU BUSY perf counter */
> gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
> @@ -724,6 +741,39 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
> };
>
> +#define GBIF_CLIENT_HALT_MASK BIT(0)
> +#define GBIF_ARB_HALT_MASK BIT(1)
> +
> +static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
> +{
> + struct msm_gpu *gpu = &adreno_gpu->base;
> +
> + if(!a6xx_has_gbif(adreno_gpu)){
This should be adreno_is_a630. There is a good argument that this code should
should live in its own function but I'll leave that up to you. Regardless, put
a space before the {.
> + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
> + spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
> + 0xf) == 0xf);
> + gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
> +
> + return;
> + }
> +
> + /* Halt new client requests on GBIF */
> + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
> + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
> + (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
> +
> + /* Halt all AXI requests on GBIF */
> + gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
> + spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
> + (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
> +
> + /*
> + * GMU needs DDR access in slumber path. Deassert GBIF halt now
> + * to allow for GMU to access system memory.
> + */
> + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
> +}
> +
> static int a6xx_pm_resume(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> @@ -748,6 +798,16 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
>
> devfreq_suspend_device(gpu->devfreq.devfreq);
>
> + /*
> + * Make sure the GMU is idle before continuing (because some transitions
> + * may use VBIF
> + */
> + a6xx_gmu_wait_for_idle(&a6xx_gpu->gmu);
> +
> + /* Clear the VBIF pipe before shutting down */
> + /* FIXME: This accesses the GPU - do we need to make sure it is on? */
You should know that it is active if you make it out of wait for idle, and the
function only accesses CX so you don't need to worry about IFPC.
> + a6xx_bus_clear_pending_transactions(adreno_gpu);
> +
> return a6xx_gmu_stop(a6xx_gpu);
> }
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index 6439955..7239b8b 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -1,5 +1,5 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> -/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
> +/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
>
> #ifndef __A6XX_GPU_H__
> #define __A6XX_GPU_H__
> @@ -42,6 +42,13 @@ struct a6xx_gpu {
> #define A6XX_PROTECT_RDONLY(_reg, _len) \
> ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
>
> +static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
> +{
> + if(adreno_is_a630(gpu))
> + return false;
> +
> + return true;
> +}
This macro isn't needed - adreno_is_a630 is a sufficient check because we know
that VBIF died with a630.
>
> int a6xx_gmu_resume(struct a6xx_gpu *gpu);
> int a6xx_gmu_stop(struct a6xx_gpu *gpu);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index c7441fb..e12d5a9 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -3,7 +3,7 @@
> * Copyright (C) 2013 Red Hat
> * Author: Rob Clark <robdclark@gmail.com>
> *
> - * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
> */
>
> #ifndef __ADRENO_GPU_H__
> @@ -216,6 +216,16 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
> return gpu->revn == 540;
> }
>
> +static inline int adreno_is_a618(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 618;
> +}
> +
> +static inline int adreno_is_a630(struct adreno_gpu *gpu)
> +{
> + return gpu->revn == 630;
> +}
> +
> int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
> const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
> const char *fwname);
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 9+ messages in thread