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From: Prasad Malisetty <pmaliset@codeaurora.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <swboyd@chromium.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	mgautam@codeaurora.org, dianders@chromium.org, mka@chromium.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes
Date: Tue, 15 Jun 2021 10:56:03 +0530	[thread overview]
Message-ID: <108a693b952c6dd84f60130f83a572d7@codeaurora.org> (raw)
In-Reply-To: <YLxI3NTvgTJ3qt7h@builder.lan>

On 2021-06-06 09:32, Bjorn Andersson wrote:
> On Fri 04 Jun 16:43 CDT 2021, Stephen Boyd wrote:
> 
>> Quoting Prasad Malisetty (2021-05-21 02:57:00)
>> > On 2021-05-08 01:36, Stephen Boyd wrote:
>> > > Quoting Prasad Malisetty (2021-05-07 03:17:27)
>> > >> Add PCIe controller and PHY nodes for sc7280 SOC.
>> > >>
>> > >> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
>> > >> ---
>> > >>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 138
>> > >> +++++++++++++++++++++++++++++++++++
>> > >>  1 file changed, 138 insertions(+)
>> > >>
>> > >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > >> index 2cc4785..a9f25fc1 100644
>> > >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > >> @@ -12,6 +12,7 @@
>> > >>  #include <dt-bindings/power/qcom-aoss-qmp.h>
>> > >>  #include <dt-bindings/power/qcom-rpmpd.h>
>> > >>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> > >> +#include <dt-bindings/gpio/gpio.h>
>> > >>
>> > >>  / {
>> > >>         interrupt-parent = <&intc>;
>> > >> @@ -316,6 +317,118 @@
>> > >>                         };
>> > >>                 };
>> > >>
>> > > [...]
>> > >> +
>> > >> +               pcie1_phy: phy@1c0e000 {
>> > >> +                       compatible =
>> > >> "qcom,sm8250-qmp-gen3x2-pcie-phy";
>> > >> +                       reg = <0 0x01c0e000 0 0x1c0>;
>> > >> +                       #address-cells = <2>;
>> > >> +                       #size-cells = <2>;
>> > >> +                       ranges;
>> > >> +                       clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
>> > >> +                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
>> > >> +                                <&gcc GCC_PCIE_CLKREF_EN>,
>> > >> +                                <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
>> > >> +                       clock-names = "aux", "cfg_ahb", "ref",
>> > >> "refgen";
>> > >> +
>> > >> +                       resets = <&gcc GCC_PCIE_1_PHY_BCR>;
>> > >> +                       reset-names = "phy";
>> > >> +
>> > >> +                       assigned-clocks = <&gcc
>> > >> GCC_PCIE1_PHY_RCHNG_CLK>;
>> > >> +                       assigned-clock-rates = <100000000>;
>> > >> +
>> > >> +                       status = "disabled";
>> > >
>> > > I think the style is to put status disabled close to the compatible?
>> >
>> > Generally I have added status disabled in end as like many nodes. just
>> > curious to ask is there any specific reason to put close to compatible.
>> 
>> It's really up to qcom maintainers, which I am not.
>> 
> 
> I like when it's the last item, as it lends itself nicely to be
> surrounded by empty lines and thereby easy to spot...
> 
>> Sure, I will change as like previous one.

> Regards,
> Bjorn
> 
>> > >> +                               };
>> > >> +
>> > >> +                               reset-n {
>> > >> +                                       pins = "gpio2";
>> > >> +                                       function = "gpio";
>> > >> +
>> > >> +                                       drive-strength = <16>;
>> > >> +                                       output-low;
>> > >> +                                       bias-disable;
>> > >> +                               };
>> > >> +
>> > >> +                               wake-n {
>> > >> +                                       pins = "gpio3";
>> > >> +                                       function = "gpio";
>> > >> +
>> > >> +                                       drive-strength = <2>;
>> > >> +                                       bias-pull-up;
>> > >> +                               };
>> > >
>> > > These last two nodes with the pull-up and drive-strength settings
>> > > should
>> > > be in the board files, like the idp one, instead of here in the SoC
>> > > file. That way board designers can take the SoC and connect the pcie to
>> > > an external device using these pins and set the configuration they want
>> > > on these pins, or choose not to connect them to the SoC at all and use
>> > > those pins for something else.
>> > >
>> > > In addition, it looks like the reset could be a reset-gpios property
>> > > instead of an output-low config.
>> > >
>> > we are using reset property as perst gpio in pcie node.
>> 
>> Ok, perst-gpios should be fine. Presumably perst-gpios should be in 
>> the
>> board and not in the SoC because of what I wrote up above.

>> Sure, I will move perst into board specific file

  reply	other threads:[~2021-06-15  5:26 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-07 10:17 [PATCH 0/3] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
2021-05-07 10:17 ` [PATCH 1/3] dt-bindings: pci: qcom: Document PCIe bindings for SC720 Prasad Malisetty
2021-05-07 19:59   ` Stephen Boyd
2021-06-04 11:26     ` Prasad Malisetty
2021-06-04 21:44       ` Stephen Boyd
2021-05-10 15:48   ` Rob Herring
2021-05-07 10:17 ` [PATCH 2/3] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
2021-05-07 20:06   ` Stephen Boyd
2021-05-21  9:57     ` Prasad Malisetty
2021-06-04 21:43       ` Stephen Boyd
2021-06-06  4:02         ` Bjorn Andersson
2021-06-15  5:26           ` Prasad Malisetty [this message]
2021-05-07 10:17 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Prasad Malisetty

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