From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FDBFC433ED for ; Mon, 3 May 2021 23:56:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6873B61177 for ; Mon, 3 May 2021 23:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229602AbhECX5P (ORCPT ); Mon, 3 May 2021 19:57:15 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:23488 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229603AbhECX5O (ORCPT ); Mon, 3 May 2021 19:57:14 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1620086181; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=piSiT9kDksxiHfZ76iqY3kE19gY3ObsqvOI9b3fVh1w=; b=bXI/Q0B8mQaDfP7AnTV8nQyTmxwywCJNVlUpJ9Znc9u314zSQBK7PJ2BlPpBNxeRs0B5n9kN MmaDUMCBLamEsCIJv6xRZOMnbFsJ8svlwQ0XamZfxTRTocEZNHnp4yB6K66BU+dhq7HNJeAr MbbCURReB2k5wgKWrlTjIroAP8M= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 60908d912cbba88980d49b0e (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 03 May 2021 23:56:01 GMT Sender: hemantk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 8DC79C433F1; Mon, 3 May 2021 23:56:00 +0000 (UTC) Received: from [10.46.162.249] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: hemantk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 78341C433F1; Mon, 3 May 2021 23:55:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 78341C433F1 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=hemantk@codeaurora.org Subject: Re: [PATCH] mhi: add MHI_STATE_M2 to resume success criteria To: Baochen Qiang , manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, ath11k@lists.infradead.org References: <20210420035339.282963-1-bqiang@codeaurora.org> From: Hemant Kumar Message-ID: <11a51914-141d-24b6-cffa-4eb093aaea7f@codeaurora.org> Date: Mon, 3 May 2021 16:55:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210420035339.282963-1-bqiang@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 4/19/21 8:53 PM, Baochen Qiang wrote: > During system resume, mhi driver triggers M3->M0 transition and then waits > for target device to enter M0 state. Once done, the device queues a state > change event into ctrl event ring and notify mhi dirver by raising an > interrupt, where a tasklet is scheduled to process this event. In most cases, > the taklet is served timely and wait operation succeeds. > > However, there are cases where CPU is busy and can not serve this tasklet > for some time. Once delay goes long enough, the device moves itself to M1 > state and also interrupts mhi driver after inserting a new state change > event to ctrl ring. Later CPU finally has time to process the ring, however > there are two events in it now: > 1. for M3->M0 event, which is processed first as queued first, > tasklet handler updates device state to M0 and wakes up the task, > i.e., the mhi driver. > 2. for M0->M1 event, which is processed later, tasklet handler > triggers M1->M2 transition and updates device state to M2 directly, > then wakes up the mhi driver(if still sleeping on this wait queue). > Note that although mhi driver has been woken up while processing the first > event, it may still has no chance to run before the second event is processed. > In other words, mhi driver has to keep waiting till timeout cause the M0 state > has been missed. > > kernel log here: > ... > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.911251] mhi 0000:06:00.0: Entered with PM state: M3, MHI state: M3 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917762] mhi 0000:06:00.0: State change event to state: M0 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4247.917767] mhi 0000:06:00.0: State change event to state: M1 > Apr 15 01:45:14 test-NUC8i7HVK kernel: [ 4338.788231] mhi 0000:06:00.0: Did not enter M0 state, MHI state: M2, PM state: M2 > ... > > Fix this issue by simply adding M2 as a valid state for resume. > > Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 > > Signed-off-by: Baochen Qiang nice explanation of the issue! Reviewed-by: Hemant Kumar -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project