From: Taniya Das <tdas@codeaurora.org>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>
Cc: Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Taniya Das <tdas@codeaurora.org>
Subject: [PATCH v1 2/3] clk: qcom: rcg2: Add support for hardware control mode
Date: Wed, 8 May 2019 23:54:54 +0530 [thread overview]
Message-ID: <1557339895-21952-3-git-send-email-tdas@codeaurora.org> (raw)
In-Reply-To: <1557339895-21952-1-git-send-email-tdas@codeaurora.org>
Add a flag to indicate to support and enable hardware control mode
of an RCG.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/clk-rcg.h | 3 +++
drivers/clk/qcom/clk-rcg2.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index c25b57c..5562f38 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -139,6 +139,7 @@ struct clk_dyn_rcg {
* @freq_tbl: frequency table
* @clkr: regmap clock handle
* @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
+ * @flags: additional flag parameters for the RCG
*/
struct clk_rcg2 {
u32 cmd_rcgr;
@@ -149,6 +150,8 @@ struct clk_rcg2 {
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
u8 cfg_off;
+ u8 flags;
+#define HW_CLK_CTRL_MODE BIT(0)
};
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 57dbac9..5bb6d45 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -289,6 +289,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
if (rcg->mnd_width && f->n && (f->m != f->n))
cfg |= CFG_MODE_DUAL_EDGE;
+ if (rcg->flags & HW_CLK_CTRL_MODE)
+ cfg |= CFG_HW_CLK_CTRL_MASK;
+
return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
mask, cfg);
}
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
next prev parent reply other threads:[~2019-05-08 18:25 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-08 18:24 [PATCH v1 0/3] clk: qcom: Misc updates for Root Clock Generators Taniya Das
2019-05-08 18:24 ` [PATCH v1 1/3] clk: qcom: rcg: Return failure for RCG update Taniya Das
2019-07-15 22:52 ` Stephen Boyd
2019-05-08 18:24 ` Taniya Das [this message]
2019-07-15 22:52 ` [PATCH v1 2/3] clk: qcom: rcg2: Add support for hardware control mode Stephen Boyd
2019-07-16 4:19 ` Taniya Das
2019-07-16 23:18 ` Stephen Boyd
2019-07-30 10:50 ` Taniya Das
2019-07-30 15:38 ` Stephen Boyd
2019-05-08 18:24 ` [PATCH v1 3/3] clk: qcom: rcg: update the DFS macro for RCG Taniya Das
2019-05-09 17:27 ` Stephen Boyd
2019-05-10 2:58 ` Taniya Das
2019-05-10 17:54 ` Stephen Boyd
2019-05-13 3:44 ` Taniya Das
2019-07-15 22:44 ` Stephen Boyd
2019-07-16 4:22 ` Taniya Das
2019-07-16 23:22 ` Stephen Boyd
2019-07-30 10:51 ` Taniya Das
2019-07-30 15:40 ` Stephen Boyd
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