* [PATCH 0/6] Add minimal boot support for IPQ6018 @ 2019-06-05 17:28 Sricharan R 2019-06-05 17:28 ` [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Sricharan R ` (5 more replies) 0 siblings, 6 replies; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq6018-cp01 board. Sricharan R (6): pinctrl: qcom: Add ipq6018 pinctrl driver dt-bindings: qcom: Add ipq6018 bindings clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: Add ipq6018 Global Clock Controller support arm64: dts: Add ipq6018 SoC and CP01 board support arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Documentation/devicetree/bindings/arm/qcom.yaml | 2 + .../devicetree/bindings/clock/qcom,gcc.txt | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq6018.c | 5267 ++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 +++++ include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ 13 files changed, 7148 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq6018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R @ 2019-06-05 17:28 ` Sricharan R 2019-07-09 1:44 ` Rob Herring 2019-06-05 17:28 ` [PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings Sricharan R ` (4 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq6018. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> Signed-off-by: speriaka <speriaka@codeaurora.org> --- .../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 ++++++++++++++++++++ 4 files changed, 1380 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt new file mode 100644 index 0000000..5a3edb1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt @@ -0,0 +1,186 @@ +Qualcomm Technologies, Inc. IPQ6018 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +IPQ6018 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,ipq6018-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio121, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data, + qdsd_cmd, + qdsd_data0, + qdsd_data1, + qdsd_data2, + qdsd_data3 + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0, + atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en, + bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, + blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, + blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, + blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, + cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, + display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, + ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1, + gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en, + ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync, + pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a, + pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b, + qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0, + qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1, + qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int, + ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, + wcss_wlan, webcam1_rst + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq6018-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart2: uart2-default { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + tx { + pins = "gpio4"; + drive-strength = <4>; + bias-disable; + }; + + rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 890d0a3..c7b32e8 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -50,6 +50,16 @@ config PINCTRL_IPQ8074 Qualcomm Technologies Inc. IPQ8074 platform. Select this for IPQ8074. +config PINCTRL_IPQ6018 + tristate "Qualcomm Technologies, Inc. IPQ6018 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ6018 platform. Select this for + IPQ6018. + config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 344b4c6..0b8b769 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o +obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c new file mode 100644 index 0000000..cdc05af9 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -0,0 +1,1183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq6018_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); + +enum ipq6018_functions { + msm_mux_gpio, + msm_mux_blsp3_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_wci20, + msm_mux_qpic_pad, + msm_mux_burn0, + msm_mux_mac12, + msm_mux_qdss_tracectl_b, + msm_mux_burn1, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracedata_b, + msm_mux_mac01, + msm_mux_qpic_pad4, + msm_mux_mac21, + msm_mux_qpic_pad5, + msm_mux_qpic_pad6, + msm_mux_qpic_pad7, + msm_mux_atest_char, + msm_mux_cxc0, + msm_mux_mac13, + msm_mux_dbg_out, + msm_mux_wci22, + msm_mux_qpic_pad1, + msm_mux_qpic_pad2, + msm_mux_qpic_pad3, + msm_mux_qpic_pad0, + msm_mux_qpic_pad8, + msm_mux_pwm00, + msm_mux_atest_char0, + msm_mux_wci23, + msm_mux_mac11, + msm_mux_pwm10, + msm_mux_atest_char1, + msm_mux_pwm20, + msm_mux_atest_char2, + msm_mux_pwm30, + msm_mux_atest_char3, + msm_mux_audio_txmclk, + msm_mux_audio_txmclkin, + msm_mux_pwm02, + msm_mux_tx_swrm0, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_audio_txbclk, + msm_mux_pwm12, + msm_mux_wsa_swrm, + msm_mux_tx_swrm1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_audio_txfsync, + msm_mux_pwm22, + msm_mux_tx_swrm2, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_audio0, + msm_mux_pwm32, + msm_mux_tx_swrm, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_audio1, + msm_mux_pwm04, + msm_mux_audio2, + msm_mux_pwm14, + msm_mux_audio3, + msm_mux_pwm24, + msm_mux_audio_rxmclk, + msm_mux_audio_rxmclkin, + msm_mux_pwm03, + msm_mux_lpass_pdm, + msm_mux_lpass_aud, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_audio_rxbclk, + msm_mux_pwm13, + msm_mux_lpass_aud0, + msm_mux_rx_swrm, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_audio_rxfsync, + msm_mux_pwm23, + msm_mux_lpass_aud1, + msm_mux_rx_swrm0, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_pwm33, + msm_mux_lpass_aud2, + msm_mux_rx_swrm1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_lpass_pcm, + msm_mux_mac10, + msm_mux_mac00, + msm_mux_mac20, + msm_mux_blsp0_uart, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp2_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp5_i2c, + msm_mux_blsp5_uart, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_tracectl_a, + msm_mux_pwm01, + msm_mux_pta1_1, + msm_mux_pwm11, + msm_mux_rx1, + msm_mux_pta1_2, + msm_mux_pwm21, + msm_mux_pta1_0, + msm_mux_pwm31, + msm_mux_prng_rosc, + msm_mux_blsp4_uart, + msm_mux_blsp4_i2c, + msm_mux_blsp4_spi, + msm_mux_pcie0_clk, + msm_mux_cri_trng0, + msm_mux_pcie0_rst, + msm_mux_cri_trng1, + msm_mux_pcie0_wake, + msm_mux_cri_trng, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_rx0, + msm_mux_tsens_max, + msm_mux_mdc, + msm_mux_qdss_tracedata_a, + msm_mux_mdio, + msm_mux_pta2_0, + msm_mux_wci21, + msm_mux_cxc1, + msm_mux_pta2_1, + msm_mux_pta2_2, + msm_mux_blsp1_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_NA, +}; + +static const char * const blsp3_uart_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", +}; + +static const char * const blsp3_i2c_groups[] = { + "gpio73", "gpio74", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", "gpio79", +}; + +static const char * const wci20_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const qpic_pad_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10", + "gpio11", "gpio17", +}; + +static const char * const burn0_groups[] = { + "gpio0", +}; + +static const char * const mac12_groups[] = { + "gpio1", "gpio11", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio1", +}; + +static const char * const burn1_groups[] = { + "gpio1", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio0", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", +}; + +static const char * const mac01_groups[] = { + "gpio3", "gpio4", +}; + +static const char * const qpic_pad4_groups[] = { + "gpio5", +}; + +static const char * const mac21_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const qpic_pad5_groups[] = { + "gpio6", +}; + +static const char * const qpic_pad6_groups[] = { + "gpio7", +}; + +static const char * const qpic_pad7_groups[] = { + "gpio8", +}; + +static const char * const atest_char_groups[] = { + "gpio9", +}; + +static const char * const cxc0_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const mac13_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const dbg_out_groups[] = { + "gpio9", +}; + +static const char * const wci22_groups[] = { + "gpio11", "gpio17", +}; + +static const char * const qpic_pad1_groups[] = { + "gpio12", +}; + +static const char * const qpic_pad2_groups[] = { + "gpio13", +}; + +static const char * const qpic_pad3_groups[] = { + "gpio14", +}; + +static const char * const qpic_pad0_groups[] = { + "gpio15", +}; + +static const char * const qpic_pad8_groups[] = { + "gpio16", +}; + +static const char * const pwm00_groups[] = { + "gpio18", +}; + +static const char * const atest_char0_groups[] = { + "gpio18", +}; + +static const char * const wci23_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const mac11_groups[] = { + "gpio18", "gpio19", +}; + +static const char * const pwm10_groups[] = { + "gpio19", +}; + +static const char * const atest_char1_groups[] = { + "gpio19", +}; + +static const char * const pwm20_groups[] = { + "gpio20", +}; + +static const char * const atest_char2_groups[] = { + "gpio20", +}; + +static const char * const pwm30_groups[] = { + "gpio21", +}; + +static const char * const atest_char3_groups[] = { + "gpio21", +}; + +static const char * const audio_txmclk_groups[] = { + "gpio22", +}; + +static const char * const audio_txmclkin_groups[] = { + "gpio22", +}; + +static const char * const pwm02_groups[] = { + "gpio22", +}; + +static const char * const tx_swrm0_groups[] = { + "gpio22", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio22", +}; + +static const char * const audio_txbclk_groups[] = { + "gpio23", +}; + +static const char * const pwm12_groups[] = { + "gpio23", +}; + +static const char * const wsa_swrm_groups[] = { + "gpio23", "gpio24", +}; + +static const char * const tx_swrm1_groups[] = { + "gpio23", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio23", +}; + +static const char * const audio_txfsync_groups[] = { + "gpio24", +}; + +static const char * const pwm22_groups[] = { + "gpio24", +}; + +static const char * const tx_swrm2_groups[] = { + "gpio24", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio24", +}; + +static const char * const audio0_groups[] = { + "gpio25", "gpio32", +}; + +static const char * const pwm32_groups[] = { + "gpio25", +}; + +static const char * const tx_swrm_groups[] = { + "gpio25", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio25", +}; + +static const char * const audio1_groups[] = { + "gpio26", "gpio33", +}; + +static const char * const pwm04_groups[] = { + "gpio26", +}; + +static const char * const audio2_groups[] = { + "gpio27", +}; + +static const char * const pwm14_groups[] = { + "gpio27", +}; + +static const char * const audio3_groups[] = { + "gpio28", +}; + +static const char * const pwm24_groups[] = { + "gpio28", +}; + +static const char * const audio_rxmclk_groups[] = { + "gpio29", +}; + +static const char * const audio_rxmclkin_groups[] = { + "gpio29", +}; + +static const char * const pwm03_groups[] = { + "gpio29", +}; + +static const char * const lpass_pdm_groups[] = { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const lpass_aud_groups[] = { + "gpio29", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio29", +}; + +static const char * const audio_rxbclk_groups[] = { + "gpio30", +}; + +static const char * const pwm13_groups[] = { + "gpio30", +}; + +static const char * const lpass_aud0_groups[] = { + "gpio30", +}; + +static const char * const rx_swrm_groups[] = { + "gpio30", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio30", +}; + +static const char * const audio_rxfsync_groups[] = { + "gpio31", +}; + +static const char * const pwm23_groups[] = { + "gpio31", +}; + +static const char * const lpass_aud1_groups[] = { + "gpio31", +}; + +static const char * const rx_swrm0_groups[] = { + "gpio31", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio31", +}; + +static const char * const pwm33_groups[] = { + "gpio32", +}; + +static const char * const lpass_aud2_groups[] = { + "gpio32", +}; + +static const char * const rx_swrm1_groups[] = { + "gpio32", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio32", +}; + +static const char * const lpass_pcm_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; + +static const char * const mac10_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const mac00_groups[] = { + "gpio34", "gpio35", +}; + +static const char * const mac20_groups[] = { + "gpio36", "gpio37", +}; + +static const char * const blsp0_uart_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio38", "gpio39", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp2_uart_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp2_i2c_groups[] = { + "gpio42", "gpio43", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp5_i2c_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const blsp5_uart_groups[] = { + "gpio48", "gpio49", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio48", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio49", +}; + +static const char * const pwm01_groups[] = { + "gpio50", +}; + +static const char * const pta1_1_groups[] = { + "gpio51", +}; + +static const char * const pwm11_groups[] = { + "gpio51", +}; + +static const char * const rx1_groups[] = { + "gpio51", +}; + +static const char * const pta1_2_groups[] = { + "gpio52", +}; + +static const char * const pwm21_groups[] = { + "gpio52", +}; + +static const char * const pta1_0_groups[] = { + "gpio53", +}; + +static const char * const pwm31_groups[] = { + "gpio53", +}; + +static const char * const prng_rosc_groups[] = { + "gpio53", +}; + +static const char * const blsp4_uart_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const blsp4_i2c_groups[] = { + "gpio55", "gpio56", +}; + +static const char * const blsp4_spi_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio59", +}; + +static const char * const cri_trng0_groups[] = { + "gpio59", +}; + +static const char * const pcie0_rst_groups[] = { + "gpio60", +}; + +static const char * const cri_trng1_groups[] = { + "gpio60", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio61", +}; + +static const char * const cri_trng_groups[] = { + "gpio61", +}; + +static const char * const sd_card_groups[] = { + "gpio62", +}; + +static const char * const sd_write_groups[] = { + "gpio63", +}; + +static const char * const rx0_groups[] = { + "gpio63", +}; + +static const char * const tsens_max_groups[] = { + "gpio63", +}; + +static const char * const mdc_groups[] = { + "gpio64", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; + +static const char * const mdio_groups[] = { + "gpio65", +}; + +static const char * const pta2_0_groups[] = { + "gpio66", +}; + +static const char * const wci21_groups[] = { + "gpio66", "gpio68", +}; + +static const char * const cxc1_groups[] = { + "gpio66", "gpio68", +}; + +static const char * const pta2_1_groups[] = { + "gpio67", +}; + +static const char * const pta2_2_groups[] = { + "gpio68", +}; + +static const char * const blsp1_uart_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; + +static const char * const blsp1_i2c_groups[] = { + "gpio69", "gpio70", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio69", "gpio71", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio70", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", +}; + +static const struct msm_function ipq6018_functions[] = { + FUNCTION(gpio), + FUNCTION(blsp3_uart), + FUNCTION(blsp3_i2c), + FUNCTION(blsp3_spi), + FUNCTION(wci20), + FUNCTION(qpic_pad), + FUNCTION(burn0), + FUNCTION(mac12), + FUNCTION(qdss_tracectl_b), + FUNCTION(burn1), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracedata_b), + FUNCTION(mac01), + FUNCTION(qpic_pad4), + FUNCTION(mac21), + FUNCTION(qpic_pad5), + FUNCTION(qpic_pad6), + FUNCTION(qpic_pad7), + FUNCTION(atest_char), + FUNCTION(cxc0), + FUNCTION(mac13), + FUNCTION(dbg_out), + FUNCTION(wci22), + FUNCTION(qpic_pad1), + FUNCTION(qpic_pad2), + FUNCTION(qpic_pad3), + FUNCTION(qpic_pad0), + FUNCTION(qpic_pad8), + FUNCTION(pwm00), + FUNCTION(atest_char0), + FUNCTION(wci23), + FUNCTION(mac11), + FUNCTION(pwm10), + FUNCTION(atest_char1), + FUNCTION(pwm20), + FUNCTION(atest_char2), + FUNCTION(pwm30), + FUNCTION(atest_char3), + FUNCTION(audio_txmclk), + FUNCTION(audio_txmclkin), + FUNCTION(pwm02), + FUNCTION(tx_swrm0), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(audio_txbclk), + FUNCTION(pwm12), + FUNCTION(wsa_swrm), + FUNCTION(tx_swrm1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(audio_txfsync), + FUNCTION(pwm22), + FUNCTION(tx_swrm2), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(audio0), + FUNCTION(pwm32), + FUNCTION(tx_swrm), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(audio1), + FUNCTION(pwm04), + FUNCTION(audio2), + FUNCTION(pwm14), + FUNCTION(audio3), + FUNCTION(pwm24), + FUNCTION(audio_rxmclk), + FUNCTION(audio_rxmclkin), + FUNCTION(pwm03), + FUNCTION(lpass_pdm), + FUNCTION(lpass_aud), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(audio_rxbclk), + FUNCTION(pwm13), + FUNCTION(lpass_aud0), + FUNCTION(rx_swrm), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(audio_rxfsync), + FUNCTION(pwm23), + FUNCTION(lpass_aud1), + FUNCTION(rx_swrm0), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(pwm33), + FUNCTION(lpass_aud2), + FUNCTION(rx_swrm1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(lpass_pcm), + FUNCTION(mac10), + FUNCTION(mac00), + FUNCTION(mac20), + FUNCTION(blsp0_uart), + FUNCTION(blsp0_i2c), + FUNCTION(blsp0_spi), + FUNCTION(blsp2_uart), + FUNCTION(blsp2_i2c), + FUNCTION(blsp2_spi), + FUNCTION(blsp5_i2c), + FUNCTION(blsp5_uart), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_tracectl_a), + FUNCTION(pwm01), + FUNCTION(pta1_1), + FUNCTION(pwm11), + FUNCTION(rx1), + FUNCTION(pta1_2), + FUNCTION(pwm21), + FUNCTION(pta1_0), + FUNCTION(pwm31), + FUNCTION(prng_rosc), + FUNCTION(blsp4_uart), + FUNCTION(blsp4_i2c), + FUNCTION(blsp4_spi), + FUNCTION(pcie0_clk), + FUNCTION(cri_trng0), + FUNCTION(pcie0_rst), + FUNCTION(cri_trng1), + FUNCTION(pcie0_wake), + FUNCTION(cri_trng), + FUNCTION(sd_card), + FUNCTION(sd_write), + FUNCTION(rx0), + FUNCTION(tsens_max), + FUNCTION(mdc), + FUNCTION(qdss_tracedata_a), + FUNCTION(mdio), + FUNCTION(pta2_0), + FUNCTION(wci21), + FUNCTION(cxc1), + FUNCTION(pta2_1), + FUNCTION(pta2_2), + FUNCTION(blsp1_uart), + FUNCTION(blsp1_i2c), + FUNCTION(blsp1_spi), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), +}; + +static const struct msm_pingroup ipq6018_groups[] = { + PINGROUP(0, qpic_pad, wci20, qdss_traceclk_b, NA, burn0, NA, NA, NA, + NA), + PINGROUP(1, qpic_pad, mac12, qdss_tracectl_b, NA, burn1, NA, NA, NA, + NA), + PINGROUP(2, qpic_pad, wci20, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(3, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(4, qpic_pad, mac01, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(5, qpic_pad4, mac21, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(6, qpic_pad5, mac21, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(7, qpic_pad6, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, qpic_pad7, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, qpic_pad, atest_char, cxc0, mac13, dbg_out, + qdss_tracedata_b, NA, NA, NA), + PINGROUP(10, qpic_pad, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, qpic_pad, wci22, mac12, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(12, qpic_pad1, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, qpic_pad2, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, qpic_pad3, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, qpic_pad0, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, qpic_pad8, cxc0, mac13, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(17, qpic_pad, qdss_tracedata_b, wci22, NA, NA, NA, NA, NA, NA), + PINGROUP(18, pwm00, atest_char0, wci23, mac11, NA, NA, NA, NA, NA), + PINGROUP(19, pwm10, atest_char1, wci23, mac11, NA, NA, NA, NA, NA), + PINGROUP(20, pwm20, atest_char2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, pwm30, atest_char3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, audio_txmclk, audio_txmclkin, pwm02, tx_swrm0, NA, + qdss_cti_trig_out_b0, NA, NA, NA), + PINGROUP(23, audio_txbclk, pwm12, wsa_swrm, tx_swrm1, NA, + qdss_cti_trig_in_b0, NA, NA, NA), + PINGROUP(24, audio_txfsync, pwm22, wsa_swrm, tx_swrm2, NA, + qdss_cti_trig_out_b1, NA, NA, NA), + PINGROUP(25, audio0, pwm32, tx_swrm, NA, qdss_cti_trig_in_b1, NA, NA, + NA, NA), + PINGROUP(26, audio1, pwm04, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, audio2, pwm14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, audio3, pwm24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, audio_rxmclk, audio_rxmclkin, pwm03, lpass_pdm, lpass_aud, + qdss_cti_trig_in_a1, NA, NA, NA), + PINGROUP(30, audio_rxbclk, pwm13, lpass_pdm, lpass_aud0, rx_swrm, NA, + qdss_cti_trig_out_a1, NA, NA), + PINGROUP(31, audio_rxfsync, pwm23, lpass_pdm, lpass_aud1, rx_swrm0, NA, + qdss_cti_trig_in_a0, NA, NA), + PINGROUP(32, audio0, pwm33, lpass_pdm, lpass_aud2, rx_swrm1, NA, + qdss_cti_trig_out_a0, NA, NA), + PINGROUP(33, audio1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, lpass_pcm, mac10, mac00, NA, NA, NA, NA, NA, NA), + PINGROUP(35, lpass_pcm, mac10, mac00, NA, NA, NA, NA, NA, NA), + PINGROUP(36, lpass_pcm, mac20, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, lpass_pcm, mac20, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(40, blsp0_uart, blsp0_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, blsp0_uart, blsp0_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, blsp2_uart, blsp2_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(43, blsp2_uart, blsp2_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(44, blsp2_uart, blsp2_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, blsp2_uart, blsp2_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, blsp5_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, blsp5_i2c, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, blsp5_uart, NA, qdss_traceclk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(49, blsp5_uart, NA, qdss_tracectl_a, NA, NA, NA, NA, NA, NA), + PINGROUP(50, pwm01, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA), + PINGROUP(52, pta1_2, pwm21, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, pta1_0, pwm31, prng_rosc, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(56, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(57, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, pcie0_clk, NA, NA, cri_trng0, NA, NA, NA, NA, NA), + PINGROUP(60, pcie0_rst, NA, NA, cri_trng1, NA, NA, NA, NA, NA), + PINGROUP(61, pcie0_wake, NA, NA, cri_trng, NA, NA, NA, NA, NA), + PINGROUP(62, sd_card, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, sd_write, rx0, NA, tsens_max, NA, NA, NA, NA, NA), + PINGROUP(64, mdc, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(65, mdio, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pta2_0, wci21, cxc1, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(67, pta2_1, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, pta2_2, wci21, cxc1, qdss_tracedata_a, NA, NA, NA, NA, NA), + PINGROUP(69, blsp1_uart, blsp1_i2c, blsp1_spi, gcc_plltest, + qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(70, blsp1_uart, blsp1_i2c, blsp1_spi, gcc_tlmm, + qdss_tracedata_a, NA, NA, NA, NA), + PINGROUP(71, blsp1_uart, blsp1_spi, gcc_plltest, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(72, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(73, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(74, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(75, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(76, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(77, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(78, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(79, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), +}; + +static const struct msm_pinctrl_soc_data ipq6018_pinctrl = { + .pins = ipq6018_pins, + .npins = ARRAY_SIZE(ipq6018_pins), + .functions = ipq6018_functions, + .nfunctions = ARRAY_SIZE(ipq6018_functions), + .groups = ipq6018_groups, + .ngroups = ARRAY_SIZE(ipq6018_groups), + .ngpios = 80, +}; + +static int ipq6018_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq6018_pinctrl); +} + +static const struct of_device_id ipq6018_pinctrl_of_match[] = { + { .compatible = "qcom,ipq6018-pinctrl", }, + { }, +}; + +static struct platform_driver ipq6018_pinctrl_driver = { + .driver = { + .name = "ipq6018-pinctrl", + .owner = THIS_MODULE, + .of_match_table = ipq6018_pinctrl_of_match, + }, + .probe = ipq6018_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq6018_pinctrl_init(void) +{ + return platform_driver_register(&ipq6018_pinctrl_driver); +} +arch_initcall(ipq6018_pinctrl_init); + +static void __exit ipq6018_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq6018_pinctrl_driver); +} +module_exit(ipq6018_pinctrl_exit); + +MODULE_DESCRIPTION("QTI ipq6018 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq6018_pinctrl_of_match); -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver 2019-06-05 17:28 ` [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Sricharan R @ 2019-07-09 1:44 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-09 1:44 UTC (permalink / raw) To: Sricharan R Cc: sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel On Wed, Jun 05, 2019 at 10:58:53PM +0530, Sricharan R wrote: > Add initial pinctrl driver to support pin configuration with > pinctrl framework for ipq6018. > > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org> > Signed-off-by: speriaka <speriaka@codeaurora.org> > --- > .../bindings/pinctrl/qcom,ipq6018-pinctrl.txt | 186 +++ Please split bindings to separate patch. Using DT schema would be nice. > drivers/pinctrl/qcom/Kconfig | 10 + > drivers/pinctrl/qcom/Makefile | 1 + > drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 ++++++++++++++++++++ > 4 files changed, 1380 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.txt > create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R 2019-06-05 17:28 ` [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Sricharan R @ 2019-06-05 17:28 ` Sricharan R 2019-06-05 17:28 ` [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller Sricharan R ` (3 subsequent siblings) 5 siblings, 0 replies; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: speriaka <speriaka@codeaurora.org> --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f6316ab..7b19028 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -36,6 +36,7 @@ description: | mdm9615 ipq8074 sdm845 + ipq6018 The 'board' element must be one of the following strings: @@ -45,6 +46,7 @@ description: | mtp sbc hk01 + cp01-c1 The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor> where the minor number may be omitted when it's zero, i.e. v1.0 is the same -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R 2019-06-05 17:28 ` [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Sricharan R 2019-06-05 17:28 ` [PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings Sricharan R @ 2019-06-05 17:28 ` Sricharan R 2019-07-09 1:45 ` Rob Herring 2019-06-05 17:28 ` [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support Sricharan R ` (2 subsequent siblings) 5 siblings, 1 reply; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Add the compatible strings and the include file for ipq6018 gcc clock controller. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: anusha <anusharao@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> --- .../devicetree/bindings/clock/qcom,gcc.txt | 1 + include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 +++++++++++++++++++++ 2 files changed, 406 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 8661c3c..40bb3de 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,gcc-ipq8064" "qcom,gcc-ipq4019" "qcom,gcc-ipq8074" + "qcom,gcc-ipq6018" "qcom,gcc-msm8660" "qcom,gcc-msm8916" "qcom,gcc-msm8960" diff --git a/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/include/dt-bindings/clock/qcom,gcc-ipq6018.h new file mode 100644 index 0000000..b8aec10 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq6018.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H + +#define GPLL0 0 +#define UBI32_PLL 1 +#define GPLL6 2 +#define GPLL4 3 +#define PCNOC_BFDCD_CLK_SRC 4 +#define GPLL2 5 +#define NSS_CRYPTO_PLL 6 +#define NSS_PPE_CLK_SRC 7 +#define GCC_XO_CLK_SRC 8 +#define NSS_CE_CLK_SRC 9 +#define GCC_SLEEP_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define NSS_PORT5_RX_CLK_SRC 12 +#define NSS_PORT5_TX_CLK_SRC 13 +#define PCIE0_AXI_CLK_SRC 14 +#define USB0_MASTER_CLK_SRC 15 +#define APSS_AHB_POSTDIV_CLK_SRC 16 +#define NSS_PORT1_RX_CLK_SRC 17 +#define NSS_PORT1_TX_CLK_SRC 18 +#define NSS_PORT2_RX_CLK_SRC 19 +#define NSS_PORT2_TX_CLK_SRC 20 +#define NSS_PORT3_RX_CLK_SRC 21 +#define NSS_PORT3_TX_CLK_SRC 22 +#define NSS_PORT4_RX_CLK_SRC 23 +#define NSS_PORT4_TX_CLK_SRC 24 +#define NSS_PORT5_RX_DIV_CLK_SRC 25 +#define NSS_PORT5_TX_DIV_CLK_SRC 26 +#define APSS_AXI_CLK_SRC 27 +#define NSS_CRYPTO_CLK_SRC 28 +#define NSS_PORT1_RX_DIV_CLK_SRC 29 +#define NSS_PORT1_TX_DIV_CLK_SRC 30 +#define NSS_PORT2_RX_DIV_CLK_SRC 31 +#define NSS_PORT2_TX_DIV_CLK_SRC 32 +#define NSS_PORT3_RX_DIV_CLK_SRC 33 +#define NSS_PORT3_TX_DIV_CLK_SRC 34 +#define NSS_PORT4_RX_DIV_CLK_SRC 35 +#define NSS_PORT4_TX_DIV_CLK_SRC 36 +#define NSS_UBI0_CLK_SRC 37 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 +#define BLSP1_UART1_APPS_CLK_SRC 50 +#define BLSP1_UART2_APPS_CLK_SRC 51 +#define BLSP1_UART3_APPS_CLK_SRC 52 +#define BLSP1_UART4_APPS_CLK_SRC 53 +#define BLSP1_UART5_APPS_CLK_SRC 54 +#define BLSP1_UART6_APPS_CLK_SRC 55 +#define CRYPTO_CLK_SRC 56 +#define NSS_UBI0_DIV_CLK_SRC 57 +#define PCIE0_AUX_CLK_SRC 58 +#define PCIE0_PIPE_CLK_SRC 59 +#define SDCC1_APPS_CLK_SRC 60 +#define USB0_AUX_CLK_SRC 61 +#define USB0_MOCK_UTMI_CLK_SRC 62 +#define USB0_PIPE_CLK_SRC 63 +#define USB1_MOCK_UTMI_CLK_SRC 64 +#define GCC_APSS_AHB_CLK 65 +#define GCC_APSS_AXI_CLK 66 +#define GCC_BLSP1_AHB_CLK 67 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 +#define GCC_BLSP1_UART1_APPS_CLK 80 +#define GCC_BLSP1_UART2_APPS_CLK 81 +#define GCC_BLSP1_UART3_APPS_CLK 82 +#define GCC_BLSP1_UART4_APPS_CLK 83 +#define GCC_BLSP1_UART5_APPS_CLK 84 +#define GCC_BLSP1_UART6_APPS_CLK 85 +#define GCC_CRYPTO_AHB_CLK 86 +#define GCC_CRYPTO_AXI_CLK 87 +#define GCC_CRYPTO_CLK 88 +#define GCC_XO_CLK 89 +#define GCC_XO_DIV4_CLK 90 +#define GCC_MDIO_AHB_CLK 91 +#define GCC_CRYPTO_PPE_CLK 92 +#define GCC_NSS_CE_APB_CLK 93 +#define GCC_NSS_CE_AXI_CLK 94 +#define GCC_NSS_CFG_CLK 95 +#define GCC_NSS_CRYPTO_CLK 96 +#define GCC_NSS_CSR_CLK 97 +#define GCC_NSS_EDMA_CFG_CLK 98 +#define GCC_NSS_EDMA_CLK 99 +#define GCC_NSS_NOC_CLK 100 +#define GCC_NSS_PORT1_RX_CLK 101 +#define GCC_NSS_PORT1_TX_CLK 102 +#define GCC_NSS_PORT2_RX_CLK 103 +#define GCC_NSS_PORT2_TX_CLK 104 +#define GCC_NSS_PORT3_RX_CLK 105 +#define GCC_NSS_PORT3_TX_CLK 106 +#define GCC_NSS_PORT4_RX_CLK 107 +#define GCC_NSS_PORT4_TX_CLK 108 +#define GCC_NSS_PORT5_RX_CLK 109 +#define GCC_NSS_PORT5_TX_CLK 110 +#define GCC_NSS_PPE_CFG_CLK 111 +#define GCC_NSS_PPE_CLK 112 +#define GCC_NSS_PPE_IPE_CLK 113 +#define GCC_NSS_PTP_REF_CLK 114 +#define GCC_NSSNOC_CE_APB_CLK 115 +#define GCC_NSSNOC_CE_AXI_CLK 116 +#define GCC_NSSNOC_CRYPTO_CLK 117 +#define GCC_NSSNOC_PPE_CFG_CLK 118 +#define GCC_NSSNOC_PPE_CLK 119 +#define GCC_NSSNOC_QOSGEN_REF_CLK 120 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 121 +#define GCC_NSSNOC_UBI0_AHB_CLK 122 +#define GCC_PORT1_MAC_CLK 123 +#define GCC_PORT2_MAC_CLK 124 +#define GCC_PORT3_MAC_CLK 125 +#define GCC_PORT4_MAC_CLK 126 +#define GCC_PORT5_MAC_CLK 127 +#define GCC_UBI0_AHB_CLK 128 +#define GCC_UBI0_AXI_CLK 129 +#define GCC_UBI0_CORE_CLK 130 +#define GCC_PCIE0_AHB_CLK 131 +#define GCC_PCIE0_AUX_CLK 132 +#define GCC_PCIE0_AXI_M_CLK 133 +#define GCC_PCIE0_AXI_S_CLK 134 +#define GCC_PCIE0_PIPE_CLK 135 +#define GCC_PRNG_AHB_CLK 136 +#define GCC_QPIC_AHB_CLK 137 +#define GCC_QPIC_CLK 138 +#define GCC_SDCC1_AHB_CLK 139 +#define GCC_SDCC1_APPS_CLK 140 +#define GCC_UNIPHY0_AHB_CLK 141 +#define GCC_UNIPHY0_PORT1_RX_CLK 142 +#define GCC_UNIPHY0_PORT1_TX_CLK 143 +#define GCC_UNIPHY0_PORT2_RX_CLK 144 +#define GCC_UNIPHY0_PORT2_TX_CLK 145 +#define GCC_UNIPHY0_PORT3_RX_CLK 146 +#define GCC_UNIPHY0_PORT3_TX_CLK 147 +#define GCC_UNIPHY0_PORT4_RX_CLK 148 +#define GCC_UNIPHY0_PORT4_TX_CLK 149 +#define GCC_UNIPHY0_PORT5_RX_CLK 150 +#define GCC_UNIPHY0_PORT5_TX_CLK 151 +#define GCC_UNIPHY0_SYS_CLK 152 +#define GCC_UNIPHY1_AHB_CLK 153 +#define GCC_UNIPHY1_PORT5_RX_CLK 154 +#define GCC_UNIPHY1_PORT5_TX_CLK 155 +#define GCC_UNIPHY1_SYS_CLK 156 +#define GCC_USB0_AUX_CLK 157 +#define GCC_USB0_MASTER_CLK 158 +#define GCC_USB0_MOCK_UTMI_CLK 159 +#define GCC_USB0_PHY_CFG_AHB_CLK 160 +#define GCC_USB0_PIPE_CLK 161 +#define GCC_USB0_SLEEP_CLK 162 +#define GCC_USB1_MASTER_CLK 163 +#define GCC_USB1_MOCK_UTMI_CLK 164 +#define GCC_USB1_PHY_CFG_AHB_CLK 165 +#define GCC_USB1_SLEEP_CLK 166 +#define GP1_CLK_SRC 167 +#define GP2_CLK_SRC 168 +#define GP3_CLK_SRC 169 +#define GCC_GP1_CLK 170 +#define GCC_GP2_CLK 171 +#define GCC_GP3_CLK 172 +#define SYSTEM_NOC_BFDCD_CLK_SRC 173 +#define GCC_NSSNOC_SNOC_CLK 174 +#define GCC_UBI0_NC_AXI_CLK 175 +#define GCC_UBI1_NC_AXI_CLK 176 +#define GPLL0_MAIN 177 +#define UBI32_PLL_MAIN 178 +#define GPLL6_MAIN 179 +#define GPLL4_MAIN 180 +#define GPLL2_MAIN 181 +#define NSS_CRYPTO_PLL_MAIN 182 +#define GCC_CMN_12GPLL_AHB_CLK 183 +#define GCC_CMN_12GPLL_SYS_CLK 184 +#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 +#define GCC_SYS_NOC_USB0_AXI_CLK 186 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 187 +#define QDSS_TSCTR_CLK_SRC 188 +#define QDSS_AT_CLK_SRC 189 +#define GCC_QDSS_AT_CLK 190 +#define GCC_QDSS_DAP_CLK 191 +#define ADSS_PWM_CLK_SRC 192 +#define GCC_ADSS_PWM_CLK 193 +#define SDCC1_ICE_CORE_CLK_SRC 194 +#define GCC_SDCC1_ICE_CORE_CLK 195 +#define GCC_DCC_CLK 196 +#define PCIE0_RCHNG_CLK_SRC 197 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 +#define PCIE0_RCHNG_CLK 199 +#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 +#define WCSS_AHB_CLK_SRC 201 +#define Q6_AXI_CLK_SRC 202 +#define GCC_Q6SS_PCLKDBG_CLK 203 +#define GCC_Q6_TSCTR_1TO2_CLK 204 +#define GCC_WCSS_CORE_TBU_CLK 205 +#define GCC_WCSS_AXI_M_CLK 206 +#define GCC_SYS_NOC_WCSS_AHB_CLK 207 +#define GCC_Q6_AXIM_CLK 208 +#define GCC_Q6SS_ATBM_CLK 209 +#define GCC_WCSS_Q6_TBU_CLK 210 +#define GCC_Q6_AXIM2_CLK 211 +#define GCC_Q6_AHB_CLK 212 +#define GCC_Q6_AHB_S_CLK 213 +#define GCC_WCSS_DBG_IFC_APB_CLK 214 +#define GCC_WCSS_DBG_IFC_ATB_CLK 215 +#define GCC_WCSS_DBG_IFC_NTS_CLK 216 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 +#define GCC_WCSS_ECAHB_CLK 222 +#define GCC_WCSS_ACMT_CLK 223 +#define GCC_WCSS_AHB_S_CLK 224 +#define GCC_RBCPR_WCSS_CLK 225 +#define RBCPR_WCSS_CLK_SRC 226 +#define GCC_RBCPR_WCSS_AHB_CLK 227 +#define GCC_LPASS_CORE_AXIM_CLK 228 +#define GCC_LPASS_SNOC_CFG_CLK 229 +#define GCC_LPASS_Q6_AXIM_CLK 230 +#define GCC_LPASS_Q6_ATBM_AT_CLK 231 +#define GCC_LPASS_Q6_PCLKDBG_CLK 232 +#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 +#define GCC_LPASS_Q6SS_TRIG_CLK 234 +#define GCC_LPASS_TBU_CLK 235 +#define LPASS_CORE_AXIM_CLK_SRC 236 +#define LPASS_SNOC_CFG_CLK_SRC 237 +#define LPASS_Q6_AXIM_CLK_SRC 238 +#define GCC_PCNOC_LPASS_CLK 239 +#define GCC_UBI0_UTCM_CLK 240 +#define SNOC_NSSNOC_BFDCD_CLK_SRC 241 +#define GCC_SNOC_NSSNOC_CLK 242 +#define GCC_MEM_NOC_Q6_AXI_CLK 243 +#define GCC_MEM_NOC_UBI32_CLK 244 +#define GCC_MEM_NOC_LPASS_CLK 245 +#define GCC_SNOC_LPASS_CFG_CLK 246 + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_UART3_BCR 6 +#define GCC_BLSP1_QUP4_BCR 7 +#define GCC_BLSP1_UART4_BCR 8 +#define GCC_BLSP1_QUP5_BCR 9 +#define GCC_BLSP1_UART5_BCR 10 +#define GCC_BLSP1_QUP6_BCR 11 +#define GCC_BLSP1_UART6_BCR 12 +#define GCC_IMEM_BCR 13 +#define GCC_SMMU_BCR 14 +#define GCC_APSS_TCU_BCR 15 +#define GCC_SMMU_XPU_BCR 16 +#define GCC_PCNOC_TBU_BCR 17 +#define GCC_SMMU_CFG_BCR 18 +#define GCC_PRNG_BCR 19 +#define GCC_BOOT_ROM_BCR 20 +#define GCC_CRYPTO_BCR 21 +#define GCC_WCSS_BCR 22 +#define GCC_WCSS_Q6_BCR 23 +#define GCC_NSS_BCR 24 +#define GCC_SEC_CTRL_BCR 25 +#define GCC_DDRSS_BCR 26 +#define GCC_SYSTEM_NOC_BCR 27 +#define GCC_PCNOC_BCR 28 +#define GCC_TCSR_BCR 29 +#define GCC_QDSS_BCR 30 +#define GCC_DCD_BCR 31 +#define GCC_MSG_RAM_BCR 32 +#define GCC_MPM_BCR 33 +#define GCC_SPDM_BCR 34 +#define GCC_RBCPR_BCR 35 +#define GCC_RBCPR_MX_BCR 36 +#define GCC_TLMM_BCR 37 +#define GCC_RBCPR_WCSS_BCR 38 +#define GCC_USB0_PHY_BCR 39 +#define GCC_USB3PHY_0_PHY_BCR 40 +#define GCC_USB0_BCR 41 +#define GCC_USB1_BCR 42 +#define GCC_QUSB2_0_PHY_BCR 43 +#define GCC_QUSB2_1_PHY_BCR 44 +#define GCC_SDCC1_BCR 45 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 46 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 47 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 +#define GCC_UNIPHY0_BCR 59 +#define GCC_UNIPHY1_BCR 60 +#define GCC_CMN_12GPLL_BCR 61 +#define GCC_QPIC_BCR 62 +#define GCC_MDIO_BCR 63 +#define GCC_WCSS_CORE_TBU_BCR 64 +#define GCC_WCSS_Q6_TBU_BCR 65 +#define GCC_USB0_TBU_BCR 66 +#define GCC_PCIE0_TBU_BCR 67 +#define GCC_PCIE0_BCR 68 +#define GCC_PCIE0_PHY_BCR 69 +#define GCC_PCIE0PHY_PHY_BCR 70 +#define GCC_PCIE0_LINK_DOWN_BCR 71 +#define GCC_DCC_BCR 72 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 +#define GCC_SMMU_CATS_BCR 74 +#define GCC_UBI0_AXI_ARES 75 +#define GCC_UBI0_AHB_ARES 76 +#define GCC_UBI0_NC_AXI_ARES 77 +#define GCC_UBI0_DBG_ARES 78 +#define GCC_UBI0_CORE_CLAMP_ENABLE 79 +#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 +#define GCC_UBI0_UTCM_ARES 81 +#define GCC_NSS_CFG_ARES 82 +#define GCC_NSS_NOC_ARES 83 +#define GCC_NSS_CRYPTO_ARES 84 +#define GCC_NSS_CSR_ARES 85 +#define GCC_NSS_CE_APB_ARES 86 +#define GCC_NSS_CE_AXI_ARES 87 +#define GCC_NSSNOC_CE_APB_ARES 88 +#define GCC_NSSNOC_CE_AXI_ARES 89 +#define GCC_NSSNOC_UBI0_AHB_ARES 90 +#define GCC_NSSNOC_SNOC_ARES 91 +#define GCC_NSSNOC_CRYPTO_ARES 92 +#define GCC_NSSNOC_ATB_ARES 93 +#define GCC_NSSNOC_QOSGEN_REF_ARES 94 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 95 +#define GCC_PCIE0_PIPE_ARES 96 +#define GCC_PCIE0_SLEEP_ARES 97 +#define GCC_PCIE0_CORE_STICKY_ARES 98 +#define GCC_PCIE0_AXI_MASTER_ARES 99 +#define GCC_PCIE0_AXI_SLAVE_ARES 100 +#define GCC_PCIE0_AHB_ARES 101 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 +#define GCC_PPE_FULL_RESET 104 +#define GCC_UNIPHY0_SOFT_RESET 105 +#define GCC_UNIPHY0_XPCS_RESET 106 +#define GCC_UNIPHY1_SOFT_RESET 107 +#define GCC_UNIPHY1_XPCS_RESET 108 +#define GCC_EDMA_HW_RESET 109 +#define GCC_ADSS_BCR 110 +#define GCC_NSS_NOC_TBU_BCR 111 +#define GCC_NSSPORT1_RESET 112 +#define GCC_NSSPORT2_RESET 113 +#define GCC_NSSPORT3_RESET 114 +#define GCC_NSSPORT4_RESET 115 +#define GCC_NSSPORT5_RESET 116 +#define GCC_UNIPHY0_PORT1_ARES 117 +#define GCC_UNIPHY0_PORT2_ARES 118 +#define GCC_UNIPHY0_PORT3_ARES 119 +#define GCC_UNIPHY0_PORT4_ARES 120 +#define GCC_UNIPHY0_PORT5_ARES 121 +#define GCC_UNIPHY0_PORT_4_5_RESET 122 +#define GCC_UNIPHY0_PORT_4_RESET 123 +#define GCC_LPASS_BCR 124 +#define GCC_UBI32_TBU_BCR 125 +#define GCC_LPASS_TBU_BCR 126 +#define GCC_WCSSAON_RESET 127 +#define GCC_LPASS_Q6_AXIM_ARES 128 +#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 +#define GCC_LPASS_Q6SS_TRIG_ARES 130 +#define GCC_LPASS_Q6_ATBM_AT_ARES 131 +#define GCC_LPASS_Q6_PCLKDBG_ARES 132 +#define GCC_LPASS_CORE_AXIM_ARES 133 +#define GCC_LPASS_SNOC_CFG_ARES 134 +#define GCC_WCSS_DBG_ARES 135 +#define GCC_WCSS_ECAHB_ARES 136 +#define GCC_WCSS_ACMT_ARES 137 +#define GCC_WCSS_DBG_BDG_ARES 138 +#define GCC_WCSS_AHB_S_ARES 139 +#define GCC_WCSS_AXI_M_ARES 140 +#define GCC_Q6SS_DBG_ARES 141 +#define GCC_Q6_AHB_S_ARES 142 +#define GCC_Q6_AHB_ARES 143 +#define GCC_Q6_AXIM2_ARES 144 +#define GCC_Q6_AXIM_ARES 145 +#define GCC_UBI0_CORE_ARES 146 + +#endif -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller 2019-06-05 17:28 ` [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller Sricharan R @ 2019-07-09 1:45 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-09 1:45 UTC (permalink / raw) To: Sricharan R Cc: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel On Wed, 5 Jun 2019 22:58:55 +0530, Sricharan R wrote: > Add the compatible strings and the include file for ipq6018 > gcc clock controller. > > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > Signed-off-by: anusha <anusharao@codeaurora.org> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> > --- > .../devicetree/bindings/clock/qcom,gcc.txt | 1 + > include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 +++++++++++++++++++++ > 2 files changed, 406 insertions(+) > create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R ` (2 preceding siblings ...) 2019-06-05 17:28 ` [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller Sricharan R @ 2019-06-05 17:28 ` Sricharan R 2019-06-05 17:34 ` Sudeep Holla 2019-06-05 17:28 ` [PATCH 6/6] arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Sricharan R [not found] ` <1559755738-28643-5-git-send-email-sricharan@codeaurora.org> 5 siblings, 1 reply; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Add initial device tree support for the Qualcomm IPQ6018 SoC and CP01 evaluation board. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ 3 files changed, 267 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 21d548f..ac22dbb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts new file mode 100644 index 0000000..ac7cb22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IPQ6018 CP01 board device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq6018.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; + compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; + interrupt-parent = <&intc>; +}; + +&tlmm { + uart_pins: uart_pins { + mux { + pins = "gpio44", "gpio45"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +&blsp1_uart3 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi new file mode 100644 index 0000000..79cccdd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IPQ6018 SoC device tree source + * + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-ipq6018.h> + +/ { + model = "Qualcomm Technologies, Inc. IPQ6018"; + compatible = "qcom,ipq6018"; + + chosen { + bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; + bootargs-append = " swiotlb=1 clk_ignore_unused"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz:tz@48500000 { + no-map; + reg = <0x0 0x48500000 0x0 0x00200000>; + }; + }; + + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + dma-ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0xb000000 0x1000>, <0xb002000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b120000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq6018"; + reg = <0x1800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + + blsp1_uart3: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b1000 0x200>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq6018-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 0xd0 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + + uart_pins: uart_pins { + pins = "gpio44", "gpio45"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus: cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + }; + + pmuv8: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + + bias_pll_cc_clk { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + + bias_pll_nss_noc_clk { + compatible = "fixed-clock"; + clock-frequency = <416500000>; + #clock-cells = <0>; + }; + + usb3phy_0_cc_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + }; +}; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support 2019-06-05 17:28 ` [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support Sricharan R @ 2019-06-05 17:34 ` Sudeep Holla 2019-06-08 2:44 ` Sricharan R 0 siblings, 1 reply; 15+ messages in thread From: Sudeep Holla @ 2019-06-05 17:34 UTC (permalink / raw) To: Sricharan R Cc: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel, Sudeep Holla On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote: > Add initial device tree support for the Qualcomm IPQ6018 SoC and > CP01 evaluation board. > > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ > 3 files changed, 267 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi > [...] > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x3>; > + next-level-cache = <&L2_0>; > + }; > + > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <0x2>; > + }; > + }; > + > + pmuv8: pmu { > + compatible = "arm,armv8-pmuv3"; We know these are Cortex-A53s, why not update these accordingly ? -- Regards, Sudeep ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support 2019-06-05 17:34 ` Sudeep Holla @ 2019-06-08 2:44 ` Sricharan R 0 siblings, 0 replies; 15+ messages in thread From: Sricharan R @ 2019-06-08 2:44 UTC (permalink / raw) To: Sudeep Holla Cc: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Hi Sudeep, On 6/5/2019 11:04 PM, Sudeep Holla wrote: > On Wed, Jun 05, 2019 at 10:58:57PM +0530, Sricharan R wrote: >> Add initial device tree support for the Qualcomm IPQ6018 SoC and >> CP01 evaluation board. >> >> Signed-off-by: Sricharan R <sricharan@codeaurora.org> >> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 ++++ >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 +++++++++++++++++++++++++++ >> 3 files changed, 267 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts >> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi >> > > [...] > >> + >> + CPU3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + enable-method = "psci"; >> + reg = <0x3>; >> + next-level-cache = <&L2_0>; >> + }; >> + >> + L2_0: l2-cache { >> + compatible = "cache"; >> + cache-level = <0x2>; >> + }; >> + }; >> + >> + pmuv8: pmu { >> + compatible = "arm,armv8-pmuv3"; > > We know these are Cortex-A53s, why not update these accordingly ? > Ok, will change this. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 6/6] arm64: defconfig: Enable qcom ipq6018 clock and pinctrl 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R ` (3 preceding siblings ...) 2019-06-05 17:28 ` [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support Sricharan R @ 2019-06-05 17:28 ` Sricharan R [not found] ` <1559755738-28643-5-git-send-email-sricharan@codeaurora.org> 5 siblings, 0 replies; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:28 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel These configs are required for booting kernel in qcom ipq6018 boards. Signed-off-by: Sricharan R <sricharan@codeaurora.org> --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4d58351..abf64ee 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -373,6 +373,7 @@ CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8994=y CONFIG_PINCTRL_MSM8996=y @@ -646,6 +647,7 @@ CONFIG_COMMON_CLK_QCOM=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_GCC_8074=y +CONFIG_IPQ_GCC_6018=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 15+ messages in thread
[parent not found: <1559755738-28643-5-git-send-email-sricharan@codeaurora.org>]
* Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support [not found] ` <1559755738-28643-5-git-send-email-sricharan@codeaurora.org> @ 2019-06-10 15:22 ` Stephen Boyd 2019-12-19 10:26 ` Sricharan R 0 siblings, 1 reply; 15+ messages in thread From: Stephen Boyd @ 2019-06-10 15:22 UTC (permalink / raw) To: Sricharan R, agross, devicetree, linus.walleij, linux-arm-kernel, linux-arm-msm, linux-clk, linux-gpio, linux-kernel, linux-soc, robh+dt Quoting Sricharan R (2019-06-05 10:28:56) > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index e1ff83c..e5fb091 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -120,6 +120,15 @@ config IPQ_GCC_8074 > i2c, USB, SD/eMMC, etc. Select this for the root clock > of ipq8074. > > +config IPQ_GCC_6018 > + tristate "IPQ6018 Global Clock Controller" > + depends on COMMON_CLK_QCOM Not sure I commented on this, but this should be removed. The whole thing is inside an if now. > + help > + Support for global clock controller on ipq6018 devices. > + Say Y if you want to use peripheral devices such as UART, SPI, > + i2c, USB, SD/eMMC, etc. Select this for the root clock > + of ipq6018. > + > config MSM_GCC_8660 > tristate "MSM8660 Global Clock Controller" > help > diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c > new file mode 100644 > index 0000000..9f4552b > --- /dev/null > +++ b/drivers/clk/qcom/gcc-ipq6018.c > @@ -0,0 +1,5267 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + */ > + > +#include <linux/kernel.h> > +#include <linux/err.h> > +#include <linux/platform_device.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/clk-provider.h> > +#include <linux/regmap.h> > + > +#include <linux/reset-controller.h> > +#include <dt-bindings/clock/qcom,gcc-ipq6018.h> > + > +#include "common.h" > +#include "clk-regmap.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-branch.h" > +#include "clk-alpha-pll.h" > +#include "clk-regmap-divider.h" > +#include "clk-regmap-mux.h" > +#include "reset.h" > + > +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } [...] > + > +static struct clk_alpha_pll gpll0_main = { > + .offset = 0x21000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > + .clkr = { > + .enable_reg = 0x0b000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll0_main", > + .parent_names = (const char *[]){ > + "xo" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_ops, > + .flags = CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + }, > + }, > +}; > + > +static struct clk_fixed_factor gpll0_out_main_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "gpll0_out_main_div2", > + .parent_names = (const char *[]){ > + "gpll0_main" > + }, > + .num_parents = 1, > + .ops = &clk_fixed_factor_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_alpha_pll_postdiv gpll0 = { > + .offset = 0x21000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll0", > + .parent_names = (const char *[]){ > + "gpll0_main" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_ro_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_alpha_pll ubi32_pll_main = { > + .offset = 0x25000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], > + .flags = SUPPORTS_DYNAMIC_UPDATE, > + .clkr = { > + .enable_reg = 0x0b000, > + .enable_mask = BIT(6), > + .hw.init = &(struct clk_init_data){ > + .name = "ubi32_pll_main", > + .parent_names = (const char *[]){ > + "xo" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > + }, > +}; > + > +static struct clk_alpha_pll_postdiv ubi32_pll = { > + .offset = 0x25000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], > + .width = 2, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "ubi32_pll", > + .parent_names = (const char *[]){ > + "ubi32_pll_main" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_ro_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_alpha_pll gpll6_main = { > + .offset = 0x37000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], > + .clkr = { > + .enable_reg = 0x0b000, > + .enable_mask = BIT(7), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll6_main", > + .parent_names = (const char *[]){ > + "xo" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_ops, > + .flags = CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + }, > + }, > +}; > + > +static struct clk_alpha_pll_postdiv gpll6 = { > + .offset = 0x37000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], > + .width = 2, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll6", > + .parent_names = (const char *[]){ > + "gpll6_main" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_ro_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_alpha_pll gpll4_main = { > + .offset = 0x24000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > + .clkr = { > + .enable_reg = 0x0b000, > + .enable_mask = BIT(5), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll4_main", > + .parent_names = (const char *[]){ > + "xo" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_ops, > + .flags = CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + }, > + }, > +}; > + > +static struct clk_alpha_pll_postdiv gpll4 = { > + .offset = 0x24000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll4", > + .parent_names = (const char *[]){ > + "gpll4_main" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_ro_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { > + F(24000000, P_XO, 1, 0, 0), > + F(50000000, P_GPLL0, 16, 0, 0), > + F(100000000, P_GPLL0, 8, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 pcnoc_bfdcd_clk_src = { > + .cmd_rcgr = 0x27000, > + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, > + .hid_width = 5, > + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "pcnoc_bfdcd_clk_src", > + .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, > + .num_parents = 3, > + .ops = &clk_rcg2_ops, > + .flags = CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + }, > +}; > + > +static struct clk_fixed_factor pcnoc_clk_src = { > + .mult = 1, > + .div = 1, > + .hw.init = &(struct clk_init_data){ > + .name = "pcnoc_clk_src", > + .parent_names = (const char *[]){ > + "pcnoc_bfdcd_clk_src" > + }, > + .num_parents = 1, > + .ops = &clk_fixed_factor_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_alpha_pll gpll2_main = { > + .offset = 0x4a000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > + .clkr = { > + .enable_reg = 0x0b000, > + .enable_mask = BIT(2), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll2_main", > + .parent_names = (const char *[]){ > + "xo" > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_ops, > + .flags = CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + }, > + }, > +}; > + [...] > + > +static struct clk_fixed_factor system_noc_clk_src = { > + .mult = 1, > + .div = 1, > + .hw.init = &(struct clk_init_data){ > + .name = "system_noc_clk_src", > + .parent_names = (const char *[]){ > + "system_noc_bfdcd_clk_src" > + }, > + .num_parents = 1, > + .ops = &clk_fixed_factor_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; What is the point of these fixed factor 1/1 clks? Just to rename things? Does it matter, or can we just specify system_noc_bfdcd_clk_src as the parent and drop this intermediate clk? > + > +static struct clk_branch gcc_sleep_clk_src = { > + .halt_reg = 0x30000, > + .clkr = { > + .enable_reg = 0x30000, > + .enable_mask = BIT(1), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_sleep_clk_src", > + .parent_names = (const char *[]){ > + "sleep_clk" > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + .flags = CLK_IS_CRITICAL, > + }, > + }, > +}; > + [...] > + > +static struct clk_branch gcc_qdss_at_clk = { > + .halt_reg = 0x29024, > + .clkr = { > + .enable_reg = 0x29024, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_qdss_at_clk", > + .parent_names = (const char *[]){ > + "qdss_at_clk_src" > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_qdss_dap_clk = { > + .halt_reg = 0x29084, > + .clkr = { > + .enable_reg = 0x29084, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_qdss_dap_clk", > + .parent_names = (const char *[]){ > + "qdss_dap_sync_clk_src" > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, Can you add a comment on why this is critical? > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_qpic_ahb_clk = { > + .halt_reg = 0x57024, > + .clkr = { > + .enable_reg = 0x57024, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_qpic_ahb_clk", > + .parent_names = (const char *[]){ > + "pcnoc_clk_src" > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + [...] > +static struct clk_branch gcc_dcc_clk = { > + .halt_reg = 0x77004, > + .clkr = { > + .enable_reg = 0x77004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_dcc_clk", > + .parent_names = (const char *[]){ > + "pcnoc_clk_src" > + }, Can you use the new method of specifying clk parents here? That will make this simpler. > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static const struct alpha_pll_config ubi32_pll_config = { > + .l = 0x3e, > + .alpha = 0x57, > + .config_ctl_val = 0x200d6aa8, > + .config_ctl_hi_val = 0x3c2, > + .main_output_mask = BIT(0), > + .aux_output_mask = BIT(1), > + .pre_div_val = 0x0, > + .pre_div_mask = BIT(12), > + .post_div_val = 0x0, > + .post_div_mask = GENMASK(9, 8), > +}; > + > +static const struct alpha_pll_config nss_crypto_pll_config = { > + .l = 0x32, > + .alpha = 0x0, > + .alpha_hi = 0x0, > + .config_ctl_val = 0x4001055b, > + .main_output_mask = BIT(0), > + .pre_div_val = 0x0, > + .pre_div_mask = GENMASK(14, 12), > + .post_div_val = 0x1 << 8, > + .post_div_mask = GENMASK(11, 8), > + .vco_mask = GENMASK(21, 20), > + .vco_val = 0x0, > + .alpha_en_mask = BIT(24), > +}; > + > +static struct clk_hw *gcc_ipq6018_hws[] = { It would be nice to trim this down to a list of 0. > + &gpll0_out_main_div2.hw, > + &pcnoc_clk_src.hw, > + &snoc_nssnoc_clk_src.hw, > + &system_noc_clk_src.hw, > + &gcc_xo_div4_clk_src.hw, > + &ubi32_mem_noc_clk_src.hw, > + &nss_ppe_cdiv_clk_src.hw, > + &gpll6_out_main_div2.hw, Why do we need this? Does anyone use it? > + &qdss_dap_sync_clk_src.hw, > + &qdss_tsctr_div2_clk_src.hw, > +}; > + ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support 2019-06-10 15:22 ` [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support Stephen Boyd @ 2019-12-19 10:26 ` Sricharan R 0 siblings, 0 replies; 15+ messages in thread From: Sricharan R @ 2019-12-19 10:26 UTC (permalink / raw) To: Stephen Boyd, agross, devicetree, linus.walleij, linux-arm-kernel, linux-arm-msm, linux-clk, linux-gpio, linux-kernel, linux-soc, robh+dt Hi Stephen, Sorry for the late response, started looking in to this again. On 6/10/2019 8:52 PM, Stephen Boyd wrote: > Quoting Sricharan R (2019-06-05 10:28:56) >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index e1ff83c..e5fb091 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -120,6 +120,15 @@ config IPQ_GCC_8074 >> i2c, USB, SD/eMMC, etc. Select this for the root clock >> of ipq8074. >> >> +config IPQ_GCC_6018 >> + tristate "IPQ6018 Global Clock Controller" >> + depends on COMMON_CLK_QCOM > > Not sure I commented on this, but this should be removed. The whole > thing is inside an if now. > ok, will change. >> + help >> + Support for global clock controller on ipq6018 devices. >> + Say Y if you want to use peripheral devices such as UART, SPI, >> + i2c, USB, SD/eMMC, etc. Select this for the root clock >> + of ipq6018. >> + >> config MSM_GCC_8660 >> tristate "MSM8660 Global Clock Controller" >> help >> diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c >> new file mode 100644 >> index 0000000..9f4552b >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-ipq6018.c >> @@ -0,0 +1,5267 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include <linux/kernel.h> >> +#include <linux/err.h> >> +#include <linux/platform_device.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_device.h> >> +#include <linux/clk-provider.h> >> +#include <linux/regmap.h> >> + >> +#include <linux/reset-controller.h> >> +#include <dt-bindings/clock/qcom,gcc-ipq6018.h> >> + >> +#include "common.h" >> +#include "clk-regmap.h" >> +#include "clk-pll.h" >> +#include "clk-rcg.h" >> +#include "clk-branch.h" >> +#include "clk-alpha-pll.h" >> +#include "clk-regmap-divider.h" >> +#include "clk-regmap-mux.h" >> +#include "reset.h" >> + >> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } > [...] >> + >> +static struct clk_alpha_pll gpll0_main = { >> + .offset = 0x21000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_main", >> + .parent_names = (const char *[]){ >> + "xo" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + .flags = CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > Need not be critical, will remove it here and in rest of the places as well. >> + }, >> + }, >> +}; >> + >> +static struct clk_fixed_factor gpll0_out_main_div2 = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_out_main_div2", >> + .parent_names = (const char *[]){ >> + "gpll0_main" >> + }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll0 = { >> + .offset = 0x21000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .width = 4, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gpll0", >> + .parent_names = (const char *[]){ >> + "gpll0_main" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ro_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_alpha_pll ubi32_pll_main = { >> + .offset = 0x25000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], >> + .flags = SUPPORTS_DYNAMIC_UPDATE, >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(6), >> + .hw.init = &(struct clk_init_data){ >> + .name = "ubi32_pll_main", >> + .parent_names = (const char *[]){ >> + "xo" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_huayra_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv ubi32_pll = { >> + .offset = 0x25000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA], >> + .width = 2, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ubi32_pll", >> + .parent_names = (const char *[]){ >> + "ubi32_pll_main" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ro_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll6_main = { >> + .offset = 0x37000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(7), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll6_main", >> + .parent_names = (const char *[]){ >> + "xo" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + .flags = CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll6 = { >> + .offset = 0x37000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO], >> + .width = 2, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gpll6", >> + .parent_names = (const char *[]){ >> + "gpll6_main" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ro_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll4_main = { >> + .offset = 0x24000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(5), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll4_main", >> + .parent_names = (const char *[]){ >> + "xo" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + .flags = CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll4 = { >> + .offset = 0x24000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .width = 4, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gpll4", >> + .parent_names = (const char *[]){ >> + "gpll4_main" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ro_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { >> + F(24000000, P_XO, 1, 0, 0), >> + F(50000000, P_GPLL0, 16, 0, 0), >> + F(100000000, P_GPLL0, 8, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = { >> + .cmd_rcgr = 0x27000, >> + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, >> + .hid_width = 5, >> + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "pcnoc_bfdcd_clk_src", >> + .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + .flags = CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + }, >> +}; >> + >> +static struct clk_fixed_factor pcnoc_clk_src = { >> + .mult = 1, >> + .div = 1, >> + .hw.init = &(struct clk_init_data){ >> + .name = "pcnoc_clk_src", >> + .parent_names = (const char *[]){ >> + "pcnoc_bfdcd_clk_src" >> + }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll2_main = { >> + .offset = 0x4a000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x0b000, >> + .enable_mask = BIT(2), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll2_main", >> + .parent_names = (const char *[]){ >> + "xo" >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + .flags = CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + }, >> + }, >> +}; >> + > [...] >> + >> +static struct clk_fixed_factor system_noc_clk_src = { >> + .mult = 1, >> + .div = 1, >> + .hw.init = &(struct clk_init_data){ >> + .name = "system_noc_clk_src", >> + .parent_names = (const char *[]){ >> + "system_noc_bfdcd_clk_src" >> + }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; > > What is the point of these fixed factor 1/1 clks? Just to rename things? > Does it matter, or can we just specify system_noc_bfdcd_clk_src as the > parent and drop this intermediate clk? > ok, will remove it. >> + >> +static struct clk_branch gcc_sleep_clk_src = { >> + .halt_reg = 0x30000, >> + .clkr = { >> + .enable_reg = 0x30000, >> + .enable_mask = BIT(1), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_sleep_clk_src", >> + .parent_names = (const char *[]){ >> + "sleep_clk" >> + }, >> + .num_parents = 1, >> + .ops = &clk_branch2_ops, >> + .flags = CLK_IS_CRITICAL, >> + }, >> + }, >> +}; >> + > [...] >> + >> +static struct clk_branch gcc_qdss_at_clk = { >> + .halt_reg = 0x29024, >> + .clkr = { >> + .enable_reg = 0x29024, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_qdss_at_clk", >> + .parent_names = (const char *[]){ >> + "qdss_at_clk_src" >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch gcc_qdss_dap_clk = { >> + .halt_reg = 0x29084, >> + .clkr = { >> + .enable_reg = 0x29084, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_qdss_dap_clk", >> + .parent_names = (const char *[]){ >> + "qdss_dap_sync_clk_src" >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > > Can you add a comment on why this is critical? > >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch gcc_qpic_ahb_clk = { >> + .halt_reg = 0x57024, >> + .clkr = { >> + .enable_reg = 0x57024, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_qpic_ahb_clk", >> + .parent_names = (const char *[]){ >> + "pcnoc_clk_src" >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + > [...] >> +static struct clk_branch gcc_dcc_clk = { >> + .halt_reg = 0x77004, >> + .clkr = { >> + .enable_reg = 0x77004, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_dcc_clk", >> + .parent_names = (const char *[]){ >> + "pcnoc_clk_src" >> + }, > > Can you use the new method of specifying clk parents here? That will > make this simpler. > ok, will use it. >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static const struct alpha_pll_config ubi32_pll_config = { >> + .l = 0x3e, >> + .alpha = 0x57, >> + .config_ctl_val = 0x200d6aa8, >> + .config_ctl_hi_val = 0x3c2, >> + .main_output_mask = BIT(0), >> + .aux_output_mask = BIT(1), >> + .pre_div_val = 0x0, >> + .pre_div_mask = BIT(12), >> + .post_div_val = 0x0, >> + .post_div_mask = GENMASK(9, 8), >> +}; >> + >> +static const struct alpha_pll_config nss_crypto_pll_config = { >> + .l = 0x32, >> + .alpha = 0x0, >> + .alpha_hi = 0x0, >> + .config_ctl_val = 0x4001055b, >> + .main_output_mask = BIT(0), >> + .pre_div_val = 0x0, >> + .pre_div_mask = GENMASK(14, 12), >> + .post_div_val = 0x1 << 8, >> + .post_div_mask = GENMASK(11, 8), >> + .vco_mask = GENMASK(21, 20), >> + .vco_val = 0x0, >> + .alpha_en_mask = BIT(24), >> +}; >> + >> +static struct clk_hw *gcc_ipq6018_hws[] = { > > It would be nice to trim this down to a list of 0. > >> + &gpll0_out_main_div2.hw, >> + &pcnoc_clk_src.hw, >> + &snoc_nssnoc_clk_src.hw, >> + &system_noc_clk_src.hw, >> + &gcc_xo_div4_clk_src.hw, >> + &ubi32_mem_noc_clk_src.hw, >> + &nss_ppe_cdiv_clk_src.hw, >> + &gpll6_out_main_div2.hw, > > Why do we need this? Does anyone use it? > Yes, will remove the fixed factor 1/1 parents from this list. But other div clks are still required. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/6] Add minimal boot support for IPQ6018 @ 2019-06-05 17:15 Sricharan R 2019-06-05 17:26 ` Sricharan R 2019-06-07 23:08 ` Linus Walleij 0 siblings, 2 replies; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:15 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq6018-cp01 board. Sricharan R (6): pinctrl: qcom: Add ipq6018 pinctrl driver dt-bindings: qcom: Add ipq6018 bindings clk: qcom: Add DT bindings for ipq6018 gcc clock controller clk: qcom: Add ipq6018 Global Clock Controller support arm64: dts: Add ipq6018 SoC and CP01 board support arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Documentation/devicetree/bindings/arm/qcom.yaml | 2 + .../devicetree/bindings/clock/qcom,gcc.txt | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq6018.c | 5267 ++++++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 +++++ include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ 13 files changed, 7148 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq6018.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/6] Add minimal boot support for IPQ6018 2019-06-05 17:15 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R @ 2019-06-05 17:26 ` Sricharan R 2019-06-07 23:08 ` Linus Walleij 1 sibling, 0 replies; 15+ messages in thread From: Sricharan R @ 2019-06-05 17:26 UTC (permalink / raw) To: robh+dt, sboyd, linus.walleij, agross, devicetree, linux-kernel, linux-clk, linux-gpio, linux-arm-msm, linux-soc, linux-arm-kernel Sorry, Got sboyd@codeaurora.org wrong. Will fix and repost Regards, Sricharan On 6/5/2019 10:45 PM, Sricharan R wrote: > The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, > Gateways and Access Points. > > This series adds minimal board boot support for ipq6018-cp01 > board. > > Sricharan R (6): > pinctrl: qcom: Add ipq6018 pinctrl driver > dt-bindings: qcom: Add ipq6018 bindings > clk: qcom: Add DT bindings for ipq6018 gcc clock controller > clk: qcom: Add ipq6018 Global Clock Controller support > arm64: dts: Add ipq6018 SoC and CP01 board support > arm64: defconfig: Enable qcom ipq6018 clock and pinctrl > > Documentation/devicetree/bindings/arm/qcom.yaml | 2 + > .../devicetree/bindings/clock/qcom,gcc.txt | 1 + > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 35 + > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 231 + > arch/arm64/configs/defconfig | 2 + > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-ipq6018.c | 5267 ++++++++++++++++++++ > drivers/pinctrl/qcom/Kconfig | 10 + > drivers/pinctrl/qcom/Makefile | 1 + > drivers/pinctrl/qcom/pinctrl-ipq6018.c | 1183 +++++ > include/dt-bindings/clock/qcom,gcc-ipq6018.h | 405 ++ > 13 files changed, 7148 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts > create mode 100644 arch/arm64/boot/dts/qcom/ipq6018.dtsi > create mode 100644 drivers/clk/qcom/gcc-ipq6018.c > create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq6018.c > create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq6018.h > -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/6] Add minimal boot support for IPQ6018 2019-06-05 17:15 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R 2019-06-05 17:26 ` Sricharan R @ 2019-06-07 23:08 ` Linus Walleij 1 sibling, 0 replies; 15+ messages in thread From: Linus Walleij @ 2019-06-07 23:08 UTC (permalink / raw) To: Sricharan R, Bjorn Andersson Cc: Rob Herring, Stephen Boyd, Andy Gross, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-kernel, linux-clk, open list:GPIO SUBSYSTEM, MSM, open list:ARM/QUALCOMM SUPPORT, Linux ARM On Wed, Jun 5, 2019 at 7:16 PM Sricharan R <sricharan@codeaurora.org> wrote: > The IPQ6018 is Qualcomm’s 802.11ax SoC for Routers, > Gateways and Access Points. > > This series adds minimal board boot support for ipq6018-cp01 > board. > > Sricharan R (6): > pinctrl: qcom: Add ipq6018 pinctrl driver > dt-bindings: qcom: Add ipq6018 bindings I'm happy to merge these two if I can get a review from Bjorn Andersson on them. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-12-19 10:26 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-06-05 17:28 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R 2019-06-05 17:28 ` [PATCH 1/6] pinctrl: qcom: Add ipq6018 pinctrl driver Sricharan R 2019-07-09 1:44 ` Rob Herring 2019-06-05 17:28 ` [PATCH 2/6] dt-bindings: qcom: Add ipq6018 bindings Sricharan R 2019-06-05 17:28 ` [PATCH 3/6] clk: qcom: Add DT bindings for ipq6018 gcc clock controller Sricharan R 2019-07-09 1:45 ` Rob Herring 2019-06-05 17:28 ` [PATCH 5/6] arm64: dts: Add ipq6018 SoC and CP01 board support Sricharan R 2019-06-05 17:34 ` Sudeep Holla 2019-06-08 2:44 ` Sricharan R 2019-06-05 17:28 ` [PATCH 6/6] arm64: defconfig: Enable qcom ipq6018 clock and pinctrl Sricharan R [not found] ` <1559755738-28643-5-git-send-email-sricharan@codeaurora.org> 2019-06-10 15:22 ` [PATCH 4/6] clk: qcom: Add ipq6018 Global Clock Controller support Stephen Boyd 2019-12-19 10:26 ` Sricharan R -- strict thread matches above, loose matches on Subject: below -- 2019-06-05 17:15 [PATCH 0/6] Add minimal boot support for IPQ6018 Sricharan R 2019-06-05 17:26 ` Sricharan R 2019-06-07 23:08 ` Linus Walleij
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