From: Wesley Cheng <wcheng@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de,
mgautam@codeaurora.org, vkoul@kernel.org, sboyd@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, jackp@codeaurora.org,
Wesley Cheng <wcheng@codeaurora.org>
Subject: [PATCH v9 4/5] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
Date: Tue, 5 May 2020 12:59:35 -0700 [thread overview]
Message-ID: <1588708776-16774-5-git-send-email-wcheng@codeaurora.org> (raw)
In-Reply-To: <1588708776-16774-1-git-send-email-wcheng@codeaurora.org>
The register map for SM8150 QMP USB SSPHY has moved
QPHY_POWER_DOWN_CONTROL to a different offset. Allow for
an offset in the register table to override default value
if it is a DP capable PHY.
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Manu Gautam <mgautam@codeaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index d62bd09..dec4a17 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -119,6 +119,7 @@ enum qphy_reg_layout {
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
+ QPHY_PCS_POWER_DOWN_CONTROL,
};
static const unsigned int msm8996_ufsphy_regs_layout[] = {
@@ -181,6 +182,7 @@ enum qphy_reg_layout {
[QPHY_SW_RESET] = 0x00,
[QPHY_START_CTRL] = 0x44,
[QPHY_PCS_STATUS] = 0x14,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
};
static const unsigned int sdm845_ufsphy_regs_layout[] = {
@@ -2030,11 +2032,18 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
}
- if (cfg->has_phy_com_ctrl)
+ if (cfg->has_phy_com_ctrl) {
qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
SW_PWRDN);
- else
- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ } else {
+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
+ qphy_setbits(pcs,
+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+ cfg->pwrdn_ctrl);
+ else
+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
+ cfg->pwrdn_ctrl);
+ }
/* Serdes configuration */
qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
@@ -2260,7 +2269,13 @@ static int qcom_qmp_phy_disable(struct phy *phy)
qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
/* Put PHY into POWER DOWN state: active low */
- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
+ cfg->pwrdn_ctrl);
+ } else {
+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
+ cfg->pwrdn_ctrl);
+ }
if (cfg->has_lane_rst)
reset_control_assert(qphy->lane_rst);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-05-05 19:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 19:59 [PATCH v9 0/5] Add SS/HS-USB changes for Qualcomm SM8150 chipset Wesley Cheng
2020-05-05 19:59 ` [PATCH v9 1/5] dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2 Wesley Cheng
2020-05-05 19:59 ` [PATCH v9 2/5] phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs Wesley Cheng
2020-05-05 19:59 ` [PATCH v9 3/5] phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Wesley Cheng
2020-05-05 19:59 ` Wesley Cheng [this message]
2020-05-05 19:59 ` [PATCH v9 5/5] phy: qcom-qmp: Rename UFS PCS QMP v4 registers Wesley Cheng
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