From: Sarthak Garg <sartgarg@codeaurora.org>
To: adrian.hunter@intel.com, ulf.hansson@linaro.org
Cc: vbadigan@codeaurora.org, stummala@codeaurora.org,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
Sarthak Garg <sartgarg@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS)
Subject: [PATCH V1 1/7] dt-bindings: mmc: Add information for DLL register properties
Date: Thu, 7 May 2020 13:32:08 +0530 [thread overview]
Message-ID: <1588838535-6050-2-git-send-email-sartgarg@codeaurora.org> (raw)
In-Reply-To: <1588838535-6050-1-git-send-email-sartgarg@codeaurora.org>
Add information regarding DLL register properties for getting target
specific configurations. These DLL register settings may vary from
target to target.
Also new compatible string value for sm8250 target.
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 5445931..b8e1d2b 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -17,6 +17,7 @@ Required properties:
"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
+ "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
@@ -46,6 +47,13 @@ Required properties:
"cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional)
+- qcom,ddr-config: Certain chipsets and platforms require particular settings
+ for the DDR_CONFIG register. Use this field to specify the register
+ value as per the Hardware Programming Guide.
+
+- qcom,dll-config: Chipset and Platform specific value. Use this field to
+ specify the DLL_CONFIG register value as per Hardware Programming Guide.
+
Example:
sdhc_1: sdhci@f9824900 {
@@ -63,6 +71,9 @@ Example:
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
+
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
};
sdhc_2: sdhci@f98a4900 {
@@ -80,4 +91,7 @@ Example:
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
};
--
2.7.4
next prev parent reply other threads:[~2020-05-07 8:04 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-07 8:02 [PATCH V1 0/7] Target specific DLL configuration for qcom SDHC Sarthak Garg
2020-05-07 8:02 ` Sarthak Garg [this message]
2020-05-15 2:50 ` [PATCH V1 1/7] dt-bindings: mmc: Add information for DLL register properties Rob Herring
2020-05-19 14:00 ` sartgarg
2020-05-20 11:33 ` Ulf Hansson
2020-05-07 8:02 ` [PATCH V1 2/7] mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 3/7] mmc: sdhci-msm: Update dll_config_3 as per HSR Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 4/7] mmc: sdhci-msm: Update DDR_CONFIG as per device tree file Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 5/7] mmc: sdhci-msm: Read and use DLL Config property from " Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 6/7] mmc: sdhci-msm: Introduce new ops to dump vendor specific registers Sarthak Garg
2020-05-07 8:02 ` [PATCH V1 7/7] mmc: sdhci-msm: dump vendor specific registers during error Sarthak Garg
2020-05-15 14:32 ` [PATCH V1 0/7] Target specific DLL configuration for qcom SDHC Adrian Hunter
2020-05-22 9:23 ` [PATCH V2 0/8] Board " Sarthak Garg
2020-05-22 9:32 ` Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 1/8] dt-bindings: mmc: Add new compatible string for sm8250 target Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 2/8] dt-bindings: mmc: Add information for DLL register properties Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 3/8] mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 4/8] mmc: sdhci-msm: Update dll_config_3 as per HSR Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 5/8] mmc: sdhci-msm: Update DDR_CONFIG as per device tree file Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 6/8] mmc: sdhci-msm: Read and use DLL Config property from " Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 7/8] mmc: sdhci-msm: Introduce new ops to dump vendor specific registers Sarthak Garg
2020-05-22 9:32 ` [PATCH V2 8/8] mmc: sdhci-msm: dump vendor specific registers during error Sarthak Garg
2020-05-25 8:47 ` [PATCH V2 0/8] Board specific DLL configuration for qcom SDHC Ulf Hansson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1588838535-6050-2-git-send-email-sartgarg@codeaurora.org \
--to=sartgarg@codeaurora.org \
--cc=adrian.hunter@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=stummala@codeaurora.org \
--cc=ulf.hansson@linaro.org \
--cc=vbadigan@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).