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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Taniya Das <tdas@codeaurora.org>
Cc: David Brown <david.brown@linaro.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andy Gross <agross@kernel.org>,
	devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org,
	Taniya Das <tdas@codeaurora.org>
Subject: Re: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Date: Tue, 13 Oct 2020 19:07:34 -0700
Message-ID: <160264125446.310579.18150875025884105137@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1602609110-11504-2-git-send-email-tdas@codeaurora.org>

Quoting Taniya Das (2020-10-13 10:11:48)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..17e1fc0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
>         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
> +
> +void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> +                       const struct alpha_pll_config *config)
> +{
> +       if (config->l)
> +               regmap_write(regmap, PLL_L_VAL(pll), config->l);

Maybe make a helper function for this too. That way we can't mix up the
if condition with the value in the write.

	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);

static void clk_alpha_pll_write_config(struct regmap *regmap,
				       unsigned int reg,
				       unsigned int val) {
	if (val)
		regmap_write(regmap, reg, val);
}

and how are we so lucky that zero isn't a value that we may need to
write?

> +
> +       if (config->alpha)
> +               regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> +       if (config->user_ctl_val)
> +               regmap_write(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
> +
> +       if (config->config_ctl_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL(pll),
> +                                               config->config_ctl_val);
> +
> +       if (config->config_ctl_hi_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> +                                               config->config_ctl_hi_val);
> +
> +       if (config->test_ctl_val)
> +               regmap_write(regmap, PLL_TEST_CTL(pll),
> +                                               config->test_ctl_val);
> +
> +       if (config->test_ctl_hi_val)
> +               regmap_write(regmap,  PLL_TEST_CTL_U(pll),
> +                                               config->test_ctl_hi_val);
> +}
> +EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
> +
> +static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
> +                                                       unsigned long prate)
> +{
> +       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> +       u32 l, alpha_width = pll_alpha_width(pll);
> +       unsigned long rrate, max = rate + PLL_RATE_MARGIN;
> +       u64 a;
> +
> +       rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
> +
> +       /*
> +        * Due to limited number of bits for fractional rate programming, the
> +        * rounded up rate could be marginally higher than the requested rate.
> +        */
> +       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
> +               pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
> +                      clk_hw_get_name(hw), rrate, rate, max);
> +               return -EINVAL;
> +       }

Can this be extracted into a helper function?

> +
> +       /* change L_VAL without having to go through the power on sequence */
> +       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> +
> +       if (clk_hw_is_enabled(hw))
> +               return wait_for_pll_enable_lock(pll);
> +
> +       return 0;
> +}
> +

  reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-13 17:11 [PATCH v2 0/3] Add Camera clock controller driver for SC7180 Taniya Das
2020-10-13 17:11 ` [PATCH v2 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs Taniya Das
2020-10-14  2:07   ` Stephen Boyd [this message]
2020-10-16 18:38     ` Taniya Das
2020-10-13 17:11 ` [PATCH v2 2/3] dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings Taniya Das
2020-10-14  2:09   ` Stephen Boyd
2020-10-16 18:39     ` Taniya Das
2020-10-16 17:25   ` Rob Herring
2020-10-13 17:11 ` [PATCH v2 3/3] clk: qcom: camcc: Add camera clock controller driver for SC7180 Taniya Das
2020-10-14  1:59   ` Stephen Boyd
2020-10-16 18:40     ` Taniya Das

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