From: Stephen Boyd <sboyd@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: mturquette@baylibre.com, robh+dt@kernel.org,
bjorn.andersson@linaro.org, vkoul@kernel.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Naveen Yadav <naveenky@codeaurora.org>
Subject: Re: [PATCH 2/4] clk: qcom: Add SDX55 GCC support
Date: Thu, 12 Nov 2020 23:58:18 -0800 [thread overview]
Message-ID: <160525429844.60232.2716300766254728207@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20201105085148.GA7308@work>
Quoting Manivannan Sadhasivam (2020-11-05 00:51:48)
> On Wed, Nov 04, 2020 at 06:23:37PM -0800, Stephen Boyd wrote:
> > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
> > > new file mode 100644
> > > index 000000000000..75831c829202
> > > --- /dev/null
> > > +++ b/drivers/clk/qcom/gcc-sdx55.c
> > > @@ -0,0 +1,1667 @@
> > > +
>
> [...]
>
> > > +static const struct clk_div_table post_div_table_lucid_even[] = {
> > > + { 0x0, 1 },
> > > + { 0x1, 2 },
> > > + { 0x3, 4 },
> > > + { 0x7, 8 },
> > > + { }
> > > +};
> >
> > I think this table is common to all lucid plls? Maybe we can push it
> > into the clk_ops somehow and stop duplicating it here?
> >
>
> Are you referring to lucid plls in this driver? Because, this table is
> not common for other SoCs. And I don't think having this way introduces
> any overhead, so I'd prefer keeping it as it is.
>
Yes all lucid type PLLs probably have the same divider table.
>
> > > +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
> > > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
> > > + .halt_reg = 0x4010,
> > > + .halt_check = BRANCH_HALT_VOTED,
> > > + .clkr = {
> > > + .enable_reg = 0x6d008,
> > > + .enable_mask = BIT(0),
> > > + .hw.init = &(struct clk_init_data){
> > > + .name = "gcc_sys_noc_cpuss_ahb_clk",
> > > + .parent_hws = (const struct clk_hw *[]){
> > > + &gcc_cpuss_ahb_clk_src.clkr.hw },
> > > + .num_parents = 1,
> > > + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
> >
> > These CLK_IS_CRITICAL clks can't be set once at driver probe time and
> > forgotten about? It would be nice to not allocate memory for things that
> > never matter.
> >
>
> Makes sense! But are we moving into the direction of deprecating the use
> of CLK_IS_CRITICAL?
No? Just judiciously using it.
next prev parent reply other threads:[~2020-11-13 7:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam
2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam
2020-10-30 19:22 ` Rob Herring
2020-10-31 3:29 ` Manivannan Sadhasivam
2020-11-05 2:03 ` Stephen Boyd
2020-10-28 7:42 ` [PATCH 2/4] clk: qcom: Add SDX55 GCC support Manivannan Sadhasivam
2020-11-05 2:23 ` Stephen Boyd
2020-11-05 8:51 ` Manivannan Sadhasivam
2020-11-13 7:58 ` Stephen Boyd [this message]
2020-10-28 7:42 ` [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 Manivannan Sadhasivam
2020-11-03 17:38 ` Bjorn Andersson
2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam
2020-11-03 17:53 ` Bjorn Andersson
2020-11-05 2:25 ` Stephen Boyd
2020-10-28 17:08 ` [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam
2020-11-03 17:34 ` Bjorn Andersson
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