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Fri, 5 Feb 2021 21:38:41 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47CA9C08ECA6 for ; Fri, 5 Feb 2021 14:34:47 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id b145so5279474pfb.4 for ; Fri, 05 Feb 2021 14:34:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:content-transfer-encoding:in-reply-to:references :subject:from:cc:to:date:message-id:user-agent; bh=XDX1Uk6gHPmMaIAVv43TEENxArIFJ9A9Ns9WicOR0qk=; b=CyZM3eAqRT+nH732eFHue3xRm40RDjX1zYxBD8x6nHigQMuAmuIEACdAeAZwT8R5Zk AFJ+I+Hbwj1dxB4d5qp8eJrJf45r8z6Jf9X+SkEnpvpxIItD9kAENQv5/vZAK3gmnjOf cza01OCZubvaxOXT26R0CVIMMOSK1HhNTNc4w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:content-transfer-encoding :in-reply-to:references:subject:from:cc:to:date:message-id :user-agent; bh=XDX1Uk6gHPmMaIAVv43TEENxArIFJ9A9Ns9WicOR0qk=; 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Or are some clks optional sometimes? > + items: > + - description: Display byte clock > + - description: Display byte interface clock > + - description: Display pixel clock > + - description: Display escape clock > + - description: Display AHB clock > + - description: Display AXI clock > + > + clock-names: > + items: > + - const: byte > + - const: byte_intf > + - const: pixel > + - const: core > + - const: iface > + - const: bus > + > + phys: > + minItems: 1 > + > + phy-names: > + const: dsi > + > + syscon-sfpb: > + description: A phandle to mmss_sfpb syscon node (only for DSIv2). > + $ref: "/schemas/types.yaml#/definitions/phandle" > + > + qcom,mdss-mdp-transfer-time-us: > + description: | > + Specifies the DSI transfer time for command mode > + panels in microseconds. Driver uses this number to adjust > + the clock rate according to the expected transfer time. > + Increasing this value would slow down the mdp processing > + and can result in slower performance. > + Decreasing this value can speed up the mdp processing, > + but this can also impact power consumption. > + As a rule this time should not be higher than the time > + that would be expected with the processing at the > + DSI link rate since anyways this would be the maximum > + transfer time that could be achieved. > + If ping pong split is enabled, this time should not be higher > + than two times the DSI link rate time. > + This is an optional property. > + default: 14000 Why is this in DT vs. being tweaked from userspace? This was there before but it isn't used anywhere in an upstream DTS file so please drop it. > + > + qcom,dual-dsi-mode: > + type: boolean > + description: | > + Indicates if the DSI controller is driving a panel which needs > + 2 DSI links. Shouldn't this be apparent from the OF graph indicating two DSI endpoints? > + > + qcom,master-dsi: > + type: boolean > + description: | > + Indicates if the DSI controller is driving the master link of > + the 2-DSI panel. When is this not the case? This property looks like some sort of workaround for driver probe ordering. It was there before though so I guess this is fine. > + > + qcom,sync-dual-dsi: > + type: boolean > + description: | > + Indicates if the DSI controller is driving a 2-DSI panel whose > + 2 links need receive command simultaneously. Feels like it should be a property of the panel node? > + > + ports: > + type: object > + description: | > + Contains DSI controller input and output ports as children, each > + containing one endpoint subnode as defined in > + Documentation/devicetree/bindings/graph.txt and > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + > + properties: > + port@0: > + type: object > + description: | > + Input endpoints of the controller. > + > + properties: > + reg: > + const: 0 > + > + endpoint: > + type: object > + properties: > + remote-endpoint: > + description: | > + For port@0, set to phandle of the connected panel/brid= ge's > + input endpoint. For port@1, set to the MDP interface o= utput. > + See Documentation/devicetree/bindings/graph.txt for > + device graph info. > + > + data-lanes: > + description: | > + This describes how the physical DSI data lanes are map= ped > + to the logical lanes on the given platform. The value = contained in > + index n describes what physical lane is mapped to the = logical lane n > + (DATAn, where n lies between 0 and 3). The clock lane = position is fixed > + and can't be changed. Hence, they aren't a part of the= DT bindings. See > + Documentation/devicetree/bindings/media/video-interfac= es.txt for > + more info on the data-lanes property. > + > + items: > + - const: 0 > + - const: 1 > + - const: 2 > + - const: 3 > + port@1: > + type: object > + description: | > + Output endpoints of the controller. > + properties: > + reg: > + const: 1 > + > + endpoint: > + type: object > + properties: > + remote-endpoint: true > + data-lanes: > + items: > + - const: 0 > + - const: 1 > + - const: 2 > + - const: 3 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - clocks > + - clock-names > + - phys > + - phy-names > + - ports > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + soc { > + #address-cells =3D <2>; > + #size-cells =3D <2>; The soc node can be left out. > + > + mdss@ae00000 { subsystem? > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + reg =3D <0 0xae00000 0 0x1000>; > + interrupt-controller; > + #interrupt-cells =3D <1>; > + > + dsi@ae94000 { > + compatible =3D "qcom,mdss-dsi-ctrl";