From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A91EDC433DB for ; Mon, 29 Mar 2021 21:09:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7406A6198E for ; Mon, 29 Mar 2021 21:09:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230526AbhC2VIo (ORCPT ); Mon, 29 Mar 2021 17:08:44 -0400 Received: from mail.kernel.org ([198.145.29.99]:54476 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230161AbhC2VIg (ORCPT ); Mon, 29 Mar 2021 17:08:36 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 154EC61987; Mon, 29 Mar 2021 21:08:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617052116; bh=H7oFD+Wy16D6yioU0LA4DZWPK5qlhfgz520Z+alPqNo=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=g48/jWSZO9tmh/95faqO1JanUlisIh6Wv6TCDK0VvK2pVaQf4jqDxxz/FLPplnWBF lfSr/KWd/jH/zd+zbtNHMsgb67/XPmnZdhYQXZdhtRbEPAbRxO17ksP5IVvrjGNAVE H0wQSVrK45dybbtt+DtDnP/nd0gYbgN+95oDiuQT43fYZWUGswUNZLfoQxIRDg7JFH f5fbv8V4EKHEtfgY2a5AWUqFz9KpF5SpTQMSKJl6eQL0XIeXv1O01Q6QLSCCJKp/hi S/vrKEBNk7cRyQtcQAQP3DpFgjiWVpPE2/dtFhsVbPCWcm4MnwExHhNezWHj94ylnw u3m3n98nr6+LA== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <1616809265-11912-1-git-send-email-tdas@codeaurora.org> References: <1616809265-11912-1-git-send-email-tdas@codeaurora.org> Subject: Re: [PATCH v2] clk: qcom: camcc: Update the clock ops for the SC7180 From: Stephen Boyd Cc: Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das To: Michael Turquette , Taniya Das Date: Mon, 29 Mar 2021 14:08:34 -0700 Message-ID: <161705211465.3012082.15103893459170781797@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Quoting Taniya Das (2021-03-26 18:41:05) > Some of the RCGs could be always ON from the XO source and could be used > as the clock on signal for the GDSC to be operational. In the cases where > the GDSCs are parked at different source with the source clock disabled, > it could lead to the GDSC to be stuck at ON/OFF during gdsc disable/enabl= e. > Thus park the RCGs at XO during clock disable and update the rcg_ops to > use the shared_ops. >=20 > Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller drive= r for SC7180") > Signed-off-by: Taniya Das > --- Applied to clk-fixes