From: Stephen Boyd <sboyd@kernel.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>,
phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
martin.botka@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Taniya Das <tdas@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver
Date: Wed, 31 Mar 2021 19:00:38 -0700 [thread overview]
Message-ID: <161724243841.2260335.10536109464664209719@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210225201845.109670-2-konrad.dybcio@somainline.org>
Quoting Konrad Dybcio (2021-02-25 12:18:43)
> diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c
> new file mode 100644
> index 000000000000..5478612cd1b3
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-msm8976.c
> @@ -0,0 +1,4181 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Qualcomm Global Clock Controller driver for MSM8956/76
> + *
> + * Copyright (c) 2016-2021, AngeloGioacchino Del Regno
> + * <angelogioacchino.delregno@somainline.org>
> + *
> + * Driver cleanup and modernization
> + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> + *
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
[....]
> +
> +static struct clk_pll gpll0 = {
> + .l_reg = 0x21004,
> + .m_reg = 0x21008,
> + .n_reg = 0x2100c,
> + .config_reg = 0x21014,
> + .mode_reg = 0x21000,
> + .status_reg = 0x2101c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "xo",
> + .name = "xo_board",
> + },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap gpll0_vote = {
> + .enable_reg = 0x45000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_vote",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_IS_CRITICAL,
Please add a comment why it is critical. I guess because the CPU is
using it?
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
[...]
> +
> +static struct clk_rcg2 apss_ahb_clk_src = {
> + .cmd_rcgr = 0x46000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_a,
> + .freq_tbl = ftbl_apss_ahb_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "apss_ahb_clk_src",
> + .parent_data = gcc_parent_data_8_a,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8_a),
> + .ops = &clk_rcg2_ops,
> + /*
> + * This clock allows the CPUs to communicate with
> + * the rest of the SoC. Without it, the brain will
> + * operate without the rest of the body.
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
Please remove this clk and set the bit to enable it at driver probe
instead.
> +
> +static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x200c,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup1_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
> + F(19200000, P_XO, 1, 0, 0),
> + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup1_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x3000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup2_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x3014,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup2_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x4000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup3_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x4024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup3_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x5000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup4_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x5024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup4_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
> + F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
> + F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
> + F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
> + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
> + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
> + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
> + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
> + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
> + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
> + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
> + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
> + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
> + F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x2044,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_uart1_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x3034,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_uart2_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0xc00c,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup1_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0xc024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup1_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0xd000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup2_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0xd014,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup2_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0xf000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup3_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0xf024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup3_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x18000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup4_i2c_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x18024,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup4_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> + .cmd_rcgr = 0xc044,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_uart1_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> + .cmd_rcgr = 0xd034,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_blsp_uart_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_uart2_apps_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_cci_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(37500000, P_GPLL0_AUX, 1, 3, 64),
> + { }
> +};
> +
> +static struct clk_rcg2 cci_clk_src = {
> + .cmd_rcgr = 0x51000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_cci,
> + .freq_tbl = ftbl_cci_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "cci_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_cpp_clk_src[] = {
> + F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
> + F(240000000, P_GPLL4_AUX, 5, 0, 0),
> + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
> + F(480000000, P_GPLL4_AUX, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 cpp_clk_src = {
> + .cmd_rcgr = 0x58018,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_cpp,
> + .freq_tbl = ftbl_cpp_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "cpp_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_csi0_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 csi0_clk_src = {
> + .cmd_rcgr = 0x4e020,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_csi0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "csi0_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_csi1_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 csi1_clk_src = {
> + .cmd_rcgr = 0x4f020,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_csi1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "csi1_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_csi2_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 csi2_clk_src = {
> + .cmd_rcgr = 0x3c020,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_csi2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "csi2_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 camss_gp0_clk_src = {
> + .cmd_rcgr = 0x54000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_gp,
> + .freq_tbl = ftbl_camss_gp0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "camss_gp0_clk_src",
> + .parent_data = gcc_parent_data_8_gp,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8_gp),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_camss_gp1_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 camss_gp1_clk_src = {
> + .cmd_rcgr = 0x55000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_gp,
> + .freq_tbl = ftbl_camss_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "camss_gp1_clk_src",
> + .parent_data = gcc_parent_data_8_gp,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8_gp),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
> + F(133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 jpeg0_clk_src = {
> + .cmd_rcgr = 0x57000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_6,
> + .freq_tbl = ftbl_jpeg0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "jpeg0_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_mclk_clk_src[] = {
> + F(8000000, P_GPLL0_OUT_MAIN, 1, 1, 100),
> + F(24000000, P_GPLL6_OUT, 1, 1, 45),
> + F(66670000, P_GPLL0_OUT_MAIN, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 mclk0_clk_src = {
> + .cmd_rcgr = 0x52000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_7,
> + .freq_tbl = ftbl_mclk_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mclk0_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 mclk1_clk_src = {
> + .cmd_rcgr = 0x53000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_7,
> + .freq_tbl = ftbl_mclk_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mclk1_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 mclk2_clk_src = {
> + .cmd_rcgr = 0x5c000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_7,
> + .freq_tbl = ftbl_mclk_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mclk2_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 csi0phytimer_clk_src = {
> + .cmd_rcgr = 0x4e000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_csi0phytimer_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "csi0phytimer_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_csi1phytimer_clk_src[] = {
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 csi1phytimer_clk_src = {
> + .cmd_rcgr = 0x4f000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_csi1phytimer_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "csi1phytimer_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
> + F(40000000, P_GPLL0_OUT_MAIN, 10, 1, 2),
> + F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 camss_top_ahb_clk_src = {
> + .cmd_rcgr = 0x5a000,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_camss_top_ahb_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "camss_top_ahb_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_vfe0_clk_src[] = {
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
> + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + F(300000000, P_GPLL4_OUT, 4, 0, 0),
> + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + F(466000000, P_GPLL2_AUX, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 vfe0_clk_src = {
> + .cmd_rcgr = 0x58000,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_vfe0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "vfe0_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_vfe1_clk_src[] = {
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
> + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
> + F(300000000, P_GPLL4_OUT, 4, 0, 0),
> + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + F(466000000, P_GPLL2_AUX, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 vfe1_clk_src = {
> + .cmd_rcgr = 0x58054,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_vfe1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "vfe1_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_crypto_clk_src[] = {
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 crypto_clk_src = {
> + .cmd_rcgr = 0x16004,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_crypto_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "crypto_clk_src",
> + .parent_data = gcc_parent_data_4_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> + .cmd_rcgr = 0x8004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_gp,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp1_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_vote.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gp2_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> + .cmd_rcgr = 0x9004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_gp,
> + .freq_tbl = ftbl_gp2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp2_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_vote.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gp3_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> + .cmd_rcgr = 0xa004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8_gp,
> + .freq_tbl = ftbl_gp3_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp3_clk_src",
> + .parent_hws = (const struct clk_hw *[]) {
> + &gpll0_vote.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 byte0_clk_src = {
> + .cmd_rcgr = 0x4d044,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_mdss_byte0,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "byte0_clk_src",
> + .parent_data = gcc_parent_data_mdss_byte0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_mdss_byte0),
> + .ops = &clk_byte2_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
Can CLK_GET_RATE_NOCACHE be removed? If not, can you add a comment on
why it is needed that describes what it is fixing? Sometimes other qcom
clk drivers can get away without having this flag.
prev parent reply other threads:[~2021-04-01 2:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-25 20:18 [PATCH 1/2] dt-bindings: clock: qcom,gcc: Document MSM8976 compatibles Konrad Dybcio
2021-03-06 21:18 ` Rob Herring
[not found] ` <20210225201845.109670-2-konrad.dybcio@somainline.org>
2021-04-01 2:00 ` Stephen Boyd [this message]
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