From: Prasad Malisetty <pmaliset@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
bhelgaas@google.com, robh+dt@kernel.org, swboyd@chromium.org,
lorenzo.pieralisi@arm.com, svarbanov@mm-sol.com
Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org,
dianders@chromium.org, mka@chromium.org, vbadigan@codeaurora.org,
sallenki@codeaurora.org, manivannan.sadhasivam@linaro.org,
linux-pci@vger.kernel.org,
Prasad Malisetty <pmaliset@codeaurora.org>
Subject: [PATCH v10 5/5] PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280
Date: Tue, 5 Oct 2021 01:11:28 +0530 [thread overview]
Message-ID: <1633376488-545-6-git-send-email-pmaliset@codeaurora.org> (raw)
In-Reply-To: <1633376488-545-1-git-send-email-pmaliset@codeaurora.org>
On the SC7280, the clock source for gcc_pcie_1_pipe_clk_src
must be the TCXO while gdsc is enabled. After PHY init successful
clock source should switch to pipe clock for gcc_pcie_1_pipe_clk_src.
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 152451b..7896a86 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
struct clk *pipe_clk;
+ struct clk *pipe_clk_src;
+ struct clk *phy_pipe_clk;
+ struct clk *ref_clk_src;
};
union qcom_pcie_resources {
@@ -1173,6 +1176,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
+ if (pcie->pipe_clk_need_muxing) {
+ res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
+ if (IS_ERR(res->pipe_clk_src))
+ return PTR_ERR(res->pipe_clk_src);
+
+ res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
+ if (IS_ERR(res->phy_pipe_clk))
+ return PTR_ERR(res->phy_pipe_clk);
+
+ res->ref_clk_src = devm_clk_get(dev, "ref");
+ if (IS_ERR(res->ref_clk_src))
+ return PTR_ERR(res->ref_clk_src);
+ }
+
res->pipe_clk = devm_clk_get(dev, "pipe");
return PTR_ERR_OR_ZERO(res->pipe_clk);
}
@@ -1191,6 +1208,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
return ret;
}
+ /* Set TCXO as clock source for pcie_pipe_clk_src */
+ if (pcie->pipe_clk_need_muxing)
+ clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
+
ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
if (ret < 0)
goto err_disable_regulators;
@@ -1262,6 +1283,10 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+ /* Set pipe clock as clock source for pcie_pipe_clk_src */
+ if (pcie->pipe_clk_need_muxing)
+ clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
+
return clk_prepare_enable(res->pipe_clk);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2021-10-04 19:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 19:41 [PATCH v10 0/5] Add DT bindings and DT nodes for PCIe and PHY in SC7280 Prasad Malisetty
2021-10-04 19:41 ` [PATCH v10 1/5] dt-bindings: pci: qcom: Document PCIe bindings for SC7280 Prasad Malisetty
2021-10-04 19:41 ` [PATCH v10 2/5] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Prasad Malisetty
2021-10-05 1:11 ` Stephen Boyd
2021-10-04 19:41 ` [PATCH v10 3/5] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Prasad Malisetty
2021-10-05 1:10 ` Stephen Boyd
2021-10-04 19:41 ` [PATCH v10 4/5] PCI: qcom: Add a flag in match data along with ops Prasad Malisetty
2021-10-05 1:13 ` Stephen Boyd
2021-10-04 19:41 ` Prasad Malisetty [this message]
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