From: Prasad Malisetty <pmaliset@codeaurora.org>
To: svarbanov@mm-sol.com, agross@kernel.org,
bjorn.andersson@linaro.org, lorenzo.pieralisi@arm.com,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, vbadigan@codeaurora.org,
kw@linux.com, bhelgaas@google.com,
manivannan.sadhasivam@linaro.org
Cc: Prasad Malisetty <pmaliset@codeaurora.org>
Subject: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init
Date: Fri, 15 Oct 2021 00:28:49 +0530 [thread overview]
Message-ID: <1634237929-25459-1-git-send-email-pmaliset@codeaurora.org> (raw)
In pcie_init_2_7_0 one of the register writes using incorrect offset
as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT
offset value should be 0x1A8 instead 0x178).
Update the correct offset value for SDM845 platform.
fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller")
Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..5bce152 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+ val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
val |= BIT(31);
- writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
+ writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
}
return 0;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next reply other threads:[~2021-10-14 18:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 18:58 Prasad Malisetty [this message]
2021-10-15 13:57 ` [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init Bjorn Helgaas
2021-10-21 7:36 ` Manivannan Sadhasivam
2021-10-21 15:21 ` Prasad Malisetty
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