From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz,
tiwai@suse.com, srinivas.kandagatla@linaro.org,
rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org,
alsa-devel@alsa-project.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, swboyd@chromium.org,
judyhsiao@chromium.org
Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>,
Venkata Prasad Potturu <potturu@codeaurora.org>
Subject: [PATCH v4 1/3] ASoC: qcom: soundwire: Disable soundwire rxtx cgcr hardware control
Date: Tue, 26 Oct 2021 17:49:22 +0530 [thread overview]
Message-ID: <1635250764-13994-2-git-send-email-srivasam@codeaurora.org> (raw)
In-Reply-To: <1635250764-13994-1-git-send-email-srivasam@codeaurora.org>
Update soundwire master rxtx cgcr register field to make clock gating control as
software controllable.
It is required for soundwire v1.6.0 and above for RX and TX path to work.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/soundwire/qcom.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 0ef79d6..2492190 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -109,6 +109,7 @@
#define SWR_MAX_CMD_ID 14
#define MAX_FIFO_RD_RETRY 3
#define SWR_OVERFLOW_RETRY_COUNT 30
+#define SWR_RXTX_CGCR_HW_CTL_MASK ~BIT(1)
struct qcom_swrm_port_config {
u8 si;
@@ -127,6 +128,7 @@ struct qcom_swrm_ctrl {
struct device *dev;
struct regmap *regmap;
void __iomem *mmio;
+ char __iomem *audio_csr_mmio;
struct completion broadcast;
struct completion enumeration;
struct work_struct slave_work;
@@ -610,6 +612,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
+ if (ctrl->audio_csr_mmio) {
+ val = ioread32(ctrl->audio_csr_mmio);
+ val &= SWR_RXTX_CGCR_HW_CTL_MASK;
+ iowrite32(val, ctrl->audio_csr_mmio);
+ }
+
ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
/* Enable Auto enumeration */
@@ -1201,6 +1209,7 @@ static int qcom_swrm_probe(struct platform_device *pdev)
const struct qcom_swrm_data *data;
int ret;
u32 val;
+ int swrm_hctl_reg;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
@@ -1251,6 +1260,11 @@ static int qcom_swrm_probe(struct platform_device *pdev)
ctrl->bus.port_ops = &qcom_swrm_port_ops;
ctrl->bus.compute_params = &qcom_swrm_compute_params;
+ if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) {
+ ctrl->audio_csr_mmio = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4);
+ if (!ctrl->audio_csr_mmio)
+ return -ENODEV;
+ }
ret = qcom_swrm_get_port_config(ctrl);
if (ret)
goto err_clk;
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2021-10-26 12:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 12:19 [PATCH v4 0/3] Update SoundWire RX and TX cgcr register control Srinivasa Rao Mandadapu
2021-10-26 12:19 ` Srinivasa Rao Mandadapu [this message]
2021-10-27 21:03 ` [PATCH v4 1/3] ASoC: qcom: soundwire: Disable soundwire rxtx cgcr hardware control Stephen Boyd
2021-10-26 12:19 ` [PATCH v4 2/3] dt-bindings: soundwire: qcom: Add bindings for RX and TX cgcr register control Srinivasa Rao Mandadapu
2021-10-27 21:00 ` Rob Herring
2021-10-27 21:02 ` Stephen Boyd
2021-10-26 12:19 ` [PATCH v4 3/3] soundwire: qcom: Add compatible name for v1.6.0 Srinivasa Rao Mandadapu
2021-10-27 21:02 ` Stephen Boyd
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