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From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	bhelgaas@google.com
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	bjorn.andersson@linaro.org, robh@kernel.org,
	linux-pci@vger.kernel.org, svarbanov@mm-sol.com
Subject: Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints
Date: Fri,  8 Apr 2022 11:03:39 +0100	[thread overview]
Message-ID: <164941220567.21822.2763856506631523192.b4-ty@arm.com> (raw)
In-Reply-To: <20211214101319.25258-1-manivannan.sadhasivam@linaro.org>

On Tue, 14 Dec 2021 15:43:19 +0530, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> 
> [...]

Applied to pci/qcom, thanks!

[1/1] PCI: qcom: Add support for handling MSIs from 8 endpoints
      https://git.kernel.org/lpieralisi/pci/c/20f1bfb8dd

Thanks,
Lorenzo

      parent reply	other threads:[~2022-04-08 10:04 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-14 10:13 [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints Manivannan Sadhasivam
2022-02-23 10:01 ` Lorenzo Pieralisi
2022-03-14  5:22   ` Manivannan Sadhasivam
2022-03-28 14:20   ` Manivannan Sadhasivam
2022-03-28 14:39     ` Lorenzo Pieralisi
2022-04-08  9:52     ` Lorenzo Pieralisi
2022-02-23 10:03 ` Dmitry Baryshkov
2022-02-23 10:30 ` Stanimir Varbanov
2022-04-08 10:03 ` Lorenzo Pieralisi [this message]

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