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[71.163.245.5]) by smtp.gmail.com with ESMTPSA id o4sm7155973qkb.29.2021.05.18.08.38.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 May 2021 08:38:09 -0700 (PDT) Subject: Re: [PATCH v2 09/17] crypto: qce: core: Add support to initialize interconnect path To: Bjorn Andersson , Bhupesh Sharma Cc: linux-arm-msm@vger.kernel.org, Rob Herring , Andy Gross , Herbert Xu , "David S . Miller" , Stephen Boyd , Michael Turquette , Vinod Koul , dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com References: <20210505213731.538612-1-bhupesh.sharma@linaro.org> <20210505213731.538612-10-bhupesh.sharma@linaro.org> <20210518150702.GW2484@yoga> From: Thara Gopinath Message-ID: <180046b9-35fb-f7c1-fc92-a0fb5eecace5@linaro.org> Date: Tue, 18 May 2021 11:38:08 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210518150702.GW2484@yoga> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 5/18/21 11:07 AM, Bjorn Andersson wrote: > On Wed 05 May 16:37 CDT 2021, Bhupesh Sharma wrote: > >> From: Thara Gopinath >> >> Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350 >> etc. requires interconnect path between the engine and memory to be >> explicitly enabled and bandwidth set prior to any operations. Add support >> in the qce core to enable the interconnect path appropriately. >> >> Cc: Bjorn Andersson >> Cc: Rob Herring >> Cc: Andy Gross >> Cc: Herbert Xu >> Cc: David S. Miller >> Cc: Stephen Boyd >> Cc: Michael Turquette >> Cc: Vinod Koul >> Cc: dmaengine@vger.kernel.org >> Cc: linux-clk@vger.kernel.org >> Cc: linux-crypto@vger.kernel.org >> Cc: devicetree@vger.kernel.org >> Cc: linux-kernel@vger.kernel.org >> Cc: bhupesh.linux@gmail.com >> Signed-off-by: Bhupesh Sharma >> [Make header file inclusion alphabetical] >> Signed-off-by: Thara Gopinath > > This says that you prepared the patch, then Thara picked up the patch > and sorted the includes. But somehow you then sent the patch. > > I.e. you name should be the last - unless you jointly wrote the path, in > which case you should also add a "Co-developed-by: Thara". > >> --- >> drivers/crypto/qce/core.c | 35 ++++++++++++++++++++++++++++------- >> drivers/crypto/qce/core.h | 1 + >> 2 files changed, 29 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c >> index 80b75085c265..92a0ff1d357e 100644 >> --- a/drivers/crypto/qce/core.c >> +++ b/drivers/crypto/qce/core.c >> @@ -5,6 +5,7 @@ >> >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -21,6 +22,8 @@ >> #define QCE_MAJOR_VERSION5 0x05 >> #define QCE_QUEUE_LENGTH 1 >> >> +#define QCE_DEFAULT_MEM_BANDWIDTH 393600 > > Do we know what this rate is? > >> + >> static const struct qce_algo_ops *qce_ops[] = { >> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER >> &skcipher_ops, >> @@ -202,21 +205,35 @@ static int qce_crypto_probe(struct platform_device *pdev) >> if (ret < 0) >> return ret; >> >> + qce->mem_path = of_icc_get(qce->dev, "memory"); > > Using devm_of_icc_get() would save you some changes to the error path. Right. I keep forgetting to use the devm_ version! Bhupesh, will you do these changes or do you want me to ? -- Warm Regards Thara