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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id p17sm11684712qtq.87.2021.05.18.05.31.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 May 2021 05:31:17 -0700 (PDT) Subject: Re: [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC To: Robert Foss Cc: MSM , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , "open list:COMMON CLK FRAMEWORK" , open list References: <20210513195617.15068-1-jonathan@marek.ca> From: Jonathan Marek Message-ID: <1ab8d444-97b1-d14d-0088-80a027e1ec1a@marek.ca> Date: Tue, 18 May 2021 08:30:14 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 5/18/21 7:53 AM, Robert Foss wrote: > Hey Jonathan, > > Thanks for submitting this. > > On Thu, 13 May 2021 at 21:56, Jonathan Marek wrote: >> >> Add support to the SM8350 display clock controller by extending the SM8250 >> display clock controller, which is almost identical but has some minor >> differences. >> >> Signed-off-by: Jonathan Marek >> --- >> drivers/clk/qcom/Kconfig | 4 +- >> drivers/clk/qcom/dispcc-sm8250.c | 84 +++++++++++++++++++++++++++----- >> 2 files changed, 75 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 45646b867cdb..cc60e6ee1654 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -484,11 +484,11 @@ config SDX_GCC_55 >> SPI, I2C, USB, SD/UFS, PCIe etc. >> >> config SM_DISPCC_8250 >> - tristate "SM8150 and SM8250 Display Clock Controller" >> + tristate "SM8150/SM8250/SM8350 Display Clock Controller" >> depends on SM_GCC_8150 || SM_GCC_8250 >> help >> Support for the display clock controller on Qualcomm Technologies, Inc >> - SM8150 and SM8250 devices. >> + SM8150/SM8250/SM8350 devices. >> Say Y if you want to support display devices and functionality such as >> splash screen. >> >> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c >> index de09cd5c209f..1fcf8085a109 100644 >> --- a/drivers/clk/qcom/dispcc-sm8250.c >> +++ b/drivers/clk/qcom/dispcc-sm8250.c >> @@ -36,6 +36,10 @@ static struct pll_vco vco_table[] = { >> { 249600000, 2000000000, 0 }, >> }; >> >> +static struct pll_vco lucid_5lpe_vco[] = { >> + { 249600000, 1750000000, 0 }, >> +}; >> + >> static struct alpha_pll_config disp_cc_pll0_config = { >> .l = 0x47, >> .alpha = 0xE000, >> @@ -1039,6 +1043,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = { >> static const struct of_device_id disp_cc_sm8250_match_table[] = { >> { .compatible = "qcom,sm8150-dispcc" }, >> { .compatible = "qcom,sm8250-dispcc" }, >> + { .compatible = "qcom,sm8350-dispcc" }, >> { } >> }; >> MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); >> @@ -1051,19 +1056,76 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) >> if (IS_ERR(regmap)) >> return PTR_ERR(regmap); >> >> - /* note: trion == lucid, except for the prepare() op */ >> - BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); >> - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { > > I'm having a quick look at this patch, and of_device_is_compatible had > 2 cases previously, sm8150 & sm8250. Now three cases (sm8150, sm8250 & > sm8350) are possible, but sm8150 & sm8250 have been lumped together. > Is this correct? > This patch doesn't change the behavior for sm8150/sm8250, which are nearly identical. The check for qcom,sm8150-dispcc is just moved below. (looking over it, I should've left it first and kept the diff smaller. I had "lumped" sm8150/sm8250 because initially I had separate "pll_configure" calls for sm8350 vs sm8150/sm8250). >> - disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; >> - disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; >> - disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; >> - disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; >> - disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; >> - disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; >> - disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; >> - disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; >> + /* SM8350 has _SRC clocks offset by 4, and some other differences */ >> + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { >> + static struct clk_rcg2* const rcgs[] = { >> + &disp_cc_mdss_byte0_clk_src, >> + &disp_cc_mdss_byte1_clk_src, >> + &disp_cc_mdss_dp_aux1_clk_src, >> + &disp_cc_mdss_dp_aux_clk_src, >> + &disp_cc_mdss_dp_link1_clk_src, >> + &disp_cc_mdss_dp_link_clk_src, >> + &disp_cc_mdss_dp_pixel1_clk_src, >> + &disp_cc_mdss_dp_pixel2_clk_src, >> + &disp_cc_mdss_dp_pixel_clk_src, >> + &disp_cc_mdss_esc0_clk_src, >> + &disp_cc_mdss_mdp_clk_src, >> + &disp_cc_mdss_pclk0_clk_src, >> + &disp_cc_mdss_pclk1_clk_src, >> + &disp_cc_mdss_rot_clk_src, >> + &disp_cc_mdss_vsync_clk_src, >> + }; >> + static struct clk_regmap_div* const divs[] = { >> + &disp_cc_mdss_byte0_div_clk_src, >> + &disp_cc_mdss_byte1_div_clk_src, >> + &disp_cc_mdss_dp_link1_div_clk_src, >> + &disp_cc_mdss_dp_link_div_clk_src, >> + }; >> + unsigned i; >> + static bool offset_applied = false; >> + >> + /* only apply the offsets once (in case of deferred probe) */ >> + if (!offset_applied) { >> + for (i = 0; i < ARRAY_SIZE(rcgs); i++) >> + rcgs[i]->cmd_rcgr -= 4; >> + >> + for (i = 0; i < ARRAY_SIZE(divs); i++) { >> + divs[i]->reg -= 4; >> + divs[i]->width = 4; >> + } >> + >> + disp_cc_mdss_ahb_clk.halt_reg -= 4; >> + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; >> + >> + offset_applied = true; >> + } >> + >> + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; >> + >> + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C; >> + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; >> + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; >> + disp_cc_pll0.vco_table = lucid_5lpe_vco; >> + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C; >> + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; >> + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; >> + disp_cc_pll1.vco_table = lucid_5lpe_vco; >> + } else { >> + /* note: trion == lucid, except for the prepare() op */ >> + BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); >> + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { >> + disp_cc_pll0_config.config_ctl_hi_val = 0x00002267; >> + disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024; >> + disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0; >> + disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops; >> + disp_cc_pll1_config.config_ctl_hi_val = 0x00002267; >> + disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; >> + disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; >> + disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; >> + } >> } >> >> + /* note for SM8350: downstream lucid_5lpe configure differs slightly */ >> clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); >> clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); >> >> -- >> 2.26.1 >>