From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Mark Rutland <Mark.Rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC
Date: Tue, 7 Jan 2014 10:54:39 +0000 [thread overview]
Message-ID: <20140107105439.GC5906@e102568-lin.cambridge.arm.com> (raw)
In-Reply-To: <1388434457-4194-5-git-send-email-sboyd@codeaurora.org>
On Mon, Dec 30, 2013 at 08:14:15PM +0000, Stephen Boyd wrote:
> The Krait L1/L2 error reporting device is made up of two
> interrupts, one per-CPU interrupt for the L1 caches and one
> interrupt for the L2 cache.
>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 72 ++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 9130435..54de94b 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -191,6 +191,35 @@ nodes to be present and contain the properties described below.
> property identifying a 64-bit zero-initialised
> memory location.
>
> + - interrupts
> + Usage: required for cpus with compatible string "qcom,krait".
> + Value type: <prop-encoded-array>
> + Definition: L1/CPU error interrupt
> +
> + - next-level-cache
> + Usage: optional
> + Value type: <phandle>
> + Definition: phandle pointing to the next level cache
> +
> +- cache node
Not sure this binding (cache node) belongs in cpus.txt
I am working on defining cache bindings for ARM within the C-state
standardization effort:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/215543.html
> +
> + Description: Describes a cache in an ARM based system
> +
> + - compatible
> + Usage: required
> + Value type: <string>
> + Definition: shall contain at least "cache"
It is a bit vague, can't we just follow the ePAPR compatible definition ?
See posting above.
> +
> + - cache-level
> + Usage: required
> + Value type: <u32>
> + Definition: level in the cache heirachy
"hierarchy". I have a problem with the cache level definition, and in
particular the numbering, ie what the level number represents. If we
mean the cache level seen through the CLIDR and co., it is hard to use
it for shared caches since the level seen by different CPUs can actually
be different, or put it differently the level number might not be unique for
a shared cache. I need to think about a proper way to sort this out.
Lorenzo
next prev parent reply other threads:[~2014-01-07 10:54 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-30 20:14 [PATCH v4 0/6] Krait L1/L2 EDAC driver Stephen Boyd
2013-12-30 20:14 ` [PATCH v4 1/6] edac: Don't try to cancel workqueue when it's never setup Stephen Boyd
2014-01-07 17:19 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 2/6] genirq: export percpu irq functions for module usage Stephen Boyd
2014-01-07 23:02 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 3/6] ARM: Add Krait L2 accessor functions Stephen Boyd
2014-01-07 23:07 ` Borislav Petkov
2014-01-07 23:09 ` Stephen Boyd
2014-01-09 0:53 ` Courtney Cavin
2014-01-09 1:54 ` Stephen Boyd
2014-01-09 11:03 ` Borislav Petkov
[not found] ` <1388434457-4194-1-git-send-email-sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2013-12-30 20:14 ` [PATCH v4 4/6] devicetree: bindings: Document Krait L1/L2 EDAC Stephen Boyd
2014-01-07 10:54 ` Lorenzo Pieralisi [this message]
2014-01-07 20:12 ` Stephen Boyd
2014-01-08 10:05 ` Lorenzo Pieralisi
2014-01-09 20:52 ` Stephen Boyd
2014-01-10 10:54 ` Lorenzo Pieralisi
2013-12-30 20:14 ` [PATCH v4 5/6] edac: Add support for Krait CPU cache error detection Stephen Boyd
2014-01-07 23:43 ` Borislav Petkov
2013-12-30 20:14 ` [PATCH v4 6/6] ARM: dts: msm: Add Krait CPU/L2 nodes Stephen Boyd
2014-01-04 10:19 ` [PATCH v4 0/6] Krait L1/L2 EDAC driver Borislav Petkov
[not found] ` <20140104101901.GA4439-K5JNixvcfoxupOikMc4+xw@public.gmane.org>
2014-01-06 22:09 ` Stephen Boyd
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