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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id g8sm282837pgq.33.2019.05.21.20.50.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 May 2019 20:50:30 -0700 (PDT) Date: Tue, 21 May 2019 20:50:28 -0700 From: Bjorn Andersson To: Amit Kucheria Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, agross@kernel.org, niklas.cassel@linaro.org, marc.w.gonzalez@free.fr, sibis@codeaurora.org, daniel.lezcano@linaro.org, Andy Gross , David Brown , Li Yang , Shawn Guo , devicetree@vger.kernel.org Subject: Re: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Message-ID: <20190522035028.GN3137@builder> References: <5224535a7ef5b257e3baa698991bf6deeefccc36.1558430617.git.amit.kucheria@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5224535a7ef5b257e3baa698991bf6deeefccc36.1558430617.git.amit.kucheria@linaro.org> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote: > msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement > the same microarchitecture and the two clusters only differ in the > maximum frequency attainable by the CPUs. > > Add capacity-dmips-mhz property to allow the topology code to determine > the actual capacity by taking into account the highest frequency for > each CPU. > > Signed-off-by: Amit Kucheria > Suggested-by: Daniel Lezcano Applied Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 4f2fb7885f39..e0e8f30ce11a 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -96,6 +96,7 @@ > reg = <0x0 0x0>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_0>; > L2_0: l2-cache { > compatible = "cache"; > @@ -109,6 +110,7 @@ > reg = <0x0 0x1>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_0>; > }; > > @@ -118,6 +120,7 @@ > reg = <0x0 0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_1>; > L2_1: l2-cache { > compatible = "cache"; > @@ -131,6 +134,7 @@ > reg = <0x0 0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > + capacity-dmips-mhz = <1024>; > next-level-cache = <&L2_1>; > }; > > -- > 2.17.1 >