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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id a9sm17192793pgw.72.2019.06.04.16.41.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jun 2019 16:41:05 -0700 (PDT) Date: Tue, 4 Jun 2019 16:41:03 -0700 From: Bjorn Andersson To: Will Deacon , Robin Murphy Cc: Vivek Gautam , Joerg Roedel , linux-arm-msm , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," , Vivek Gautam , open list , Linux ARM Subject: Re: [PATCH] iommu: io-pgtable: Support non-coherent page tables Message-ID: <20190604234103.GH4814@minitux> References: <20190515233234.22990-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.12.0 (2019-05-25) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 15 May 23:47 PDT 2019, Vivek Gautam wrote: > On Thu, May 16, 2019 at 5:03 AM Bjorn Andersson > wrote: > > > > Describe the memory related to page table walks as non-cachable for iommu > > instances that are not DMA coherent. > > > > Signed-off-by: Bjorn Andersson > > --- > > drivers/iommu/io-pgtable-arm.c | 12 +++++++++--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c > > index 4e21efbc4459..68ff22ffd2cb 100644 > > --- a/drivers/iommu/io-pgtable-arm.c > > +++ b/drivers/iommu/io-pgtable-arm.c > > @@ -803,9 +803,15 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) > > return NULL; > > > > /* TCR */ > > - reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > > - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | > > - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); > > + if (cfg->quirks & IO_PGTABLE_QUIRK_NO_DMA) { > > + reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > > + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | > > + (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); > > + } else { > > + reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | > > + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_IRGN0_SHIFT) | > > + (ARM_LPAE_TCR_RGN_NC << ARM_LPAE_TCR_ORGN0_SHIFT); > > + } > > This looks okay to me based on the discussion that we had on a similar > patch that I > posted. So, > Reviewed-by: Vivek Gautam > > [1] https://lore.kernel.org/patchwork/patch/1032939/ > Will, Robin, any input on this patch? Regards, Bjorn