From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_NEOMUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B2C2C04AB5 for ; Thu, 6 Jun 2019 07:49:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DED1220874 for ; Thu, 6 Jun 2019 07:49:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726713AbfFFHtm (ORCPT ); Thu, 6 Jun 2019 03:49:42 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42050 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725769AbfFFHtm (ORCPT ); Thu, 6 Jun 2019 03:49:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E39E341; Thu, 6 Jun 2019 00:49:41 -0700 (PDT) Received: from queper01-ThinkPad-T460s (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3E4DC3F246; Thu, 6 Jun 2019 00:49:38 -0700 (PDT) Date: Thu, 6 Jun 2019 08:49:24 +0100 From: Quentin Perret To: Vincent Guittot Cc: Stephen Boyd , Amit Kucheria , Andy Gross , Matthias Kaehlcke , David Brown , Rob Herring , Mark Rutland , linux-arm-msm , "open list:ARM/QUALCOMM SUPPORT" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Douglas Anderson , Rajendra Nayak Subject: Re: [PATCH] arm64: dts: sdm845: Add CPU topology Message-ID: <20190606074921.43mbinemk3j565yu@queper01-ThinkPad-T460s> References: <20190114184255.258318-1-mka@chromium.org> <155786856719.14659.2902538189660269078@swboyd.mtv.corp.google.com> <5cdf2dc8.1c69fb81.521c8.9339@mx.google.com> <20190605172048.ahzusevvdxrpnebk@queper01-ThinkPad-T460s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Vincent, On Thursday 06 Jun 2019 at 09:05:16 (+0200), Vincent Guittot wrote: > Hi Quentin, > > On Wed, 5 Jun 2019 at 19:21, Quentin Perret wrote: > > > > On Friday 17 May 2019 at 14:55:19 (-0700), Stephen Boyd wrote: > > > Quoting Amit Kucheria (2019-05-16 04:54:45) > > > > (cc'ing Andy's correct email address) > > > > > > > > On Wed, May 15, 2019 at 2:46 AM Stephen Boyd wrote: > > > > > > > > > > Quoting Amit Kucheria (2019-05-13 04:54:12) > > > > > > On Mon, May 13, 2019 at 4:31 PM Amit Kucheria wrote: > > > > > > > > > > > > > > On Tue, Jan 15, 2019 at 12:13 AM Matthias Kaehlcke wrote: > > > > > > > > > > > > > > > > The 8 CPU cores of the SDM845 are organized in two clusters of 4 big > > > > > > > > ("gold") and 4 little ("silver") cores. Add a cpu-map node to the DT > > > > > > > > that describes this topology. > > > > > > > > > > > > > > This is partly true. There are two groups of gold and silver cores, > > > > > > > but AFAICT they are in a single cluster, not two separate ones. SDM845 > > > > > > > is one of the early examples of ARM's Dynamiq architecture. > > > > > > > > > > > > > > > Signed-off-by: Matthias Kaehlcke > > > > > > > > > > > > > > I noticed that this patch sneaked through for this merge window but > > > > > > > perhaps we can whip up a quick fix for -rc2? > > > > > > > > > > > > > > > > > > > And please find attached a patch to fix this up. Andy, since this > > > > > > hasn't landed yet (can we still squash this into the original patch?), > > > > > > I couldn't add a Fixes tag. > > > > > > > > > > > > > > > > I had the same concern. Thanks for catching this. I suspect this must > > > > > cause some problem for IPA given that it can't discern between the big > > > > > and little "power clusters"? > > > > > > > > Both EAS and IPA, I believe. It influences the scheduler's view of the > > > > the topology. > > > > > > And EAS and IPA are OK with the real topology? I'm just curious if > > > changing the topology to reflect reality will be a problem for those > > > two. > > > > FWIW, neither EAS nor IPA depends on this. Not the upstream version of > > EAS at least (which is used in recent Android kernels -- 4.19+). > > > > But doing this is still required for other things in the scheduler (the > > so-called 'capacity-awareness' code). So until we have a better > > solution, this patch is doing the right thing. > > I'm not sure to catch what you mean ? > Which so-called 'capacity-awareness' code are you speaking about ? and > what is the problem ? I'm talking about the wake-up path. ATM select_idle_sibling() is totally unaware of capacity differences. In its current form, this function basically assumes that all CPUs in a given sd_llc have the same capacity, which would be wrong if we had a single MC level for SDM845. So, until select_idle_sibling() is 'fixed' to be capacity-aware, we need two levels of sd for asymetric systems (including DynamIQ) so the wake_cap() story actually works. I hope that clarifies it :) Thanks, Quentin