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* [PATCH v2 0/9] qcom: Add cpuidle to some platforms
@ 2019-05-21  9:35 Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation Amit Kucheria
                   ` (8 more replies)
  0 siblings, 9 replies; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree, linux-arm-kernel

Changes since v1:
 - Reworded changes to the idle-state documentation on Sudeep's feedback.
 - Renamed several idle-state node names to be homogeneous across qcom
   platforms. We now use cpu_sleep_0_0 format for the node name while using
   LITTLE_CPU_SLEEP_0 format for labels to help differentiate the different
   states for different CPU types.
 - Add a new patch to add capacity-dmips-mhz property for msm8996 to allow
   topology code to find its true capacity.
 - Add power-collapse state to msm8998 in additon to the retention state.
 - Added acks

MSM8998 changes are untested for v2 because I couldn't access the mtp I
usually have access to. Hopefully Marc and Sibi can help with testing.

Description
-----------
Fix up a few entry-method="psci" issues and then add cpuidle low power
states for msm8996, msm8998, qcs404, sdm845. All these have been tested
to only make sure that the C-states are entered from Linux point-of-view.

We will continue to add more states and make power measurements to tweak
some of these numbers, but getting these merged will allow other people to
use these platforms to work on cpuidle, eas and related topics.


Amit Kucheria (7):
  arm64: dts: fsl: ls1028a: Fix entry-method property to reflect
    documentation
  Documentation: arm: Link idle-states binding to "enable-method"
    property
  arm64: dts: qcom: msm8916: Add entry-method property for the
    idle-states node
  arm64: dts: qcom: msm8916: Use more generic idle state names
  arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states
  arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  arm64: dts: msm8996: Add proper capacity scaling for the cpus

Niklas Cassel (1):
  arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states

Raju P.L.S.S.S.N (1):
  arm64: dts: qcom: sdm845: Add PSCI cpuidle low power states

 .../devicetree/bindings/arm/idle-states.txt   | 13 +++-
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  2 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi         | 13 ++--
 arch/arm64/boot/dts/qcom/msm8996.dtsi         | 21 ++++++
 arch/arm64/boot/dts/qcom/msm8998.dtsi         | 50 ++++++++++++++
 arch/arm64/boot/dts/qcom/qcs404.dtsi          | 18 +++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi          | 69 +++++++++++++++++++
 7 files changed, 177 insertions(+), 9 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Amit Kucheria
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: linux-arm-kernel, devicetree

The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be set
to "psci".

We fixed up all uses of the entry-method property in
commit e9880240e4f4 ("arm64: dts: Fix various entry-method properties to
reflect documentation"). But a new one has appeared. Fix it up.

[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbcfa3bb..42e7822a0227 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -51,7 +51,7 @@
 		 * PSCI node is not added default, U-boot will add missing
 		 * parts if it determines to use PSCI.
 		 */
-		entry-method = "arm,psci";
+		entry-method = "psci";
 
 		CPU_PH20: cpu-ph20 {
 			compatible = "arm,idle-state";
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-21 10:34   ` Marc Gonzalez
  2019-06-13 23:13   ` Rob Herring
  2019-05-21  9:35 ` [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node Amit Kucheria
                   ` (6 subsequent siblings)
  8 siblings, 2 replies; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

The "enable-method" property for cpu nodes needs to be "psci" for CPU
idle management to be setup correctly.

Add a note to the binding documentation to this effect to make it
obvious.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
---
 .../devicetree/bindings/arm/idle-states.txt         | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
index 45730ba60af5..3bdbe675b9e6 100644
--- a/Documentation/devicetree/bindings/arm/idle-states.txt
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -241,9 +241,13 @@ processor idle states, defined as device tree nodes, are listed.
 			   - "psci"
 			# On ARM 32-bit systems this property is optional
 
-The nodes describing the idle states (state) can only be defined within the
-idle-states node, any other configuration is considered invalid and therefore
-must be ignored.
+This assumes that the "enable-method" property is set to "psci" in the cpu
+node[6] that is responsible for setting up CPU idle management in the OS
+implementation.
+
+The nodes describing the idle states (state) can only be defined
+within the idle-states node, any other configuration is considered invalid
+and therefore must be ignored.
 
 ===========================================
 4 - state node
@@ -697,3 +701,6 @@ cpus {
 
 [5] Devicetree Specification
     https://www.devicetree.org/specifications/
+
+[6] ARM Linux Kernel documentation - Booting AArch64 Linux
+    Documentation/arm64/booting.txt
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-22  3:30   ` Bjorn Andersson
  2019-05-21  9:35 ` [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names Amit Kucheria
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be set
to "psci".

[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0803ca8c02da..82ea5b8b37a2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -158,6 +158,8 @@
 		};
 
 		idle-states {
+			entry-method = "psci";
+
 			CPU_SPC: spc {
 				compatible = "arm,idle-state";
 				arm,psci-suspend-param = <0x40000002>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (2 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-22  3:30   ` Bjorn Andersson
  2019-05-21  9:35 ` [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states Amit Kucheria
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

Instead of using Qualcomm-specific terminology, use generic node names
for the idle states that are easier to understand. Move the description
into the "idle-state-name" property.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 82ea5b8b37a2..3a8c6c4fcf15 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -110,7 +110,7 @@
 			reg = <0x0>;
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
-			cpu-idle-states = <&CPU_SPC>;
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&apcs>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -122,7 +122,7 @@
 			reg = <0x1>;
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
-			cpu-idle-states = <&CPU_SPC>;
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&apcs>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -134,7 +134,7 @@
 			reg = <0x2>;
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
-			cpu-idle-states = <&CPU_SPC>;
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&apcs>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -146,7 +146,7 @@
 			reg = <0x3>;
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
-			cpu-idle-states = <&CPU_SPC>;
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&apcs>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>;
@@ -160,8 +160,9 @@
 		idle-states {
 			entry-method = "psci";
 
-			CPU_SPC: spc {
+			CPU_SLEEP_0: cpu-sleep-0 {
 				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
 				arm,psci-suspend-param = <0x40000002>;
 				entry-latency-us = <130>;
 				exit-latency-us = <150>;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (3 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-22  3:31   ` Bjorn Andersson
  2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

From: Niklas Cassel <niklas.cassel@linaro.org>

Add device bindings for cpuidle states for cpu devices.

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
[rename the idle-states to more generic names and fixups]
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index e8fd26633d57..0a9b29af64c2 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -30,6 +30,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -38,6 +39,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x101>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -46,6 +48,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x102>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -54,6 +57,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x103>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -61,6 +65,20 @@
 			compatible = "cache";
 			cache-level = <2>;
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <125>;
+				exit-latency-us = <180>;
+				min-residency-us = <595>;
+				local-timer-stop;
+			};
+		};
 	};
 
 	firmware {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 6/9] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (4 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states Amit Kucheria
@ 2019-05-21  9:35 ` " Amit Kucheria
  2019-05-21 10:13   ` Daniel Lezcano
                     ` (2 more replies)
  2019-05-21  9:35 ` [PATCH v2 7/9] arm64: dts: qcom: msm8998: " Amit Kucheria
                   ` (2 subsequent siblings)
  8 siblings, 3 replies; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

Add device bindings for cpuidle states for cpu devices.

msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
the same microarchitecture and the two clusters only differ in the
maximum frequency attainable by the CPUs.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c761269caf80..4f2fb7885f39 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -95,6 +95,7 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 			      compatible = "cache";
@@ -107,6 +108,7 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -115,6 +117,7 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 			      compatible = "cache";
@@ -127,6 +130,7 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x101>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_1>;
 		};
 
@@ -151,6 +155,19 @@
 				};
 			};
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <40>;
+				exit-latency-us = <80>;
+				min-residency-us = <300>;
+			};
+		};
 	};
 
 	thermal-zones {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (5 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
@ 2019-05-21  9:35 ` " Amit Kucheria
  2019-05-21 12:03   ` Marc Gonzalez
  2019-05-21  9:35 ` [PATCH v2 8/9] arm64: dts: qcom: sdm845: " Amit Kucheria
  2019-05-21  9:35 ` [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Amit Kucheria
  8 siblings, 1 reply; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

Add device bindings for cpuidle states for cpu devices.

Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 50 +++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 3fd0769fe648..54810980fcf9 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -78,6 +78,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			efficiency = <1024>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
@@ -97,6 +98,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			efficiency = <1024>;
 			next-level-cache = <&L2_0>;
 			L1_I_1: l1-icache {
@@ -112,6 +114,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			efficiency = <1024>;
 			next-level-cache = <&L2_0>;
 			L1_I_2: l1-icache {
@@ -127,6 +130,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			efficiency = <1024>;
 			next-level-cache = <&L2_0>;
 			L1_I_3: l1-icache {
@@ -142,6 +146,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			efficiency = <1536>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
@@ -161,6 +166,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x101>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			efficiency = <1536>;
 			next-level-cache = <&L2_1>;
 			L1_I_101: l1-icache {
@@ -176,6 +182,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x102>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			efficiency = <1536>;
 			next-level-cache = <&L2_1>;
 			L1_I_102: l1-icache {
@@ -191,6 +198,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x103>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			efficiency = <1536>;
 			next-level-cache = <&L2_1>;
 			L1_I_103: l1-icache {
@@ -238,6 +246,48 @@
 				};
 			};
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-retention";
+				arm,psci-suspend-param = <0x00000002>;
+				entry-latency-us = <43>;
+				exit-latency-us = <86>;
+				min-residency-us = <200>;
+			};
+
+			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-power-collapse";
+				arm,psci-suspend-param = <0x00000003>;
+				entry-latency-us = <100>;
+				exit-latency-us = <612>;
+				min-residency-us = <1000>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-retention";
+				arm,psci-suspend-param = <0x00000002>;
+				entry-latency-us = <41>;
+				exit-latency-us = <82>;
+				min-residency-us = <200>;
+			};
+
+			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-power-collapse";
+				arm,psci-suspend-param = <0x00000003>;
+				entry-latency-us = <100>;
+				exit-latency-us = <525>;
+				min-residency-us = <1000>;
+				local-timer-stop;
+			};
+		};
 	};
 
 	firmware {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 8/9] arm64: dts: qcom: sdm845: Add PSCI cpuidle low power states
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (6 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 7/9] arm64: dts: qcom: msm8998: " Amit Kucheria
@ 2019-05-21  9:35 ` " Amit Kucheria
  2019-05-22  3:59   ` Bjorn Andersson
  2019-05-21  9:35 ` [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Amit Kucheria
  8 siblings, 1 reply; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: Raju P.L.S.S.S.N, mkshah, devicetree

From: "Raju P.L.S.S.S.N" <rplsssn@codeaurora.org>

Add device bindings for cpuidle states for cpu devices.

Cc: <mkshah@codeaurora.org>
Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
[amit: rename the idle-states to more generic names and fixups]
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 69 ++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5308f1671824..a0ae6bf033ee 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -119,6 +119,7 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_0>;
@@ -136,6 +137,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_100>;
@@ -150,6 +153,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x200>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_200>;
@@ -164,6 +169,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x300>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_300>;
@@ -178,6 +185,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x400>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_400>;
@@ -192,6 +201,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x500>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_500>;
@@ -206,6 +217,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x600>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_600>;
@@ -220,6 +233,8 @@
 			compatible = "qcom,kryo385";
 			reg = <0x0 0x700>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
+					   &CLUSTER_SLEEP_0>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			#cooling-cells = <2>;
 			next-level-cache = <&L2_700>;
@@ -228,6 +243,60 @@
 				next-level-cache = <&L3_0>;
 			};
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-power-down";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <350>;
+				exit-latency-us = <461>;
+				min-residency-us = <1890>;
+				local-timer-stop;
+			};
+
+			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-rail-power-down";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <360>;
+				exit-latency-us = <531>;
+				min-residency-us = <3934>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-power-down";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <264>;
+				exit-latency-us = <621>;
+				min-residency-us = <952>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-rail-power-down";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <702>;
+				exit-latency-us = <1061>;
+				min-residency-us = <4488>;
+				local-timer-stop;
+			};
+
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "cluster-power-down";
+				arm,psci-suspend-param = <0x400000F4>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9987>;
+				local-timer-stop;
+			};
+		};
 	};
 
 	pmu {
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus
  2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
                   ` (7 preceding siblings ...)
  2019-05-21  9:35 ` [PATCH v2 8/9] arm64: dts: qcom: sdm845: " Amit Kucheria
@ 2019-05-21  9:35 ` Amit Kucheria
  2019-05-21 10:14   ` Daniel Lezcano
  2019-05-22  3:50   ` Bjorn Andersson
  8 siblings, 2 replies; 27+ messages in thread
From: Amit Kucheria @ 2019-05-21  9:35 UTC (permalink / raw)
  To: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo
  Cc: devicetree

msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
the same microarchitecture and the two clusters only differ in the
maximum frequency attainable by the CPUs.

Add capacity-dmips-mhz property to allow the topology code to determine
the actual capacity by taking into account the highest frequency for
each CPU.

Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4f2fb7885f39..e0e8f30ce11a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -96,6 +96,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 			      compatible = "cache";
@@ -109,6 +110,7 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
 			next-level-cache = <&L2_0>;
 		};
 
@@ -118,6 +120,7 @@
 			reg = <0x0 0x100>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 			      compatible = "cache";
@@ -131,6 +134,7 @@
 			reg = <0x0 0x101>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			capacity-dmips-mhz = <1024>;
 			next-level-cache = <&L2_1>;
 		};
 
-- 
2.17.1


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 6/9] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
@ 2019-05-21 10:13   ` Daniel Lezcano
  2019-05-22  3:49   ` Bjorn Andersson
  2019-05-23 21:24   ` Niklas Cassel
  2 siblings, 0 replies; 27+ messages in thread
From: Daniel Lezcano @ 2019-05-21 10:13 UTC (permalink / raw)
  To: Amit Kucheria, linux-kernel, linux-arm-msm, bjorn.andersson,
	agross, niklas.cassel, marc.w.gonzalez, sibis, Andy Gross,
	David Brown, Li Yang, Shawn Guo
  Cc: devicetree

On 21/05/2019 11:35, Amit Kucheria wrote:
> Add device bindings for cpuidle states for cpu devices.
> 
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>



> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c761269caf80..4f2fb7885f39 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -95,6 +95,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
> @@ -107,6 +108,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -115,6 +117,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  			      compatible = "cache";
> @@ -127,6 +130,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x101>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  		};
>  
> @@ -151,6 +155,19 @@
>  				};
>  			};
>  		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP_0: cpu-sleep-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "standalone-power-collapse";
> +				arm,psci-suspend-param = <0x00000004>;
> +				entry-latency-us = <40>;
> +				exit-latency-us = <80>;
> +				min-residency-us = <300>;
> +			};
> +		};
>  	};
>  
>  	thermal-zones {
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus
  2019-05-21  9:35 ` [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Amit Kucheria
@ 2019-05-21 10:14   ` Daniel Lezcano
  2019-05-22  3:50   ` Bjorn Andersson
  1 sibling, 0 replies; 27+ messages in thread
From: Daniel Lezcano @ 2019-05-21 10:14 UTC (permalink / raw)
  To: Amit Kucheria, linux-kernel, linux-arm-msm, bjorn.andersson,
	agross, niklas.cassel, marc.w.gonzalez, sibis, Andy Gross,
	David Brown, Li Yang, Shawn Guo
  Cc: devicetree

On 21/05/2019 11:35, Amit Kucheria wrote:
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
> 
> Add capacity-dmips-mhz property to allow the topology code to determine
> the actual capacity by taking into account the highest frequency for
> each CPU.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 4f2fb7885f39..e0e8f30ce11a 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -96,6 +96,7 @@
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
> @@ -109,6 +110,7 @@
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -118,6 +120,7 @@
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  			      compatible = "cache";
> @@ -131,6 +134,7 @@
>  			reg = <0x0 0x101>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_1>;
>  		};
>  
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property
  2019-05-21  9:35 ` [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Amit Kucheria
@ 2019-05-21 10:34   ` Marc Gonzalez
  2019-06-13 23:13   ` Rob Herring
  1 sibling, 0 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-21 10:34 UTC (permalink / raw)
  To: Amit Kucheria; +Cc: MSM, Bjorn Andersson, Andy Gross

On 21/05/2019 11:35, Amit Kucheria wrote:

> The "enable-method" property for cpu nodes needs to be "psci" for CPU
> idle management to be setup correctly.
> 
> Add a note to the binding documentation to this effect to make it
> obvious.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
>  .../devicetree/bindings/arm/idle-states.txt         | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> index 45730ba60af5..3bdbe675b9e6 100644
> --- a/Documentation/devicetree/bindings/arm/idle-states.txt
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -241,9 +241,13 @@ processor idle states, defined as device tree nodes, are listed.
>  			   - "psci"
>  			# On ARM 32-bit systems this property is optional
>  
> -The nodes describing the idle states (state) can only be defined within the
> -idle-states node, any other configuration is considered invalid and therefore
> -must be ignored.
> +This assumes that the "enable-method" property is set to "psci" in the cpu
> +node[6] that is responsible for setting up CPU idle management in the OS
> +implementation.
> +
> +The nodes describing the idle states (state) can only be defined
> +within the idle-states node, any other configuration is considered invalid
> +and therefore must be ignored.

Nit: I suppose your text editor automatically "reflowed" this last paragraph?
I would leave it as-is, to minimize the diff, and avoid cosmetic changes.

Regards.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 7/9] arm64: dts: qcom: msm8998: " Amit Kucheria
@ 2019-05-21 12:03   ` Marc Gonzalez
  2019-05-21 16:10     ` Marc Gonzalez
  2019-05-22  9:17     ` Marc Gonzalez
  0 siblings, 2 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-21 12:03 UTC (permalink / raw)
  To: Amit Kucheria; +Cc: MSM, LKML, Bjorn Andersson, Daniel Lezcano, Andy Gross

On 21/05/2019 11:35, Amit Kucheria wrote:

> Add device bindings for cpuidle states for cpu devices.
> 
> Cc: Marc Gonzalez <marc.w.gonzalez@free.fr>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8998.dtsi | 50 +++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 3fd0769fe648..54810980fcf9 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -78,6 +78,7 @@
>  			compatible = "arm,armv8";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
>  			efficiency = <1024>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {


NB: this patch does not apply cleanly to v5.2-rc1  ;-)

86f93c93dd50 arm64: dts: msm8998: efficiency is not valid property

commit 86f93c93dd5005f0aeb8ce84c2113e21a6006c7d
Author:     Amit Kucheria <amit.kucheria@linaro.org>
AuthorDate: Fri Mar 29 15:42:08 2019 +0530
Commit:     Andy Gross <agross@kernel.org>
CommitDate: Tue Apr 9 23:08:17 2019 -0500

After manually fixing up the trivial conflict, the DTB builds without errors.

I then enable
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y

(because I'm using a board-specific tiny defconfig)

And... the system starts to boot, hangs a few seconds, then silently reboots:

scsi 0:0:0:3: Direct-Access     SAMSUNG  KLUBG4G1CE-B0B1  0800 PQ: 0 ANSI: 6
sd 0:0:0:1: [sdb] 16384-byte physical blocks
sd 0:0:0:2: [sdc] 2048 4096-byte logical blocks: (8.39 MB/8.00 MiB)
sd 0:0:0:2: [sdc] 16384-byte physical blocks

Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.2.2-00157-M8998LZB-1
S - IMAGE_VARIANT_STRING=Msm8998LA


Looks like the "helpful" behavior of the secure OS...

Regards.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-21 12:03   ` Marc Gonzalez
@ 2019-05-21 16:10     ` Marc Gonzalez
  2019-05-22  9:17     ` Marc Gonzalez
  1 sibling, 0 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-21 16:10 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: MSM, LKML, Bjorn Andersson, Daniel Lezcano, Andy Gross, Jeffrey Hugo

On 21/05/2019 14:03, Marc Gonzalez wrote:

> the system starts to boot, hangs a few seconds, then silently reboots

Using extremely high-tech debugging tools (i.e. spraying printk left and right)
I traced this one down to:

psci_cpu_suspend_enter: 435
psci_cpu_suspend: 171
psci_cpu_suspend: __invoke_psci_fn_smc c4000001
__invoke_psci_fn_smc: id=c4000001 3 0 0
/*** we never return from arm_smccc_smc() ***/


The following dmesg log caught my eye, and might be relevant:

ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware


If I revert your patch, psci_cpu_suspend_enter() is never called,
so we don't tickle the arm_smccc_smc() monster.

Could it be that my FW doesn't support PSCI?

Regards.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node
  2019-05-21  9:35 ` [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node Amit Kucheria
@ 2019-05-22  3:30   ` Bjorn Andersson
  0 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:30 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> The idle-states binding documentation[1] mentions that the
> 'entry-method' property is required on 64-bit platforms and must be set
> to "psci".
> 
> [1] Documentation/devicetree/bindings/arm/idle-states.txt (see
> idle-states node)
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Picked up

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 0803ca8c02da..82ea5b8b37a2 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -158,6 +158,8 @@
>  		};
>  
>  		idle-states {
> +			entry-method = "psci";
> +
>  			CPU_SPC: spc {
>  				compatible = "arm,idle-state";
>  				arm,psci-suspend-param = <0x40000002>;
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names
  2019-05-21  9:35 ` [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names Amit Kucheria
@ 2019-05-22  3:30   ` Bjorn Andersson
  0 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:30 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> Instead of using Qualcomm-specific terminology, use generic node names
> for the idle states that are easier to understand. Move the description
> into the "idle-state-name" property.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---

Picked up

Regards,
Bjorn

>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 82ea5b8b37a2..3a8c6c4fcf15 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -110,7 +110,7 @@
>  			reg = <0x0>;
>  			next-level-cache = <&L2_0>;
>  			enable-method = "psci";
> -			cpu-idle-states = <&CPU_SPC>;
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			clocks = <&apcs>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -122,7 +122,7 @@
>  			reg = <0x1>;
>  			next-level-cache = <&L2_0>;
>  			enable-method = "psci";
> -			cpu-idle-states = <&CPU_SPC>;
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			clocks = <&apcs>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -134,7 +134,7 @@
>  			reg = <0x2>;
>  			next-level-cache = <&L2_0>;
>  			enable-method = "psci";
> -			cpu-idle-states = <&CPU_SPC>;
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			clocks = <&apcs>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -146,7 +146,7 @@
>  			reg = <0x3>;
>  			next-level-cache = <&L2_0>;
>  			enable-method = "psci";
> -			cpu-idle-states = <&CPU_SPC>;
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			clocks = <&apcs>;
>  			operating-points-v2 = <&cpu_opp_table>;
>  			#cooling-cells = <2>;
> @@ -160,8 +160,9 @@
>  		idle-states {
>  			entry-method = "psci";
>  
> -			CPU_SPC: spc {
> +			CPU_SLEEP_0: cpu-sleep-0 {
>  				compatible = "arm,idle-state";
> +				idle-state-name = "standalone-power-collapse";
>  				arm,psci-suspend-param = <0x40000002>;
>  				entry-latency-us = <130>;
>  				exit-latency-us = <150>;
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states Amit Kucheria
@ 2019-05-22  3:31   ` Bjorn Andersson
  0 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:31 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> From: Niklas Cassel <niklas.cassel@linaro.org>
> 
> Add device bindings for cpuidle states for cpu devices.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> [rename the idle-states to more generic names and fixups]
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---

Applied

Regards,
Bjorn

>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index e8fd26633d57..0a9b29af64c2 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -30,6 +30,7 @@
>  			compatible = "arm,cortex-a53";
>  			reg = <0x100>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -38,6 +39,7 @@
>  			compatible = "arm,cortex-a53";
>  			reg = <0x101>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -46,6 +48,7 @@
>  			compatible = "arm,cortex-a53";
>  			reg = <0x102>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -54,6 +57,7 @@
>  			compatible = "arm,cortex-a53";
>  			reg = <0x103>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -61,6 +65,20 @@
>  			compatible = "cache";
>  			cache-level = <2>;
>  		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP_0: cpu-sleep-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "standalone-power-collapse";
> +				arm,psci-suspend-param = <0x40000003>;
> +				entry-latency-us = <125>;
> +				exit-latency-us = <180>;
> +				min-residency-us = <595>;
> +				local-timer-stop;
> +			};
> +		};
>  	};
>  
>  	firmware {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 6/9] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
  2019-05-21 10:13   ` Daniel Lezcano
@ 2019-05-22  3:49   ` Bjorn Andersson
  2019-05-23 21:24   ` Niklas Cassel
  2 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:49 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> Add device bindings for cpuidle states for cpu devices.
> 
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>

Applied

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c761269caf80..4f2fb7885f39 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -95,6 +95,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
> @@ -107,6 +108,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -115,6 +117,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  			      compatible = "cache";
> @@ -127,6 +130,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x101>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  		};
>  
> @@ -151,6 +155,19 @@
>  				};
>  			};
>  		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP_0: cpu-sleep-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "standalone-power-collapse";
> +				arm,psci-suspend-param = <0x00000004>;
> +				entry-latency-us = <40>;
> +				exit-latency-us = <80>;
> +				min-residency-us = <300>;
> +			};
> +		};
>  	};
>  
>  	thermal-zones {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus
  2019-05-21  9:35 ` [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Amit Kucheria
  2019-05-21 10:14   ` Daniel Lezcano
@ 2019-05-22  3:50   ` Bjorn Andersson
  1 sibling, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:50 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
> 
> Add capacity-dmips-mhz property to allow the topology code to determine
> the actual capacity by taking into account the highest frequency for
> each CPU.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>

Applied

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 4f2fb7885f39..e0e8f30ce11a 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -96,6 +96,7 @@
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
> @@ -109,6 +110,7 @@
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -118,6 +120,7 @@
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  			      compatible = "cache";
> @@ -131,6 +134,7 @@
>  			reg = <0x0 0x101>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
> +			capacity-dmips-mhz = <1024>;
>  			next-level-cache = <&L2_1>;
>  		};
>  
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 8/9] arm64: dts: qcom: sdm845: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 8/9] arm64: dts: qcom: sdm845: " Amit Kucheria
@ 2019-05-22  3:59   ` Bjorn Andersson
  0 siblings, 0 replies; 27+ messages in thread
From: Bjorn Andersson @ 2019-05-22  3:59 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, agross, niklas.cassel,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, Raju P.L.S.S.S.N, mkshah, devicetree

On Tue 21 May 02:35 PDT 2019, Amit Kucheria wrote:

> From: "Raju P.L.S.S.S.N" <rplsssn@codeaurora.org>
> 
> Add device bindings for cpuidle states for cpu devices.
> 
> Cc: <mkshah@codeaurora.org>
> Signed-off-by: Raju P.L.S.S.S.N <rplsssn@codeaurora.org>
> Reviewed-by: Evan Green <evgreen@chromium.org>
> [amit: rename the idle-states to more generic names and fixups]
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---

Applied

Thanks,
Bjorn

>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 69 ++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 5308f1671824..a0ae6bf033ee 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -119,6 +119,7 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_0>;
> @@ -136,6 +137,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_100>;
> @@ -150,6 +153,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x200>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_200>;
> @@ -164,6 +169,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x300>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_300>;
> @@ -178,6 +185,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x400>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_400>;
> @@ -192,6 +201,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x500>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_500>;
> @@ -206,6 +217,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x600>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_600>;
> @@ -220,6 +233,8 @@
>  			compatible = "qcom,kryo385";
>  			reg = <0x0 0x700>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1
> +					   &CLUSTER_SLEEP_0>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			#cooling-cells = <2>;
>  			next-level-cache = <&L2_700>;
> @@ -228,6 +243,60 @@
>  				next-level-cache = <&L3_0>;
>  			};
>  		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "little-power-down";
> +				arm,psci-suspend-param = <0x40000003>;
> +				entry-latency-us = <350>;
> +				exit-latency-us = <461>;
> +				min-residency-us = <1890>;
> +				local-timer-stop;
> +			};
> +
> +			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "little-rail-power-down";
> +				arm,psci-suspend-param = <0x40000004>;
> +				entry-latency-us = <360>;
> +				exit-latency-us = <531>;
> +				min-residency-us = <3934>;
> +				local-timer-stop;
> +			};
> +
> +			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "big-power-down";
> +				arm,psci-suspend-param = <0x40000003>;
> +				entry-latency-us = <264>;
> +				exit-latency-us = <621>;
> +				min-residency-us = <952>;
> +				local-timer-stop;
> +			};
> +
> +			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "big-rail-power-down";
> +				arm,psci-suspend-param = <0x40000004>;
> +				entry-latency-us = <702>;
> +				exit-latency-us = <1061>;
> +				min-residency-us = <4488>;
> +				local-timer-stop;
> +			};
> +
> +			CLUSTER_SLEEP_0: cluster-sleep-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "cluster-power-down";
> +				arm,psci-suspend-param = <0x400000F4>;
> +				entry-latency-us = <3263>;
> +				exit-latency-us = <6562>;
> +				min-residency-us = <9987>;
> +				local-timer-stop;
> +			};
> +		};
>  	};
>  
>  	pmu {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-21 12:03   ` Marc Gonzalez
  2019-05-21 16:10     ` Marc Gonzalez
@ 2019-05-22  9:17     ` Marc Gonzalez
  2019-05-22  9:35       ` Marc Zyngier
  2019-05-22 14:48       ` Marc Gonzalez
  1 sibling, 2 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-22  9:17 UTC (permalink / raw)
  To: Amit Kucheria, MSM, Linux ARM
  Cc: Bjorn Andersson, Daniel Lezcano, Niklas Cassel, Jeffrey Hugo,
	Sibi Sankar, Mark Rutland, Lorenzo Pieralisi, Robin Murphy,
	Sudeep Holla, Marc Zyngier

[ Re-sending to a wider audience, hoping to catch someone's eye ]

https://patchwork.kernel.org/patch/10953257/

On 21/05/2019 14:03, Marc Gonzalez wrote:

> With CPUIDLE enabled, my system starts to boot, hangs a few seconds,
> then silently reboots (killed by FW)

Using extremely high-tech debugging tools (i.e. spraying printk left and right)
I traced this crash down to:

psci_cpu_suspend_enter: 435
psci_cpu_suspend: 171
psci_cpu_suspend: __invoke_psci_fn_smc c4000001
__invoke_psci_fn_smc: id=c4000001 3 0 0
/*** execution never returns from arm_smccc_smc() ***/


The following dmesg log caught my eye, and might be relevant:

	ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware

Is that bad, doctor? I don't think it would explain the crash though...


If I revert the patch, psci_cpu_suspend_enter() is never called,
so we don't tickle the arm_smccc_smc() monster.

Could it be that this FW doesn't support PSCI?

Regards.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-22  9:17     ` Marc Gonzalez
@ 2019-05-22  9:35       ` Marc Zyngier
  2019-05-22 15:39         ` Marc Gonzalez
  2019-05-22 14:48       ` Marc Gonzalez
  1 sibling, 1 reply; 27+ messages in thread
From: Marc Zyngier @ 2019-05-22  9:35 UTC (permalink / raw)
  To: Marc Gonzalez, Amit Kucheria, MSM, Linux ARM
  Cc: Bjorn Andersson, Daniel Lezcano, Niklas Cassel, Jeffrey Hugo,
	Sibi Sankar, Mark Rutland, Lorenzo Pieralisi, Robin Murphy,
	Sudeep Holla

On 22/05/2019 10:17, Marc Gonzalez wrote:
> [ Re-sending to a wider audience, hoping to catch someone's eye ]
> 
> https://patchwork.kernel.org/patch/10953257/
> 
> On 21/05/2019 14:03, Marc Gonzalez wrote:
> 
>> With CPUIDLE enabled, my system starts to boot, hangs a few seconds,
>> then silently reboots (killed by FW)
> 
> Using extremely high-tech debugging tools (i.e. spraying printk left and right)
> I traced this crash down to:
> 
> psci_cpu_suspend_enter: 435
> psci_cpu_suspend: 171
> psci_cpu_suspend: __invoke_psci_fn_smc c4000001
> __invoke_psci_fn_smc: id=c4000001 3 0 0
> /*** execution never returns from arm_smccc_smc() ***/
> 
> 
> The following dmesg log caught my eye, and might be relevant:
> 
> 	ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware
> 
> Is that bad, doctor? I don't think it would explain the crash though...

It doesn't explain it.

It is bad though: your vendor doesn't tell the kernel about the HW being
free of Spectre-v2, and doesn't provide a mitigation either. Hopefully,
this is a responsible vendor that will provide you with a firmware
update that fixes it.

> 
> 
> If I revert the patch, psci_cpu_suspend_enter() is never called,
> so we don't tickle the arm_smccc_smc() monster.
> 
> Could it be that this FW doesn't support PSCI?

Probably not in as well as it could, at least for CPU suspend.

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-22  9:17     ` Marc Gonzalez
  2019-05-22  9:35       ` Marc Zyngier
@ 2019-05-22 14:48       ` Marc Gonzalez
  1 sibling, 0 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-22 14:48 UTC (permalink / raw)
  To: Amit Kucheria, MSM, Linux ARM
  Cc: Bjorn Andersson, Daniel Lezcano, Niklas Cassel, Jeffrey Hugo,
	Sibi Sankar, Mark Rutland, Lorenzo Pieralisi, Robin Murphy,
	Sudeep Holla, Marc Zyngier, Andy Gross

On 22/05/2019 11:17, Marc Gonzalez wrote:

> Could it be that this FW doesn't support PSCI?

I believe it works now.

Tested-by: Marc Gonzalez <marc.w.gonzalez@free.fr>

As pointed out by Niklas in v1:
	arm,psci-suspend-param needs to be 0x40000003 not 0x3

(If either local-timer-stop is removed, bad things happen.)

Below is the diff with next-20190521.

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 412195b9794c..224f84e39204 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -78,6 +78,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 				compatible = "arm,arch-cache";
@@ -96,6 +97,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			next-level-cache = <&L2_0>;
 			L1_I_1: l1-icache {
 				compatible = "arm,arch-cache";
@@ -110,6 +112,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			next-level-cache = <&L2_0>;
 			L1_I_2: l1-icache {
 				compatible = "arm,arch-cache";
@@ -124,6 +127,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 			next-level-cache = <&L2_0>;
 			L1_I_3: l1-icache {
 				compatible = "arm,arch-cache";
@@ -138,6 +142,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 				compatible = "arm,arch-cache";
@@ -156,6 +161,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x101>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			next-level-cache = <&L2_1>;
 			L1_I_101: l1-icache {
 				compatible = "arm,arch-cache";
@@ -170,6 +176,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x102>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			next-level-cache = <&L2_1>;
 			L1_I_102: l1-icache {
 				compatible = "arm,arch-cache";
@@ -184,6 +191,7 @@
 			compatible = "arm,armv8";
 			reg = <0x0 0x103>;
 			enable-method = "psci";
+			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 			next-level-cache = <&L2_1>;
 			L1_I_103: l1-icache {
 				compatible = "arm,arch-cache";
@@ -230,6 +238,48 @@
 				};
 			};
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-retention";
+				arm,psci-suspend-param = <0x00000002>;
+				entry-latency-us = <43>;
+				exit-latency-us = <86>;
+				min-residency-us = <200>;
+			};
+
+			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "little-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <100>;
+				exit-latency-us = <612>;
+				min-residency-us = <1000>;
+				local-timer-stop;
+			};
+
+			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-retention";
+				arm,psci-suspend-param = <0x00000002>;
+				entry-latency-us = <41>;
+				exit-latency-us = <82>;
+				min-residency-us = <200>;
+			};
+
+			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "big-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <100>;
+				exit-latency-us = <525>;
+				min-residency-us = <1000>;
+				local-timer-stop;
+			};
+		};
 	};
 
 	firmware {






# for F in $(find /sys/devices/system/cpu -type f); do echo $F; cat $F; done
/sys/devices/system/cpu/cpuidle/current_governor_ro
menu
/sys/devices/system/cpu/cpuidle/current_driver
arm_idle
/sys/devices/system/cpu/uevent
/sys/devices/system/cpu/cpu7/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu7/cpuidle/state1/above
1
/sys/devices/system/cpu/cpu7/cpuidle/state1/time
15749
/sys/devices/system/cpu/cpu7/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu7/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu7/cpuidle/state1/latency
123
/sys/devices/system/cpu/cpu7/cpuidle/state1/usage
19
/sys/devices/system/cpu/cpu7/cpuidle/state1/desc
big-retention
/sys/devices/system/cpu/cpu7/cpuidle/state1/below
6
/sys/devices/system/cpu/cpu7/cpuidle/state1/name
cpu-sleep-1-0
/sys/devices/system/cpu/cpu7/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu7/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu7/cpuidle/state2/above
8
/sys/devices/system/cpu/cpu7/cpuidle/state2/time
616012492
/sys/devices/system/cpu/cpu7/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu7/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu7/cpuidle/state2/latency
625
/sys/devices/system/cpu/cpu7/cpuidle/state2/usage
120
/sys/devices/system/cpu/cpu7/cpuidle/state2/desc
big-power-collapse
/sys/devices/system/cpu/cpu7/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu7/cpuidle/state2/name
cpu-sleep-1-1
/sys/devices/system/cpu/cpu7/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu7/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu7/cpuidle/state0/time
29077
/sys/devices/system/cpu/cpu7/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu7/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu7/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu7/cpuidle/state0/usage
11
/sys/devices/system/cpu/cpu7/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu7/cpuidle/state0/below
8
/sys/devices/system/cpu/cpu7/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu7/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@103
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu7/power/runtime_active_time
0
/sys/devices/system/cpu/cpu7/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu7/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu7/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu7/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu7/power/control
auto
/sys/devices/system/cpu/cpu7/topology/physical_package_id
1
/sys/devices/system/cpu/cpu7/topology/core_siblings
f0
/sys/devices/system/cpu/cpu7/topology/core_siblings_list
4-7
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list
7
/sys/devices/system/cpu/cpu7/topology/core_id
3
/sys/devices/system/cpu/cpu7/topology/thread_siblings
80
/sys/devices/system/cpu/cpu7/cpu_capacity
1024
/sys/devices/system/cpu/cpu7/cache/uevent
/sys/devices/system/cpu/cpu7/cache/index2/uevent
/sys/devices/system/cpu/cpu7/cache/index2/shared_cpu_list
4-7
/sys/devices/system/cpu/cpu7/cache/index2/type
Unified
/sys/devices/system/cpu/cpu7/cache/index2/level
2
/sys/devices/system/cpu/cpu7/cache/index2/shared_cpu_map
f0
/sys/devices/system/cpu/cpu7/cache/index0/uevent
/sys/devices/system/cpu/cpu7/cache/index0/shared_cpu_list
7
/sys/devices/system/cpu/cpu7/cache/index0/type
Data
/sys/devices/system/cpu/cpu7/cache/index0/level
1
/sys/devices/system/cpu/cpu7/cache/index0/shared_cpu_map
80
/sys/devices/system/cpu/cpu7/cache/index1/uevent
/sys/devices/system/cpu/cpu7/cache/index1/shared_cpu_list
7
/sys/devices/system/cpu/cpu7/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu7/cache/index1/level
1
/sys/devices/system/cpu/cpu7/cache/index1/shared_cpu_map
80
/sys/devices/system/cpu/cpu7/regs/identification/revidr_el1
0x0000000000000001
/sys/devices/system/cpu/cpu7/regs/identification/midr_el1
0x0000000051af8001
/sys/devices/system/cpu/cpu5/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu5/cpuidle/state1/above
0
/sys/devices/system/cpu/cpu5/cpuidle/state1/time
19922
/sys/devices/system/cpu/cpu5/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu5/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu5/cpuidle/state1/latency
123
/sys/devices/system/cpu/cpu5/cpuidle/state1/usage
28
/sys/devices/system/cpu/cpu5/cpuidle/state1/desc
big-retention
/sys/devices/system/cpu/cpu5/cpuidle/state1/below
5
/sys/devices/system/cpu/cpu5/cpuidle/state1/name
cpu-sleep-1-0
/sys/devices/system/cpu/cpu5/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu5/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu5/cpuidle/state2/above
12
/sys/devices/system/cpu/cpu5/cpuidle/state2/time
616088023
/sys/devices/system/cpu/cpu5/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu5/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu5/cpuidle/state2/latency
625
/sys/devices/system/cpu/cpu5/cpuidle/state2/usage
248
/sys/devices/system/cpu/cpu5/cpuidle/state2/desc
big-power-collapse
/sys/devices/system/cpu/cpu5/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu5/cpuidle/state2/name
cpu-sleep-1-1
/sys/devices/system/cpu/cpu5/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu5/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu5/cpuidle/state0/time
30023
/sys/devices/system/cpu/cpu5/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu5/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu5/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu5/cpuidle/state0/usage
16
/sys/devices/system/cpu/cpu5/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu5/cpuidle/state0/below
10
/sys/devices/system/cpu/cpu5/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu5/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@101
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu5/power/runtime_active_time
0
/sys/devices/system/cpu/cpu5/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu5/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu5/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu5/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu5/power/control
auto
/sys/devices/system/cpu/cpu5/topology/physical_package_id
1
/sys/devices/system/cpu/cpu5/topology/core_siblings
f0
/sys/devices/system/cpu/cpu5/topology/core_siblings_list
4-7
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list
5
/sys/devices/system/cpu/cpu5/topology/core_id
1
/sys/devices/system/cpu/cpu5/topology/thread_siblings
20
/sys/devices/system/cpu/cpu5/cpu_capacity
1024
/sys/devices/system/cpu/cpu5/cache/uevent
/sys/devices/system/cpu/cpu5/cache/index2/uevent
/sys/devices/system/cpu/cpu5/cache/index2/shared_cpu_list
4-7
/sys/devices/system/cpu/cpu5/cache/index2/type
Unified
/sys/devices/system/cpu/cpu5/cache/index2/level
2
/sys/devices/system/cpu/cpu5/cache/index2/shared_cpu_map
f0
/sys/devices/system/cpu/cpu5/cache/index0/uevent
/sys/devices/system/cpu/cpu5/cache/index0/shared_cpu_list
5
/sys/devices/system/cpu/cpu5/cache/index0/type
Data
/sys/devices/system/cpu/cpu5/cache/index0/level
1
/sys/devices/system/cpu/cpu5/cache/index0/shared_cpu_map
20
/sys/devices/system/cpu/cpu5/cache/index1/uevent
/sys/devices/system/cpu/cpu5/cache/index1/shared_cpu_list
5
/sys/devices/system/cpu/cpu5/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu5/cache/index1/level
1
/sys/devices/system/cpu/cpu5/cache/index1/shared_cpu_map
20
/sys/devices/system/cpu/cpu5/regs/identification/revidr_el1
0x0000000000000001
/sys/devices/system/cpu/cpu5/regs/identification/midr_el1
0x0000000051af8001
/sys/devices/system/cpu/possible
0-7
/sys/devices/system/cpu/offline

/sys/devices/system/cpu/present
0-7
/sys/devices/system/cpu/power/runtime_active_time
0
/sys/devices/system/cpu/power/runtime_status
unsupported
/sys/devices/system/cpu/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/power/runtime_suspended_time
0
/sys/devices/system/cpu/power/control
auto
/sys/devices/system/cpu/cpu3/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu3/cpuidle/state1/above
0
/sys/devices/system/cpu/cpu3/cpuidle/state1/time
7453
/sys/devices/system/cpu/cpu3/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu3/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu3/cpuidle/state1/latency
129
/sys/devices/system/cpu/cpu3/cpuidle/state1/usage
10
/sys/devices/system/cpu/cpu3/cpuidle/state1/desc
little-retention
/sys/devices/system/cpu/cpu3/cpuidle/state1/below
2
/sys/devices/system/cpu/cpu3/cpuidle/state1/name
cpu-sleep-0-0
/sys/devices/system/cpu/cpu3/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu3/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu3/cpuidle/state2/above
8
/sys/devices/system/cpu/cpu3/cpuidle/state2/time
616684999
/sys/devices/system/cpu/cpu3/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu3/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu3/cpuidle/state2/latency
712
/sys/devices/system/cpu/cpu3/cpuidle/state2/usage
298
/sys/devices/system/cpu/cpu3/cpuidle/state2/desc
little-power-collapse
/sys/devices/system/cpu/cpu3/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu3/cpuidle/state2/name
cpu-sleep-0-1
/sys/devices/system/cpu/cpu3/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu3/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu3/cpuidle/state0/time
29256
/sys/devices/system/cpu/cpu3/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu3/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu3/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu3/cpuidle/state0/usage
11
/sys/devices/system/cpu/cpu3/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu3/cpuidle/state0/below
8
/sys/devices/system/cpu/cpu3/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu3/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@3
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu3/power/runtime_active_time
0
/sys/devices/system/cpu/cpu3/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu3/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu3/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu3/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu3/power/control
auto
/sys/devices/system/cpu/cpu3/topology/physical_package_id
0
/sys/devices/system/cpu/cpu3/topology/core_siblings
0f
/sys/devices/system/cpu/cpu3/topology/core_siblings_list
0-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list
3
/sys/devices/system/cpu/cpu3/topology/core_id
3
/sys/devices/system/cpu/cpu3/topology/thread_siblings
08
/sys/devices/system/cpu/cpu3/cpu_capacity
1024
/sys/devices/system/cpu/cpu3/cache/uevent
/sys/devices/system/cpu/cpu3/cache/index2/uevent
/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_list
0-3
/sys/devices/system/cpu/cpu3/cache/index2/type
Unified
/sys/devices/system/cpu/cpu3/cache/index2/level
2
/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_map
0f
/sys/devices/system/cpu/cpu3/cache/index0/uevent
/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_list
3
/sys/devices/system/cpu/cpu3/cache/index0/type
Data
/sys/devices/system/cpu/cpu3/cache/index0/level
1
/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_map
08
/sys/devices/system/cpu/cpu3/cache/index1/uevent
/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_list
3
/sys/devices/system/cpu/cpu3/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu3/cache/index1/level
1
/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_map
08
/sys/devices/system/cpu/cpu3/regs/identification/revidr_el1
0x0000000000000180
/sys/devices/system/cpu/cpu3/regs/identification/midr_el1
0x0000000051af8014
/sys/devices/system/cpu/online
0-7
/sys/devices/system/cpu/cpu1/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu1/cpuidle/state1/above
3
/sys/devices/system/cpu/cpu1/cpuidle/state1/time
8494
/sys/devices/system/cpu/cpu1/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu1/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu1/cpuidle/state1/latency
129
/sys/devices/system/cpu/cpu1/cpuidle/state1/usage
15
/sys/devices/system/cpu/cpu1/cpuidle/state1/desc
little-retention
/sys/devices/system/cpu/cpu1/cpuidle/state1/below
0
/sys/devices/system/cpu/cpu1/cpuidle/state1/name
cpu-sleep-0-0
/sys/devices/system/cpu/cpu1/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu1/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu1/cpuidle/state2/above
6
/sys/devices/system/cpu/cpu1/cpuidle/state2/time
617122679
/sys/devices/system/cpu/cpu1/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu1/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu1/cpuidle/state2/latency
712
/sys/devices/system/cpu/cpu1/cpuidle/state2/usage
394
/sys/devices/system/cpu/cpu1/cpuidle/state2/desc
little-power-collapse
/sys/devices/system/cpu/cpu1/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu1/cpuidle/state2/name
cpu-sleep-0-1
/sys/devices/system/cpu/cpu1/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu1/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu1/cpuidle/state0/time
4704
/sys/devices/system/cpu/cpu1/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu1/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu1/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu1/cpuidle/state0/usage
8
/sys/devices/system/cpu/cpu1/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu1/cpuidle/state0/below
4
/sys/devices/system/cpu/cpu1/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu1/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@1
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu1/power/runtime_active_time
0
/sys/devices/system/cpu/cpu1/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu1/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu1/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu1/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu1/power/control
auto
/sys/devices/system/cpu/cpu1/topology/physical_package_id
0
/sys/devices/system/cpu/cpu1/topology/core_siblings
0f
/sys/devices/system/cpu/cpu1/topology/core_siblings_list
0-3
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list
1
/sys/devices/system/cpu/cpu1/topology/core_id
1
/sys/devices/system/cpu/cpu1/topology/thread_siblings
02
/sys/devices/system/cpu/cpu1/cpu_capacity
1024
/sys/devices/system/cpu/cpu1/cache/uevent
/sys/devices/system/cpu/cpu1/cache/index2/uevent
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list
0-3
/sys/devices/system/cpu/cpu1/cache/index2/type
Unified
/sys/devices/system/cpu/cpu1/cache/index2/level
2
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map
0f
/sys/devices/system/cpu/cpu1/cache/index0/uevent
/sys/devices/system/cpu/cpu1/cache/index0/shared_cpu_list
1
/sys/devices/system/cpu/cpu1/cache/index0/type
Data
/sys/devices/system/cpu/cpu1/cache/index0/level
1
/sys/devices/system/cpu/cpu1/cache/index0/shared_cpu_map
02
/sys/devices/system/cpu/cpu1/cache/index1/uevent
/sys/devices/system/cpu/cpu1/cache/index1/shared_cpu_list
1
/sys/devices/system/cpu/cpu1/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu1/cache/index1/level
1
/sys/devices/system/cpu/cpu1/cache/index1/shared_cpu_map
02
/sys/devices/system/cpu/cpu1/regs/identification/revidr_el1
0x0000000000000180
/sys/devices/system/cpu/cpu1/regs/identification/midr_el1
0x0000000051af8014
/sys/devices/system/cpu/vulnerabilities/spectre_v2
Vulnerable
/sys/devices/system/cpu/vulnerabilities/mds
Not affected
/sys/devices/system/cpu/vulnerabilities/l1tf
Not affected
/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
Vulnerable
/sys/devices/system/cpu/vulnerabilities/spectre_v1
Mitigation: __user pointer sanitization
/sys/devices/system/cpu/vulnerabilities/meltdown
Mitigation: PTI
/sys/devices/system/cpu/cpu6/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu6/cpuidle/state1/above
0
/sys/devices/system/cpu/cpu6/cpuidle/state1/time
7186
/sys/devices/system/cpu/cpu6/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu6/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu6/cpuidle/state1/latency
123
/sys/devices/system/cpu/cpu6/cpuidle/state1/usage
9
/sys/devices/system/cpu/cpu6/cpuidle/state1/desc
big-retention
/sys/devices/system/cpu/cpu6/cpuidle/state1/below
2
/sys/devices/system/cpu/cpu6/cpuidle/state1/name
cpu-sleep-1-0
/sys/devices/system/cpu/cpu6/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu6/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu6/cpuidle/state2/above
4
/sys/devices/system/cpu/cpu6/cpuidle/state2/time
617440536
/sys/devices/system/cpu/cpu6/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu6/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu6/cpuidle/state2/latency
625
/sys/devices/system/cpu/cpu6/cpuidle/state2/usage
385
/sys/devices/system/cpu/cpu6/cpuidle/state2/desc
big-power-collapse
/sys/devices/system/cpu/cpu6/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu6/cpuidle/state2/name
cpu-sleep-1-1
/sys/devices/system/cpu/cpu6/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu6/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu6/cpuidle/state0/time
28990
/sys/devices/system/cpu/cpu6/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu6/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu6/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu6/cpuidle/state0/usage
10
/sys/devices/system/cpu/cpu6/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu6/cpuidle/state0/below
8
/sys/devices/system/cpu/cpu6/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu6/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@102
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu6/power/runtime_active_time
0
/sys/devices/system/cpu/cpu6/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu6/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu6/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu6/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu6/power/control
auto
/sys/devices/system/cpu/cpu6/topology/physical_package_id
1
/sys/devices/system/cpu/cpu6/topology/core_siblings
f0
/sys/devices/system/cpu/cpu6/topology/core_siblings_list
4-7
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list
6
/sys/devices/system/cpu/cpu6/topology/core_id
2
/sys/devices/system/cpu/cpu6/topology/thread_siblings
40
/sys/devices/system/cpu/cpu6/cpu_capacity
1024
/sys/devices/system/cpu/cpu6/cache/uevent
/sys/devices/system/cpu/cpu6/cache/index2/uevent
/sys/devices/system/cpu/cpu6/cache/index2/shared_cpu_list
4-7
/sys/devices/system/cpu/cpu6/cache/index2/type
Unified
/sys/devices/system/cpu/cpu6/cache/index2/level
2
/sys/devices/system/cpu/cpu6/cache/index2/shared_cpu_map
f0
/sys/devices/system/cpu/cpu6/cache/index0/uevent
/sys/devices/system/cpu/cpu6/cache/index0/shared_cpu_list
6
/sys/devices/system/cpu/cpu6/cache/index0/type
Data
/sys/devices/system/cpu/cpu6/cache/index0/level
1
/sys/devices/system/cpu/cpu6/cache/index0/shared_cpu_map
40
/sys/devices/system/cpu/cpu6/cache/index1/uevent
/sys/devices/system/cpu/cpu6/cache/index1/shared_cpu_list
6
/sys/devices/system/cpu/cpu6/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu6/cache/index1/level
1
/sys/devices/system/cpu/cpu6/cache/index1/shared_cpu_map
40
/sys/devices/system/cpu/cpu6/regs/identification/revidr_el1
0x0000000000000001
/sys/devices/system/cpu/cpu6/regs/identification/midr_el1
0x0000000051af8001
/sys/devices/system/cpu/cpu4/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu4/cpuidle/state1/above
4
/sys/devices/system/cpu/cpu4/cpuidle/state1/time
48576
/sys/devices/system/cpu/cpu4/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu4/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu4/cpuidle/state1/latency
123
/sys/devices/system/cpu/cpu4/cpuidle/state1/usage
58
/sys/devices/system/cpu/cpu4/cpuidle/state1/desc
big-retention
/sys/devices/system/cpu/cpu4/cpuidle/state1/below
15
/sys/devices/system/cpu/cpu4/cpuidle/state1/name
cpu-sleep-1-0
/sys/devices/system/cpu/cpu4/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu4/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu4/cpuidle/state2/above
19
/sys/devices/system/cpu/cpu4/cpuidle/state2/time
617566283
/sys/devices/system/cpu/cpu4/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu4/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu4/cpuidle/state2/latency
625
/sys/devices/system/cpu/cpu4/cpuidle/state2/usage
515
/sys/devices/system/cpu/cpu4/cpuidle/state2/desc
big-power-collapse
/sys/devices/system/cpu/cpu4/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu4/cpuidle/state2/name
cpu-sleep-1-1
/sys/devices/system/cpu/cpu4/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu4/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu4/cpuidle/state0/time
33524
/sys/devices/system/cpu/cpu4/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu4/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu4/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu4/cpuidle/state0/usage
19
/sys/devices/system/cpu/cpu4/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu4/cpuidle/state0/below
9
/sys/devices/system/cpu/cpu4/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu4/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@100
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu4/power/runtime_active_time
0
/sys/devices/system/cpu/cpu4/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu4/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu4/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu4/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu4/power/control
auto
/sys/devices/system/cpu/cpu4/topology/physical_package_id
1
/sys/devices/system/cpu/cpu4/topology/core_siblings
f0
/sys/devices/system/cpu/cpu4/topology/core_siblings_list
4-7
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list
4
/sys/devices/system/cpu/cpu4/topology/core_id
0
/sys/devices/system/cpu/cpu4/topology/thread_siblings
10
/sys/devices/system/cpu/cpu4/cpu_capacity
1024
/sys/devices/system/cpu/cpu4/cache/uevent
/sys/devices/system/cpu/cpu4/cache/index2/uevent
/sys/devices/system/cpu/cpu4/cache/index2/shared_cpu_list
4-7
/sys/devices/system/cpu/cpu4/cache/index2/type
Unified
/sys/devices/system/cpu/cpu4/cache/index2/level
2
/sys/devices/system/cpu/cpu4/cache/index2/shared_cpu_map
f0
/sys/devices/system/cpu/cpu4/cache/index0/uevent
/sys/devices/system/cpu/cpu4/cache/index0/shared_cpu_list
4
/sys/devices/system/cpu/cpu4/cache/index0/type
Data
/sys/devices/system/cpu/cpu4/cache/index0/level
1
/sys/devices/system/cpu/cpu4/cache/index0/shared_cpu_map
10
/sys/devices/system/cpu/cpu4/cache/index1/uevent
/sys/devices/system/cpu/cpu4/cache/index1/shared_cpu_list
4
/sys/devices/system/cpu/cpu4/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu4/cache/index1/level
1
/sys/devices/system/cpu/cpu4/cache/index1/shared_cpu_map
10
/sys/devices/system/cpu/cpu4/regs/identification/revidr_el1
0x0000000000000001
/sys/devices/system/cpu/cpu4/regs/identification/midr_el1
0x0000000051af8001
/sys/devices/system/cpu/isolated

/sys/devices/system/cpu/kernel_max
255
/sys/devices/system/cpu/cpu2/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu2/cpuidle/state1/above
27
/sys/devices/system/cpu/cpu2/cpuidle/state1/time
80485
/sys/devices/system/cpu/cpu2/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu2/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu2/cpuidle/state1/latency
129
/sys/devices/system/cpu/cpu2/cpuidle/state1/usage
142
/sys/devices/system/cpu/cpu2/cpuidle/state1/desc
little-retention
/sys/devices/system/cpu/cpu2/cpuidle/state1/below
6
/sys/devices/system/cpu/cpu2/cpuidle/state1/name
cpu-sleep-0-0
/sys/devices/system/cpu/cpu2/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu2/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu2/cpuidle/state2/above
14
/sys/devices/system/cpu/cpu2/cpuidle/state2/time
617916929
/sys/devices/system/cpu/cpu2/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu2/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu2/cpuidle/state2/latency
712
/sys/devices/system/cpu/cpu2/cpuidle/state2/usage
614
/sys/devices/system/cpu/cpu2/cpuidle/state2/desc
little-power-collapse
/sys/devices/system/cpu/cpu2/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu2/cpuidle/state2/name
cpu-sleep-0-1
/sys/devices/system/cpu/cpu2/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu2/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu2/cpuidle/state0/time
36601
/sys/devices/system/cpu/cpu2/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu2/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu2/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu2/cpuidle/state0/usage
49
/sys/devices/system/cpu/cpu2/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu2/cpuidle/state0/below
20
/sys/devices/system/cpu/cpu2/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu2/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@2
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu2/power/runtime_active_time
0
/sys/devices/system/cpu/cpu2/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu2/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu2/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu2/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu2/power/control
auto
/sys/devices/system/cpu/cpu2/topology/physical_package_id
0
/sys/devices/system/cpu/cpu2/topology/core_siblings
0f
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-3
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list
2
/sys/devices/system/cpu/cpu2/topology/core_id
2
/sys/devices/system/cpu/cpu2/topology/thread_siblings
04
/sys/devices/system/cpu/cpu2/cpu_capacity
1024
/sys/devices/system/cpu/cpu2/cache/uevent
/sys/devices/system/cpu/cpu2/cache/index2/uevent
/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_list
0-3
/sys/devices/system/cpu/cpu2/cache/index2/type
Unified
/sys/devices/system/cpu/cpu2/cache/index2/level
2
/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_map
0f
/sys/devices/system/cpu/cpu2/cache/index0/uevent
/sys/devices/system/cpu/cpu2/cache/index0/shared_cpu_list
2
/sys/devices/system/cpu/cpu2/cache/index0/type
Data
/sys/devices/system/cpu/cpu2/cache/index0/level
1
/sys/devices/system/cpu/cpu2/cache/index0/shared_cpu_map
04
/sys/devices/system/cpu/cpu2/cache/index1/uevent
/sys/devices/system/cpu/cpu2/cache/index1/shared_cpu_list
2
/sys/devices/system/cpu/cpu2/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu2/cache/index1/level
1
/sys/devices/system/cpu/cpu2/cache/index1/shared_cpu_map
04
/sys/devices/system/cpu/cpu2/regs/identification/revidr_el1
0x0000000000000180
/sys/devices/system/cpu/cpu2/regs/identification/midr_el1
0x0000000051af8014
/sys/devices/system/cpu/cpu0/cpuidle/state1/disable
0
/sys/devices/system/cpu/cpu0/cpuidle/state1/above
42
/sys/devices/system/cpu/cpu0/cpuidle/state1/time
363386
/sys/devices/system/cpu/cpu0/cpuidle/state1/power
0
/sys/devices/system/cpu/cpu0/cpuidle/state1/residency
200
/sys/devices/system/cpu/cpu0/cpuidle/state1/latency
129
/sys/devices/system/cpu/cpu0/cpuidle/state1/usage
416
/sys/devices/system/cpu/cpu0/cpuidle/state1/desc
little-retention
/sys/devices/system/cpu/cpu0/cpuidle/state1/below
117
/sys/devices/system/cpu/cpu0/cpuidle/state1/name
cpu-sleep-0-0
/sys/devices/system/cpu/cpu0/cpuidle/driver/name
arm_idle
/sys/devices/system/cpu/cpu0/cpuidle/state2/disable
0
/sys/devices/system/cpu/cpu0/cpuidle/state2/above
189
/sys/devices/system/cpu/cpu0/cpuidle/state2/time
616567065
/sys/devices/system/cpu/cpu0/cpuidle/state2/power
0
/sys/devices/system/cpu/cpu0/cpuidle/state2/residency
1000
/sys/devices/system/cpu/cpu0/cpuidle/state2/latency
712
/sys/devices/system/cpu/cpu0/cpuidle/state2/usage
1661
/sys/devices/system/cpu/cpu0/cpuidle/state2/desc
little-power-collapse
/sys/devices/system/cpu/cpu0/cpuidle/state2/below
0
/sys/devices/system/cpu/cpu0/cpuidle/state2/name
cpu-sleep-0-1
/sys/devices/system/cpu/cpu0/cpuidle/state0/disable
0
/sys/devices/system/cpu/cpu0/cpuidle/state0/above
0
/sys/devices/system/cpu/cpu0/cpuidle/state0/time
7123
/sys/devices/system/cpu/cpu0/cpuidle/state0/power
4294967295
/sys/devices/system/cpu/cpu0/cpuidle/state0/residency
1
/sys/devices/system/cpu/cpu0/cpuidle/state0/latency
1
/sys/devices/system/cpu/cpu0/cpuidle/state0/usage
53
/sys/devices/system/cpu/cpu0/cpuidle/state0/desc
ARM WFI
/sys/devices/system/cpu/cpu0/cpuidle/state0/below
14
/sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
/sys/devices/system/cpu/cpu0/uevent
OF_NAME=cpu
OF_FULLNAME=/cpus/cpu@0
OF_TYPE=cpu
OF_COMPATIBLE_0=arm,armv8
OF_COMPATIBLE_N=1
MODALIAS=cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B

/sys/devices/system/cpu/cpu0/power/runtime_active_time
0
/sys/devices/system/cpu/cpu0/power/pm_qos_resume_latency_us
0
/sys/devices/system/cpu/cpu0/power/runtime_status
unsupported
/sys/devices/system/cpu/cpu0/power/autosuspend_delay_ms
cat: read error: Input/output error
/sys/devices/system/cpu/cpu0/power/runtime_suspended_time
0
/sys/devices/system/cpu/cpu0/power/control
auto
/sys/devices/system/cpu/cpu0/topology/physical_package_id
0
/sys/devices/system/cpu/cpu0/topology/core_siblings
0f
/sys/devices/system/cpu/cpu0/topology/core_siblings_list
0-3
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list
0
/sys/devices/system/cpu/cpu0/topology/core_id
0
/sys/devices/system/cpu/cpu0/topology/thread_siblings
01
/sys/devices/system/cpu/cpu0/cpu_capacity
1024
/sys/devices/system/cpu/cpu0/cache/uevent
/sys/devices/system/cpu/cpu0/cache/index2/uevent
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list
0-3
/sys/devices/system/cpu/cpu0/cache/index2/type
Unified
/sys/devices/system/cpu/cpu0/cache/index2/level
2
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map
0f
/sys/devices/system/cpu/cpu0/cache/index0/uevent
/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list
0
/sys/devices/system/cpu/cpu0/cache/index0/type
Data
/sys/devices/system/cpu/cpu0/cache/index0/level
1
/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_map
01
/sys/devices/system/cpu/cpu0/cache/index1/uevent
/sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_list
0
/sys/devices/system/cpu/cpu0/cache/index1/type
Instruction
/sys/devices/system/cpu/cpu0/cache/index1/level
1
/sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_map
01
/sys/devices/system/cpu/cpu0/regs/identification/revidr_el1
0x0000000000000180
/sys/devices/system/cpu/cpu0/regs/identification/midr_el1
0x0000000051af8014
/sys/devices/system/cpu/modalias
cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,000B


^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 7/9] arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  2019-05-22  9:35       ` Marc Zyngier
@ 2019-05-22 15:39         ` Marc Gonzalez
  0 siblings, 0 replies; 27+ messages in thread
From: Marc Gonzalez @ 2019-05-22 15:39 UTC (permalink / raw)
  To: Marc Zyngier, MSM, Linux ARM
  Cc: Amit Kucheria, Bjorn Andersson, Daniel Lezcano, Niklas Cassel,
	Jeffrey Hugo, Sibi Sankar, Mark Rutland, Lorenzo Pieralisi,
	Robin Murphy, Sudeep Holla

On 22/05/2019 11:35, Marc Zyngier wrote:

> On 22/05/2019 10:17, Marc Gonzalez wrote:
> 
>> The following dmesg log caught my eye, and might be relevant:
>>
>> 	ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware
>>
>> Is that bad, doctor? I don't think it would explain the crash though...
> 
> It doesn't explain it.
> 
> It is bad though: your vendor doesn't tell the kernel about the HW being
> free of Spectre-v2, and doesn't provide a mitigation either. Hopefully,
> this is a responsible vendor that will provide you with a firmware
> update that fixes it.

# cd /sys/devices/system/cpu/vulnerabilities/
# grep "" *
l1tf:Not affected
mds:Not affected
meltdown:Mitigation: PTI
spec_store_bypass:Vulnerable
spectre_v1:Mitigation: __user pointer sanitization
spectre_v2:Vulnerable

OK, so there are apparently two unmitigated vulns, spec_store_bypass
and spectre_v2.

These vulns need to be mitigated in FW because otherwise some secure
property of the secure OS could be violated? Or because disabling the
faulty optimization requires secure privileges?


Some documentation, for my own reference:

https://elixir.bootlin.com/linux/latest/source/Documentation/ABI/testing/sysfs-devices-system-cpu
https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability

Regards.

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 6/9] arm64: dts: qcom: msm8996: Add PSCI cpuidle low power states
  2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
  2019-05-21 10:13   ` Daniel Lezcano
  2019-05-22  3:49   ` Bjorn Andersson
@ 2019-05-23 21:24   ` Niklas Cassel
  2 siblings, 0 replies; 27+ messages in thread
From: Niklas Cassel @ 2019-05-23 21:24 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	marc.w.gonzalez, sibis, daniel.lezcano, Andy Gross, David Brown,
	Li Yang, Shawn Guo, devicetree

On Tue, May 21, 2019 at 03:05:16PM +0530, Amit Kucheria wrote:
> Add device bindings for cpuidle states for cpu devices.
> 
> msm8996 features 4 cpus - 2 in each cluster. However, all cpus implement
> the same microarchitecture and the two clusters only differ in the
> maximum frequency attainable by the CPUs.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c761269caf80..4f2fb7885f39 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -95,6 +95,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  			L2_0: l2-cache {
>  			      compatible = "cache";
> @@ -107,6 +108,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x1>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -115,6 +117,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  			L2_1: l2-cache {
>  			      compatible = "cache";
> @@ -127,6 +130,7 @@
>  			compatible = "qcom,kryo";
>  			reg = <0x0 0x101>;
>  			enable-method = "psci";
> +			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_1>;
>  		};
>  
> @@ -151,6 +155,19 @@
>  				};
>  			};
>  		};
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP_0: cpu-sleep-0 {
> +				compatible = "arm,idle-state";
> +				idle-state-name = "standalone-power-collapse";
> +				arm,psci-suspend-param = <0x00000004>;
> +				entry-latency-us = <40>;
> +				exit-latency-us = <80>;

Hello Amit,

Looking at this line of code in msm-4.14:
https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/drivers/cpuidle/lpm-levels.c?h=LA.UM.7.1.r1-14000-sm8150.0#n993

And seeing the equivalent in msm-4.4:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/cpuidle/lpm-levels.c?h=msm-4.4#n1080

It becomes obvious that

qcom,time-overhead == entry-latency-us + exit-latency-us
and
qcom,latency-us == exit-latency-us

which means that

entry-latency-us == qcom,time-overhead - qcom,latency-us


Using this formula, with the numbers from downstream SDM845:
https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi?h=msm-4.9#n123

qcom,latency-us = <621>;
qcom,time-overhead = <885>;

885 - 621 = 264

we end up with the same values that Raju
has in his submission for upstream SDM845:
https://patchwork.kernel.org/patch/10953253/

entry-latency-us = <264>;
exit-latency-us = <621>;



Which for msm8996:

qcom,latency-us = <80>;
qcom,time-overhead = <210>;

gives:

entry-latency-us = <130>
exit-latency-us = <80>;

> +				min-residency-us = <300>;
> +			};
> +		};
>  	};
>  
>  	thermal-zones {
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 27+ messages in thread

* Re: [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property
  2019-05-21  9:35 ` [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Amit Kucheria
  2019-05-21 10:34   ` Marc Gonzalez
@ 2019-06-13 23:13   ` Rob Herring
  1 sibling, 0 replies; 27+ messages in thread
From: Rob Herring @ 2019-06-13 23:13 UTC (permalink / raw)
  To: Amit Kucheria
  Cc: linux-kernel, linux-arm-msm, bjorn.andersson, agross,
	niklas.cassel, marc.w.gonzalez, sibis, daniel.lezcano,
	Andy Gross, David Brown, Li Yang, Shawn Guo, devicetree

On Tue, 21 May 2019 15:05:12 +0530, Amit Kucheria wrote:
> The "enable-method" property for cpu nodes needs to be "psci" for CPU
> idle management to be setup correctly.
> 
> Add a note to the binding documentation to this effect to make it
> obvious.
> 
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
>  .../devicetree/bindings/arm/idle-states.txt         | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 

Applied, thanks.

Rob

^ permalink raw reply	[flat|nested] 27+ messages in thread

end of thread, back to index

Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-21  9:35 [PATCH v2 0/9] qcom: Add cpuidle to some platforms Amit Kucheria
2019-05-21  9:35 ` [PATCH v2 1/9] arm64: dts: fsl: ls1028a: Fix entry-method property to reflect documentation Amit Kucheria
2019-05-21  9:35 ` [PATCH v2 2/9] Documentation: arm: Link idle-states binding to "enable-method" property Amit Kucheria
2019-05-21 10:34   ` Marc Gonzalez
2019-06-13 23:13   ` Rob Herring
2019-05-21  9:35 ` [PATCH v2 3/9] arm64: dts: qcom: msm8916: Add entry-method property for the idle-states node Amit Kucheria
2019-05-22  3:30   ` Bjorn Andersson
2019-05-21  9:35 ` [PATCH v2 4/9] arm64: dts: qcom: msm8916: Use more generic idle state names Amit Kucheria
2019-05-22  3:30   ` Bjorn Andersson
2019-05-21  9:35 ` [PATCH v2 5/9] arm64: dts: qcom: qcs404: Add PSCI cpuidle low power states Amit Kucheria
2019-05-22  3:31   ` Bjorn Andersson
2019-05-21  9:35 ` [PATCH v2 6/9] arm64: dts: qcom: msm8996: " Amit Kucheria
2019-05-21 10:13   ` Daniel Lezcano
2019-05-22  3:49   ` Bjorn Andersson
2019-05-23 21:24   ` Niklas Cassel
2019-05-21  9:35 ` [PATCH v2 7/9] arm64: dts: qcom: msm8998: " Amit Kucheria
2019-05-21 12:03   ` Marc Gonzalez
2019-05-21 16:10     ` Marc Gonzalez
2019-05-22  9:17     ` Marc Gonzalez
2019-05-22  9:35       ` Marc Zyngier
2019-05-22 15:39         ` Marc Gonzalez
2019-05-22 14:48       ` Marc Gonzalez
2019-05-21  9:35 ` [PATCH v2 8/9] arm64: dts: qcom: sdm845: " Amit Kucheria
2019-05-22  3:59   ` Bjorn Andersson
2019-05-21  9:35 ` [PATCH v2 9/9] arm64: dts: msm8996: Add proper capacity scaling for the cpus Amit Kucheria
2019-05-21 10:14   ` Daniel Lezcano
2019-05-22  3:50   ` Bjorn Andersson

Linux-ARM-MSM Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
		linux-arm-msm@vger.kernel.org linux-arm-msm@archiver.kernel.org
	public-inbox-index linux-arm-msm


Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm


AGPL code for this site: git clone https://public-inbox.org/ public-inbox