Linux-ARM-MSM Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v3 00/14] Support CPU frequency scaling on QCS404
@ 2019-06-25 16:47 Jorge Ramirez-Ortiz
  2019-06-25 16:47 ` [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Jorge Ramirez-Ortiz
                   ` (13 more replies)
  0 siblings, 14 replies; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

The following patchset enables CPU frequency scaling support on the
QCS404 (with dynamic voltage scaling).

Patch 8 "clk: qcom: hfpll: CLK_IGNORE_UNUSED" is a bit controversial;
in this platform, this PLL provides the clock signal to a CPU
core. But in others it might not.

We opted for the minimal ammount of changes without affecting the
default functionality: simply bypassing the COMMON_CLK_DISABLE_UNUSED
framework and letting the firwmare chose whether to enable or disable
the clock at boot. However maybe a DT property and marking the clock
as critical would be more appropriate for this PLL. we'd appreciate the
maintainer's input on this topic.

v2:
   - dts: ms8916: apcs mux/divider: new bindings
     (the driver can still support the old bindings)
     
   - qcs404.dtsi
     fix apcs-hfpll definition
     fix cpu_opp_table definition
     
   - GPLL0_AO_OUT operating frequency
     define new alpha_pll_fixed_ops to limit the operating frequency

v3:
  - qcom-apcs-ipc-mailbox
    replace goto to ease readability
    
  - apcs-msm8916.c
    rework patch to use of_clk_parent_fill

  - hfpll.c
    add relevant comments to the code

  - qcs404.dtsi
    add voltage scaling support

Jorge Ramirez-Ortiz (14):
  clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
  mbox: qcom: add APCS child device for QCS404
  mbox: qcom: replace integer with valid macro
  dt-bindings: mailbox: qcom: Add clock-name optional property
  clk: qcom: apcs-msm8916: get parent clock names from DT
  clk: qcom: hfpll: get parent clock names from DT
  clk: qcom: hfpll: register as clock provider
  clk: qcom: hfpll: CLK_IGNORE_UNUSED
  arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
  arm64: dts: qcom: qcs404: Add OPP table
  arm64: dts: qcom: qcs404: Add HFPLL node
  arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider
  arm64: dts: qcom: qcs404: Add DVFS support
  arm64: defconfig: Enable HFPLL

 .../mailbox/qcom,apcs-kpss-global.txt         | 24 +++++++++--
 arch/arm64/boot/dts/qcom/msm8916.dtsi         |  3 +-
 arch/arm64/boot/dts/qcom/qcs404.dtsi          | 42 +++++++++++++++++++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/clk/qcom/apcs-msm8916.c               | 23 ++++++++--
 drivers/clk/qcom/clk-alpha-pll.c              |  8 ++++
 drivers/clk/qcom/clk-alpha-pll.h              |  1 +
 drivers/clk/qcom/gcc-qcs404.c                 |  2 +-
 drivers/clk/qcom/hfpll.c                      | 25 ++++++++++-
 drivers/mailbox/qcom-apcs-ipc-mailbox.c       | 18 ++++----
 10 files changed, 130 insertions(+), 17 deletions(-)

-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:30   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404 Jorge Ramirez-Ortiz
                   ` (12 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
specifications.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++
 drivers/clk/qcom/clk-alpha-pll.h | 1 +
 drivers/clk/qcom/gcc-qcs404.c    | 2 +-
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0ced4a5a9a17..ef51f302bdf0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 }
 
+const struct clk_ops clk_alpha_pll_fixed_ops = {
+	.enable = clk_alpha_pll_enable,
+	.disable = clk_alpha_pll_disable,
+	.is_enabled = clk_alpha_pll_is_enabled,
+	.recalc_rate = clk_alpha_pll_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
+
 const struct clk_ops clk_alpha_pll_ops = {
 	.enable = clk_alpha_pll_enable,
 	.disable = clk_alpha_pll_disable,
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 66755f0f84fc..6b4eb74706b4 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -104,6 +104,7 @@ struct alpha_pll_config {
 };
 
 extern const struct clk_ops clk_alpha_pll_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 extern const struct clk_ops clk_alpha_pll_huayra_ops;
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 29cf464dd2c8..18c6563889f3 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
 			.parent_names = (const char *[]){ "cxo" },
 			.num_parents = 1,
 			.flags = CLK_IS_CRITICAL,
-			.ops = &clk_alpha_pll_ops,
+			.ops = &clk_alpha_pll_fixed_ops,
 		},
 	},
 };
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
  2019-06-25 16:47 ` [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 14:44   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 03/14] mbox: qcom: replace integer with valid macro Jorge Ramirez-Ortiz
                   ` (11 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

There is clock controller functionality in the APCS hardware block of
qcs404 devices similar to msm8916.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 drivers/mailbox/qcom-apcs-ipc-mailbox.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 705e17a5479c..a05dc3aabac7 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -89,16 +89,18 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
-		apcs->clk = platform_device_register_data(&pdev->dev,
-							  "qcom-apcs-msm8916-clk",
-							  -1, NULL, 0);
-		if (IS_ERR(apcs->clk))
-			dev_err(&pdev->dev, "failed to register APCS clk\n");
-	}
-
 	platform_set_drvdata(pdev, apcs);
 
+	if (!of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global") &&
+	    !of_device_is_compatible(np, "qcom,qcs404-apcs-apps-global"))
+		return 0;
+
+	apcs->clk = platform_device_register_data(&pdev->dev,
+						  "qcom-apcs-msm8916-clk",
+						  -1, NULL, 0);
+	if (IS_ERR(apcs->clk))
+		dev_err(&pdev->dev, "failed to register APCS clk\n");
+
 	return 0;
 }
 
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 03/14] mbox: qcom: replace integer with valid macro
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
  2019-06-25 16:47 ` [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Jorge Ramirez-Ortiz
  2019-06-25 16:47 ` [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404 Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 14:37   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property Jorge Ramirez-Ortiz
                   ` (10 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Use the correct macro when registering the platform device.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index a05dc3aabac7..c8088e9caf02 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -97,7 +97,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
 
 	apcs->clk = platform_device_register_data(&pdev->dev,
 						  "qcom-apcs-msm8916-clk",
-						  -1, NULL, 0);
+						  PLATFORM_DEVID_NONE, NULL, 0);
 	if (IS_ERR(apcs->clk))
 		dev_err(&pdev->dev, "failed to register APCS clk\n");
 
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (2 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 03/14] mbox: qcom: replace integer with valid macro Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 14:45   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT Jorge Ramirez-Ortiz
                   ` (9 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

When the APCS clock is registered (platform dependent), it retrieves
its parent names from hardcoded values in the driver.

The following commit allows the DT node to provide such clock names to
the platform data based clock driver therefore avoiding having to
explicitly embed those names in the clock driver source code.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../mailbox/qcom,apcs-kpss-global.txt         | 24 ++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 1232fc9fc709..b69310322b09 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -18,10 +18,11 @@ platforms.
 	Usage: required
 	Value type: <prop-encoded-array>
 	Definition: must specify the base address and size of the global block
+
 - clocks:
-	Usage: required if #clocks-cells property is present
-	Value type: <phandle>
-	Definition: phandle to the input PLL, which feeds the APCS mux/divider
+	Usage: required if #clock-names property is present
+	Value type: <phandle array>
+	Definition: phandles to the two parent clocks of the clock driver.
 
 - #mbox-cells:
 	Usage: required
@@ -33,6 +34,12 @@ platforms.
 	Value type: <u32>
 	Definition: as described in clock.txt, must be 0
 
+- clock-names:
+	Usage: required if the platform data based clock driver needs to
+	retrieve the parent clock names from device tree.
+	This will requires two mandatory clocks to be defined.
+	Value type: <string-array>
+	Definition: must be "aux" and "pll"
 
 = EXAMPLE
 The following example describes the APCS HMSS found in MSM8996 and part of the
@@ -65,3 +72,14 @@ Below is another example of the APCS binding on MSM8916 platforms:
 		clocks = <&a53pll>;
 		#clock-cells = <0>;
 	};
+
+Below is another example of the APCS binding on QCS404 platforms:
+
+	apcs_glb: mailbox@b011000 {
+		compatible = "qcom,qcs404-apcs-apps-global", "syscon";
+		reg = <0x0b011000 0x1000>;
+		#mbox-cells = <1>;
+		clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
+		clock-names = "aux", "pll";
+		#clock-cells = <0>;
+	};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (3 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 14:58   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 06/14] clk: qcom: hfpll: " Jorge Ramirez-Ortiz
                   ` (8 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Allow accessing the parent clock names required for the driver
operation by using the device tree node.

This permits extending the driver to other platforms without having to
modify its source code.

For backwards compatibility leave previous values as default.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 drivers/clk/qcom/apcs-msm8916.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
index a6c89a310b18..dd82eb1e5202 100644
--- a/drivers/clk/qcom/apcs-msm8916.c
+++ b/drivers/clk/qcom/apcs-msm8916.c
@@ -19,7 +19,7 @@
 
 static const u32 gpll0_a53cc_map[] = { 4, 5 };
 
-static const char * const gpll0_a53cc[] = {
+static const char *gpll0_a53cc[] = {
 	"gpll0_vote",
 	"a53pll",
 };
@@ -50,6 +50,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
 	struct regmap *regmap;
 	struct clk_init_data init = { };
 	int ret = -ENODEV;
+	const char *parents[2];
+	int pll_index = 0;
 
 	regmap = dev_get_regmap(parent, NULL);
 	if (!regmap) {
@@ -61,6 +63,16 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
 	if (!a53cc)
 		return -ENOMEM;
 
+	/* legacy bindings only defined the pll parent clock (index = 0) with no
+	 * name; when both of the parents are specified in the bindings, the
+	 * pll is the second one (index = 1).
+	 */
+	if (of_clk_parent_fill(parent->of_node, parents, 2) == 2) {
+		gpll0_a53cc[0] = parents[0];
+		gpll0_a53cc[1] = parents[1];
+		pll_index = 1;
+	}
+
 	init.name = "a53mux";
 	init.parent_names = gpll0_a53cc;
 	init.num_parents = ARRAY_SIZE(gpll0_a53cc);
@@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
 	a53cc->src_shift = 8;
 	a53cc->parent_map = gpll0_a53cc_map;
 
-	a53cc->pclk = devm_clk_get(parent, NULL);
+	a53cc->pclk = of_clk_get(parent->of_node, pll_index);
 	if (IS_ERR(a53cc->pclk)) {
 		ret = PTR_ERR(a53cc->pclk);
-		dev_err(dev, "failed to get clk: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "failed to get clk: %d\n", ret);
 		return ret;
 	}
 
@@ -87,6 +100,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
 	ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
 	if (ret) {
 		dev_err(dev, "failed to register clock notifier: %d\n", ret);
+		clk_put(a53cc->pclk);
 		return ret;
 	}
 
@@ -109,6 +123,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
 
 err:
 	clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+	clk_put(a53cc->pclk);
+
 	return ret;
 }
 
@@ -117,6 +133,7 @@ static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
 	struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
 
 	clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
+	clk_put(a53cc->pclk);
 
 	return 0;
 }
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 06/14] clk: qcom: hfpll: get parent clock names from DT
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (4 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` " Jorge Ramirez-Ortiz
  2019-07-11 15:07   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider Jorge Ramirez-Ortiz
                   ` (7 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Allow accessing the parent clock name required for the driver
operation using the device tree node.

This permits extending the driver to other platforms without having to
modify its source code.

For backwards compatibility leave the previous value as default.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 drivers/clk/qcom/hfpll.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index a6de7101430c..87b7f46d27e0 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -52,6 +52,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 	void __iomem *base;
 	struct regmap *regmap;
 	struct clk_hfpll *h;
+	struct clk *pclk;
 	struct clk_init_data init = {
 		.parent_names = (const char *[]){ "xo" },
 		.num_parents = 1,
@@ -75,6 +76,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 					  0, &init.name))
 		return -ENODEV;
 
+	/* get parent clock from device tree (optional) */
+	pclk = devm_clk_get(dev, "xo");
+	if (!IS_ERR(pclk))
+		init.parent_names = (const char *[]){ __clk_get_name(pclk) };
+	else if (PTR_ERR(pclk) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
+
 	h->d = &hdata;
 	h->clkr.hw.init = &init;
 	spin_lock_init(&h->lock);
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (5 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 06/14] clk: qcom: hfpll: " Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:07   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED Jorge Ramirez-Ortiz
                   ` (6 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Make the output of the high frequency pll a clock provider.
On the QCS404 this PLL controls cpu frequency scaling.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/qcom/hfpll.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index 87b7f46d27e0..0ffed0d41c50 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -53,6 +53,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 	struct regmap *regmap;
 	struct clk_hfpll *h;
 	struct clk *pclk;
+	int ret;
 	struct clk_init_data init = {
 		.parent_names = (const char *[]){ "xo" },
 		.num_parents = 1,
@@ -87,7 +88,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 	h->clkr.hw.init = &init;
 	spin_lock_init(&h->lock);
 
-	return devm_clk_register_regmap(&pdev->dev, &h->clkr);
+	ret = devm_clk_register_regmap(dev, &h->clkr);
+	if (ret) {
+		dev_err(dev, "failed to register regmap clock: %d\n", ret);
+		return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+					   &h->clkr.hw);
 }
 
 static struct platform_driver qcom_hfpll_driver = {
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (6 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:16   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Jorge Ramirez-Ortiz
                   ` (5 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
to keep the software model of the clock in line with reality, the
framework transverses the clock tree and disables those clocks that
were enabled by the firmware but have not been enabled by any device
driver.

If CPUFREQ is enabled, early during the system boot, it might attempt
to change the CPU frequency ("set_rate"). If the HFPLL is selected as
a provider, it will then change the rate for this clock.

As boot continues, clk_disable_unused_subtree will run. Since it wont
find a valid counter (enable_count) for a clock that is actually
enabled it will attempt to disable it which will cause the CPU to
stop. Notice that in this driver, calls to check whether the clock is
enabled are routed via the is_enabled callback which queries the
hardware.

The following commit, rather than marking the clock critical and
forcing the clock to be always enabled, addresses the above scenario
making sure the clock is not disabled but it continues to rely on the
firmware to enable the clock.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 drivers/clk/qcom/hfpll.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index 0ffed0d41c50..d5fd27938e7b 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -58,6 +58,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
 		.parent_names = (const char *[]){ "xo" },
 		.num_parents = 1,
 		.ops = &clk_ops_hfpll,
+		/*
+		 * rather than marking the clock critical and forcing the clock
+		 * to be always enabled, we make sure that the clock is not
+		 * disabled: the firmware remains responsible of enabling this
+		 * clock (for more info check the commit log)
+		 */
+		.flags = CLK_IGNORE_UNUSED,
 	};
 
 	h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (7 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:24   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table Jorge Ramirez-Ortiz
                   ` (4 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.

The driver still supports the previous bindings; however with this
update it we allow the msm8916 to access the parent clock names
required by the driver operation using the device tree node.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5ea9fb8f2f87..96dc7a12aa94 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -429,7 +429,8 @@
 			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 			reg = <0xb011000 0x1000>;
 			#mbox-cells = <1>;
-			clocks = <&a53pll>;
+			clocks = <&gcc GPLL0_VOTE>, <&a53pll>;
+			clock-names = "aux", "pll";
 			#clock-cells = <0>;
 		};
 
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (8 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:25   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node Jorge Ramirez-Ortiz
                   ` (3 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Add a CPU OPP table to qcs404

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 3f17e1b09c13..d876dae5b0a5 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -83,6 +83,24 @@
 		};
 	};
 
+	cpu_opp_table: cpu-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1094400000 {
+			opp-hz = /bits/ 64 <1094400000>;
+			opp-microvolt = <1224000 1224000 1224000>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			opp-microvolt = <1288000 1288000 1288000>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			opp-microvolt = <1384000 1384000 1384000>;
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-qcs404", "qcom,scm";
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (9 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:25   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Jorge Ramirez-Ortiz
                   ` (2 subsequent siblings)
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

The high frequency pll functionality is required to enable CPU
frequency scaling operation.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index d876dae5b0a5..94471aa31979 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -852,6 +852,15 @@
 			#mbox-cells = <1>;
 		};
 
+		apcs_hfpll: clock-controller@b016000 {
+			compatible = "qcom,hfpll";
+			reg = <0x0b016000 0x30>;
+			#clock-cells = <0>;
+			clock-output-names = "apcs_hfpll";
+			clocks = <&xo_board>;
+			clock-names = "xo";
+		};
+
 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (10 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:27   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support Jorge Ramirez-Ortiz
  2019-06-25 16:47 ` [PATCH v3 14/14] arm64: defconfig: Enable HFPLL Jorge Ramirez-Ortiz
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Specify the clocks that feed the APCS mux/divider instead of using
default hardcoded values in the source code.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 94471aa31979..9569686dbc41 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -850,6 +850,9 @@
 			compatible = "qcom,qcs404-apcs-apps-global", "syscon";
 			reg = <0x0b011000 0x1000>;
 			#mbox-cells = <1>;
+			clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
+			clock-names = "aux", "pll";
+			#clock-cells = <0>;
 		};
 
 		apcs_hfpll: clock-controller@b016000 {
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (11 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-06-26  9:08   ` Niklas Cassel
  2019-07-11 15:29   ` Bjorn Andersson
  2019-06-25 16:47 ` [PATCH v3 14/14] arm64: defconfig: Enable HFPLL Jorge Ramirez-Ortiz
  13 siblings, 2 replies; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

Support dynamic voltage and frequency scaling on qcs404.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 9569686dbc41..4b4ce0b5df76 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -34,6 +34,9 @@
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			cpu-supply = <&pms405_s3>;
 		};
 
 		CPU1: cpu@101 {
@@ -43,6 +46,9 @@
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			cpu-supply = <&pms405_s3>;
 		};
 
 		CPU2: cpu@102 {
@@ -52,6 +58,9 @@
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			cpu-supply = <&pms405_s3>;
 		};
 
 		CPU3: cpu@103 {
@@ -61,6 +70,9 @@
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			next-level-cache = <&L2_0>;
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			cpu-supply = <&pms405_s3>;
 		};
 
 		L2_0: l2-cache {
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* [PATCH v3 14/14] arm64: defconfig: Enable HFPLL
  2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
                   ` (12 preceding siblings ...)
  2019-06-25 16:47 ` [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support Jorge Ramirez-Ortiz
@ 2019-06-25 16:47 ` Jorge Ramirez-Ortiz
  2019-07-11 15:27   ` Bjorn Andersson
  13 siblings, 1 reply; 33+ messages in thread
From: Jorge Ramirez-Ortiz @ 2019-06-25 16:47 UTC (permalink / raw)
  To: jorge.ramirez-ortiz, sboyd, bjorn.andersson, david.brown,
	jassisinghbrar, mark.rutland, mturquette, robh+dt, will.deacon,
	arnd, horms+renesas, heiko, sibis, enric.balletbo, jagan, olof
  Cc: vkoul, niklas.cassel, georgi.djakov, amit.kucheria, devicetree,
	linux-kernel, linux-arm-kernel, linux-clk, linux-arm-msm,
	khasim.mohammed

The high frequency pll is required on compatible Qualcomm SoCs to
support the CPU frequency scaling feature.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fbbc065415d4..7cc4ad24dfe5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -671,6 +671,7 @@ CONFIG_MSM_MMCC_8996=y
 CONFIG_MSM_GCC_8998=y
 CONFIG_QCS_GCC_404=y
 CONFIG_SDM_GCC_845=y
+CONFIG_QCOM_HFPLL=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_ARM_MHU=y
-- 
2.21.0


^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
  2019-06-25 16:47 ` [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support Jorge Ramirez-Ortiz
@ 2019-06-26  9:08   ` Niklas Cassel
  2019-06-26  9:10     ` Niklas Cassel
  2019-07-11 15:29   ` Bjorn Andersson
  1 sibling, 1 reply; 33+ messages in thread
From: Niklas Cassel @ 2019-06-26  9:08 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: Stephen Boyd, Bjorn Andersson, David Brown, jassisinghbrar,
	Mark Rutland, Michael Turquette, Rob Herring, Will Deacon, arnd,
	horms+renesas, heiko, Sibi Sankar, enric.balletbo, Jagan Teki,
	olof, Vinod Koul, Georgi Djakov, Amit Kucheria, devicetree,
	Linux Kernel Mailing List, Linux ARM, linux-clk, linux-arm-msm,
	Khasim Syed Mohammed

I actually think that it makes sense to squash this patch with the
[PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table
patch.

But that might be a personal preference.

Either way, I think this series in ready for the real mailing list.




On Tue, 25 Jun 2019 at 18:48, Jorge Ramirez-Ortiz
<jorge.ramirez-ortiz@linaro.org> wrote:
>
> Support dynamic voltage and frequency scaling on qcs404.
>
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 9569686dbc41..4b4ce0b5df76 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -34,6 +34,9 @@
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SLEEP_0>;
>                         next-level-cache = <&L2_0>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       cpu-supply = <&pms405_s3>;
>                 };
>
>                 CPU1: cpu@101 {
> @@ -43,6 +46,9 @@
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SLEEP_0>;
>                         next-level-cache = <&L2_0>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       cpu-supply = <&pms405_s3>;
>                 };
>
>                 CPU2: cpu@102 {
> @@ -52,6 +58,9 @@
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SLEEP_0>;
>                         next-level-cache = <&L2_0>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       cpu-supply = <&pms405_s3>;
>                 };
>
>                 CPU3: cpu@103 {
> @@ -61,6 +70,9 @@
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SLEEP_0>;
>                         next-level-cache = <&L2_0>;
> +                       clocks = <&apcs_glb>;
> +                       operating-points-v2 = <&cpu_opp_table>;
> +                       cpu-supply = <&pms405_s3>;
>                 };
>
>                 L2_0: l2-cache {
> --
> 2.21.0
>

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
  2019-06-26  9:08   ` Niklas Cassel
@ 2019-06-26  9:10     ` Niklas Cassel
  0 siblings, 0 replies; 33+ messages in thread
From: Niklas Cassel @ 2019-06-26  9:10 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: Stephen Boyd, Bjorn Andersson, David Brown, jassisinghbrar,
	Mark Rutland, Michael Turquette, Rob Herring, Will Deacon, arnd,
	horms+renesas, heiko, Sibi Sankar, enric.balletbo, Jagan Teki,
	olof, Vinod Koul, Georgi Djakov, Amit Kucheria, devicetree,
	Linux Kernel Mailing List, Linux ARM, linux-clk, linux-arm-msm,
	Khasim Syed Mohammed

Perhaps I should look at the recipient list next time before posting :)

Kind regards,
Niklas

On Wed, 26 Jun 2019 at 11:08, Niklas Cassel <niklas.cassel@linaro.org> wrote:
>
> I actually think that it makes sense to squash this patch with the
> [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table
> patch.
>
> But that might be a personal preference.
>
> Either way, I think this series in ready for the real mailing list.
>
>
>
>
> On Tue, 25 Jun 2019 at 18:48, Jorge Ramirez-Ortiz
> <jorge.ramirez-ortiz@linaro.org> wrote:
> >
> > Support dynamic voltage and frequency scaling on qcs404.
> >
> > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > index 9569686dbc41..4b4ce0b5df76 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > @@ -34,6 +34,9 @@
> >                         enable-method = "psci";
> >                         cpu-idle-states = <&CPU_SLEEP_0>;
> >                         next-level-cache = <&L2_0>;
> > +                       clocks = <&apcs_glb>;
> > +                       operating-points-v2 = <&cpu_opp_table>;
> > +                       cpu-supply = <&pms405_s3>;
> >                 };
> >
> >                 CPU1: cpu@101 {
> > @@ -43,6 +46,9 @@
> >                         enable-method = "psci";
> >                         cpu-idle-states = <&CPU_SLEEP_0>;
> >                         next-level-cache = <&L2_0>;
> > +                       clocks = <&apcs_glb>;
> > +                       operating-points-v2 = <&cpu_opp_table>;
> > +                       cpu-supply = <&pms405_s3>;
> >                 };
> >
> >                 CPU2: cpu@102 {
> > @@ -52,6 +58,9 @@
> >                         enable-method = "psci";
> >                         cpu-idle-states = <&CPU_SLEEP_0>;
> >                         next-level-cache = <&L2_0>;
> > +                       clocks = <&apcs_glb>;
> > +                       operating-points-v2 = <&cpu_opp_table>;
> > +                       cpu-supply = <&pms405_s3>;
> >                 };
> >
> >                 CPU3: cpu@103 {
> > @@ -61,6 +70,9 @@
> >                         enable-method = "psci";
> >                         cpu-idle-states = <&CPU_SLEEP_0>;
> >                         next-level-cache = <&L2_0>;
> > +                       clocks = <&apcs_glb>;
> > +                       operating-points-v2 = <&cpu_opp_table>;
> > +                       cpu-supply = <&pms405_s3>;
> >                 };
> >
> >                 L2_0: l2-cache {
> > --
> > 2.21.0
> >

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 03/14] mbox: qcom: replace integer with valid macro
  2019-06-25 16:47 ` [PATCH v3 03/14] mbox: qcom: replace integer with valid macro Jorge Ramirez-Ortiz
@ 2019-07-11 14:37   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 14:37 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Use the correct macro when registering the platform device.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index a05dc3aabac7..c8088e9caf02 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -97,7 +97,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
>  
>  	apcs->clk = platform_device_register_data(&pdev->dev,
>  						  "qcom-apcs-msm8916-clk",
> -						  -1, NULL, 0);
> +						  PLATFORM_DEVID_NONE, NULL, 0);
>  	if (IS_ERR(apcs->clk))
>  		dev_err(&pdev->dev, "failed to register APCS clk\n");
>  
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404
  2019-06-25 16:47 ` [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404 Jorge Ramirez-Ortiz
@ 2019-07-11 14:44   ` Bjorn Andersson
  2019-07-31 14:10     ` Jorge Ramirez
  0 siblings, 1 reply; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 14:44 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> There is clock controller functionality in the APCS hardware block of
> qcs404 devices similar to msm8916.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
>  drivers/mailbox/qcom-apcs-ipc-mailbox.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 705e17a5479c..a05dc3aabac7 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -89,16 +89,18 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
> -		apcs->clk = platform_device_register_data(&pdev->dev,
> -							  "qcom-apcs-msm8916-clk",
> -							  -1, NULL, 0);
> -		if (IS_ERR(apcs->clk))
> -			dev_err(&pdev->dev, "failed to register APCS clk\n");
> -	}
> -
>  	platform_set_drvdata(pdev, apcs);
>  
> +	if (!of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global") &&
> +	    !of_device_is_compatible(np, "qcom,qcs404-apcs-apps-global"))

If the remainder of the function was a long snippet I think this would
motivate the somewhat unusual early return. But I think it would be
cleaner to just add to the existing conditional.

Regards,
Bjorn

> +		return 0;
> +
> +	apcs->clk = platform_device_register_data(&pdev->dev,
> +						  "qcom-apcs-msm8916-clk",
> +						  -1, NULL, 0);
> +	if (IS_ERR(apcs->clk))
> +		dev_err(&pdev->dev, "failed to register APCS clk\n");
> +
>  	return 0;
>  }
>  
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property
  2019-06-25 16:47 ` [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property Jorge Ramirez-Ortiz
@ 2019-07-11 14:45   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 14:45 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> When the APCS clock is registered (platform dependent), it retrieves
> its parent names from hardcoded values in the driver.
> 
> The following commit allows the DT node to provide such clock names to
> the platform data based clock driver therefore avoiding having to
> explicitly embed those names in the clock driver source code.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  .../mailbox/qcom,apcs-kpss-global.txt         | 24 ++++++++++++++++---
>  1 file changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> index 1232fc9fc709..b69310322b09 100644
> --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
> @@ -18,10 +18,11 @@ platforms.
>  	Usage: required
>  	Value type: <prop-encoded-array>
>  	Definition: must specify the base address and size of the global block
> +
>  - clocks:
> -	Usage: required if #clocks-cells property is present
> -	Value type: <phandle>
> -	Definition: phandle to the input PLL, which feeds the APCS mux/divider
> +	Usage: required if #clock-names property is present
> +	Value type: <phandle array>
> +	Definition: phandles to the two parent clocks of the clock driver.
>  
>  - #mbox-cells:
>  	Usage: required
> @@ -33,6 +34,12 @@ platforms.
>  	Value type: <u32>
>  	Definition: as described in clock.txt, must be 0
>  
> +- clock-names:
> +	Usage: required if the platform data based clock driver needs to
> +	retrieve the parent clock names from device tree.
> +	This will requires two mandatory clocks to be defined.
> +	Value type: <string-array>
> +	Definition: must be "aux" and "pll"
>  
>  = EXAMPLE
>  The following example describes the APCS HMSS found in MSM8996 and part of the
> @@ -65,3 +72,14 @@ Below is another example of the APCS binding on MSM8916 platforms:
>  		clocks = <&a53pll>;
>  		#clock-cells = <0>;
>  	};
> +
> +Below is another example of the APCS binding on QCS404 platforms:
> +
> +	apcs_glb: mailbox@b011000 {
> +		compatible = "qcom,qcs404-apcs-apps-global", "syscon";
> +		reg = <0x0b011000 0x1000>;
> +		#mbox-cells = <1>;
> +		clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
> +		clock-names = "aux", "pll";
> +		#clock-cells = <0>;
> +	};
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT
  2019-06-25 16:47 ` [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT Jorge Ramirez-Ortiz
@ 2019-07-11 14:58   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 14:58 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Allow accessing the parent clock names required for the driver
> operation by using the device tree node.
> 
> This permits extending the driver to other platforms without having to
> modify its source code.
> 
> For backwards compatibility leave previous values as default.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  drivers/clk/qcom/apcs-msm8916.c | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c
> index a6c89a310b18..dd82eb1e5202 100644
> --- a/drivers/clk/qcom/apcs-msm8916.c
> +++ b/drivers/clk/qcom/apcs-msm8916.c
> @@ -19,7 +19,7 @@
>  
>  static const u32 gpll0_a53cc_map[] = { 4, 5 };
>  
> -static const char * const gpll0_a53cc[] = {
> +static const char *gpll0_a53cc[] = {
>  	"gpll0_vote",
>  	"a53pll",
>  };
> @@ -50,6 +50,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>  	struct regmap *regmap;
>  	struct clk_init_data init = { };
>  	int ret = -ENODEV;
> +	const char *parents[2];
> +	int pll_index = 0;
>  
>  	regmap = dev_get_regmap(parent, NULL);
>  	if (!regmap) {
> @@ -61,6 +63,16 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>  	if (!a53cc)
>  		return -ENOMEM;
>  
> +	/* legacy bindings only defined the pll parent clock (index = 0) with no
> +	 * name; when both of the parents are specified in the bindings, the
> +	 * pll is the second one (index = 1).
> +	 */
> +	if (of_clk_parent_fill(parent->of_node, parents, 2) == 2) {
> +		gpll0_a53cc[0] = parents[0];
> +		gpll0_a53cc[1] = parents[1];
> +		pll_index = 1;
> +	}
> +
>  	init.name = "a53mux";
>  	init.parent_names = gpll0_a53cc;
>  	init.num_parents = ARRAY_SIZE(gpll0_a53cc);
> @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>  	a53cc->src_shift = 8;
>  	a53cc->parent_map = gpll0_a53cc_map;
>  
> -	a53cc->pclk = devm_clk_get(parent, NULL);
> +	a53cc->pclk = of_clk_get(parent->of_node, pll_index);
>  	if (IS_ERR(a53cc->pclk)) {
>  		ret = PTR_ERR(a53cc->pclk);
> -		dev_err(dev, "failed to get clk: %d\n", ret);
> +		if (ret != -EPROBE_DEFER)
> +			dev_err(dev, "failed to get clk: %d\n", ret);
>  		return ret;
>  	}
>  
> @@ -87,6 +100,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>  	ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb);
>  	if (ret) {
>  		dev_err(dev, "failed to register clock notifier: %d\n", ret);
> +		clk_put(a53cc->pclk);
>  		return ret;
>  	}
>  
> @@ -109,6 +123,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev)
>  
>  err:
>  	clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
> +	clk_put(a53cc->pclk);
> +
>  	return ret;
>  }
>  
> @@ -117,6 +133,7 @@ static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
>  	struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
>  
>  	clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
> +	clk_put(a53cc->pclk);
>  
>  	return 0;
>  }
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 06/14] clk: qcom: hfpll: get parent clock names from DT
  2019-06-25 16:47 ` [PATCH v3 06/14] clk: qcom: hfpll: " Jorge Ramirez-Ortiz
@ 2019-07-11 15:07   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:07 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Allow accessing the parent clock name required for the driver
> operation using the device tree node.
> 
> This permits extending the driver to other platforms without having to
> modify its source code.
> 
> For backwards compatibility leave the previous value as default.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

The driver should be updated to use parent_data instead, but I consider
that's an independent change.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  drivers/clk/qcom/hfpll.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index a6de7101430c..87b7f46d27e0 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -52,6 +52,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>  	void __iomem *base;
>  	struct regmap *regmap;
>  	struct clk_hfpll *h;
> +	struct clk *pclk;
>  	struct clk_init_data init = {
>  		.parent_names = (const char *[]){ "xo" },
>  		.num_parents = 1,
> @@ -75,6 +76,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>  					  0, &init.name))
>  		return -ENODEV;
>  
> +	/* get parent clock from device tree (optional) */
> +	pclk = devm_clk_get(dev, "xo");
> +	if (!IS_ERR(pclk))
> +		init.parent_names = (const char *[]){ __clk_get_name(pclk) };
> +	else if (PTR_ERR(pclk) == -EPROBE_DEFER)
> +		return -EPROBE_DEFER;
> +
>  	h->d = &hdata;
>  	h->clkr.hw.init = &init;
>  	spin_lock_init(&h->lock);
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider
  2019-06-25 16:47 ` [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider Jorge Ramirez-Ortiz
@ 2019-07-11 15:07   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:07 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Make the output of the high frequency pll a clock provider.
> On the QCS404 this PLL controls cpu frequency scaling.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Acked-by: Stephen Boyd <sboyd@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  drivers/clk/qcom/hfpll.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index 87b7f46d27e0..0ffed0d41c50 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -53,6 +53,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>  	struct regmap *regmap;
>  	struct clk_hfpll *h;
>  	struct clk *pclk;
> +	int ret;
>  	struct clk_init_data init = {
>  		.parent_names = (const char *[]){ "xo" },
>  		.num_parents = 1,
> @@ -87,7 +88,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>  	h->clkr.hw.init = &init;
>  	spin_lock_init(&h->lock);
>  
> -	return devm_clk_register_regmap(&pdev->dev, &h->clkr);
> +	ret = devm_clk_register_regmap(dev, &h->clkr);
> +	if (ret) {
> +		dev_err(dev, "failed to register regmap clock: %d\n", ret);
> +		return ret;
> +	}
> +
> +	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
> +					   &h->clkr.hw);
>  }
>  
>  static struct platform_driver qcom_hfpll_driver = {
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED
  2019-06-25 16:47 ` [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED Jorge Ramirez-Ortiz
@ 2019-07-11 15:16   ` Bjorn Andersson
  2019-07-31 14:30     ` Jorge Ramirez
  0 siblings, 1 reply; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:16 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
> to keep the software model of the clock in line with reality, the
> framework transverses the clock tree and disables those clocks that
> were enabled by the firmware but have not been enabled by any device
> driver.
> 
> If CPUFREQ is enabled, early during the system boot, it might attempt
> to change the CPU frequency ("set_rate"). If the HFPLL is selected as
> a provider, it will then change the rate for this clock.
> 
> As boot continues, clk_disable_unused_subtree will run. Since it wont
> find a valid counter (enable_count) for a clock that is actually
> enabled it will attempt to disable it which will cause the CPU to
> stop.

But if CPUfreq has acquired the CPU clock and the hfpll is the currently
selected input, why does the clock framework not know about this clock
being used?

> Notice that in this driver, calls to check whether the clock is
> enabled are routed via the is_enabled callback which queries the
> hardware.
> 
> The following commit, rather than marking the clock critical and
> forcing the clock to be always enabled, addresses the above scenario
> making sure the clock is not disabled but it continues to rely on the
> firmware to enable the clock.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>


I can see that we have a real issue in the case where CPUfreq is not
enabled and hence there are no clients, according to Linux. And that I
don't know another way to guard against.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/clk/qcom/hfpll.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
> index 0ffed0d41c50..d5fd27938e7b 100644
> --- a/drivers/clk/qcom/hfpll.c
> +++ b/drivers/clk/qcom/hfpll.c
> @@ -58,6 +58,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>  		.parent_names = (const char *[]){ "xo" },
>  		.num_parents = 1,
>  		.ops = &clk_ops_hfpll,
> +		/*
> +		 * rather than marking the clock critical and forcing the clock
> +		 * to be always enabled, we make sure that the clock is not
> +		 * disabled: the firmware remains responsible of enabling this
> +		 * clock (for more info check the commit log)
> +		 */
> +		.flags = CLK_IGNORE_UNUSED,
>  	};
>  
>  	h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
  2019-06-25 16:47 ` [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Jorge Ramirez-Ortiz
@ 2019-07-11 15:24   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:24 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
> 
> The driver still supports the previous bindings; however with this
> update it we allow the msm8916 to access the parent clock names
> required by the driver operation using the device tree node.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 5ea9fb8f2f87..96dc7a12aa94 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -429,7 +429,8 @@
>  			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
>  			reg = <0xb011000 0x1000>;
>  			#mbox-cells = <1>;
> -			clocks = <&a53pll>;
> +			clocks = <&gcc GPLL0_VOTE>, <&a53pll>;
> +			clock-names = "aux", "pll";
>  			#clock-cells = <0>;
>  		};
>  
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table
  2019-06-25 16:47 ` [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table Jorge Ramirez-Ortiz
@ 2019-07-11 15:25   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:25 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Add a CPU OPP table to qcs404
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 3f17e1b09c13..d876dae5b0a5 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -83,6 +83,24 @@
>  		};
>  	};
>  
> +	cpu_opp_table: cpu-opp-table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-1094400000 {
> +			opp-hz = /bits/ 64 <1094400000>;
> +			opp-microvolt = <1224000 1224000 1224000>;
> +		};
> +		opp-1248000000 {
> +			opp-hz = /bits/ 64 <1248000000>;
> +			opp-microvolt = <1288000 1288000 1288000>;
> +		};
> +		opp-1401600000 {
> +			opp-hz = /bits/ 64 <1401600000>;
> +			opp-microvolt = <1384000 1384000 1384000>;
> +		};
> +	};
> +
>  	firmware {
>  		scm: scm {
>  			compatible = "qcom,scm-qcs404", "qcom,scm";
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node
  2019-06-25 16:47 ` [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node Jorge Ramirez-Ortiz
@ 2019-07-11 15:25   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:25 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> The high frequency pll functionality is required to enable CPU
> frequency scaling operation.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index d876dae5b0a5..94471aa31979 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -852,6 +852,15 @@
>  			#mbox-cells = <1>;
>  		};
>  
> +		apcs_hfpll: clock-controller@b016000 {
> +			compatible = "qcom,hfpll";
> +			reg = <0x0b016000 0x30>;
> +			#clock-cells = <0>;
> +			clock-output-names = "apcs_hfpll";
> +			clocks = <&xo_board>;
> +			clock-names = "xo";
> +		};
> +
>  		timer@b120000 {
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider
  2019-06-25 16:47 ` [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Jorge Ramirez-Ortiz
@ 2019-07-11 15:27   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:27 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Specify the clocks that feed the APCS mux/divider instead of using
> default hardcoded values in the source code.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 94471aa31979..9569686dbc41 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -850,6 +850,9 @@
>  			compatible = "qcom,qcs404-apcs-apps-global", "syscon";
>  			reg = <0x0b011000 0x1000>;
>  			#mbox-cells = <1>;
> +			clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>;
> +			clock-names = "aux", "pll";
> +			#clock-cells = <0>;
>  		};
>  
>  		apcs_hfpll: clock-controller@b016000 {
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 14/14] arm64: defconfig: Enable HFPLL
  2019-06-25 16:47 ` [PATCH v3 14/14] arm64: defconfig: Enable HFPLL Jorge Ramirez-Ortiz
@ 2019-07-11 15:27   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:27 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> The high frequency pll is required on compatible Qualcomm SoCs to
> support the CPU frequency scaling feature.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index fbbc065415d4..7cc4ad24dfe5 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -671,6 +671,7 @@ CONFIG_MSM_MMCC_8996=y
>  CONFIG_MSM_GCC_8998=y
>  CONFIG_QCS_GCC_404=y
>  CONFIG_SDM_GCC_845=y
> +CONFIG_QCOM_HFPLL=y
>  CONFIG_HWSPINLOCK=y
>  CONFIG_HWSPINLOCK_QCOM=y
>  CONFIG_ARM_MHU=y
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support
  2019-06-25 16:47 ` [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support Jorge Ramirez-Ortiz
  2019-06-26  9:08   ` Niklas Cassel
@ 2019-07-11 15:29   ` Bjorn Andersson
  1 sibling, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:29 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Support dynamic voltage and frequency scaling on qcs404.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

I agree with Niklas on the possibility of squashing this with the opp
table. But unless you respin this

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 9569686dbc41..4b4ce0b5df76 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -34,6 +34,9 @@
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&pms405_s3>;
>  		};
>  
>  		CPU1: cpu@101 {
> @@ -43,6 +46,9 @@
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&pms405_s3>;
>  		};
>  
>  		CPU2: cpu@102 {
> @@ -52,6 +58,9 @@
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&pms405_s3>;
>  		};
>  
>  		CPU3: cpu@103 {
> @@ -61,6 +70,9 @@
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&pms405_s3>;
>  		};
>  
>  		L2_0: l2-cache {
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency
  2019-06-25 16:47 ` [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Jorge Ramirez-Ortiz
@ 2019-07-11 15:30   ` Bjorn Andersson
  0 siblings, 0 replies; 33+ messages in thread
From: Bjorn Andersson @ 2019-07-11 15:30 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:

> Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware
> specifications.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Acked-by: Stephen Boyd <sboyd@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> ---
>  drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++
>  drivers/clk/qcom/clk-alpha-pll.h | 1 +
>  drivers/clk/qcom/gcc-qcs404.c    | 2 +-
>  3 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 0ced4a5a9a17..ef51f302bdf0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
>  	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
>  }
>  
> +const struct clk_ops clk_alpha_pll_fixed_ops = {
> +	.enable = clk_alpha_pll_enable,
> +	.disable = clk_alpha_pll_disable,
> +	.is_enabled = clk_alpha_pll_is_enabled,
> +	.recalc_rate = clk_alpha_pll_recalc_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
> +
>  const struct clk_ops clk_alpha_pll_ops = {
>  	.enable = clk_alpha_pll_enable,
>  	.disable = clk_alpha_pll_disable,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 66755f0f84fc..6b4eb74706b4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -104,6 +104,7 @@ struct alpha_pll_config {
>  };
>  
>  extern const struct clk_ops clk_alpha_pll_ops;
> +extern const struct clk_ops clk_alpha_pll_fixed_ops;
>  extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
>  extern const struct clk_ops clk_alpha_pll_postdiv_ops;
>  extern const struct clk_ops clk_alpha_pll_huayra_ops;
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 29cf464dd2c8..18c6563889f3 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
>  			.parent_names = (const char *[]){ "cxo" },
>  			.num_parents = 1,
>  			.flags = CLK_IS_CRITICAL,
> -			.ops = &clk_alpha_pll_ops,
> +			.ops = &clk_alpha_pll_fixed_ops,
>  		},
>  	},
>  };
> -- 
> 2.21.0
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404
  2019-07-11 14:44   ` Bjorn Andersson
@ 2019-07-31 14:10     ` Jorge Ramirez
  0 siblings, 0 replies; 33+ messages in thread
From: Jorge Ramirez @ 2019-07-31 14:10 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On 7/11/19 16:44, Bjorn Andersson wrote:
> On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> 
>> There is clock controller functionality in the APCS hardware block of
>> qcs404 devices similar to msm8916.
>>
>> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
>> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
>> ---
>>  drivers/mailbox/qcom-apcs-ipc-mailbox.c | 18 ++++++++++--------
>>  1 file changed, 10 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> index 705e17a5479c..a05dc3aabac7 100644
>> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
>> @@ -89,16 +89,18 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
>>  		return ret;
>>  	}
>>  
>> -	if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {
>> -		apcs->clk = platform_device_register_data(&pdev->dev,
>> -							  "qcom-apcs-msm8916-clk",
>> -							  -1, NULL, 0);
>> -		if (IS_ERR(apcs->clk))
>> -			dev_err(&pdev->dev, "failed to register APCS clk\n");
>> -	}
>> -
>>  	platform_set_drvdata(pdev, apcs);
>>  
>> +	if (!of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global") &&
>> +	    !of_device_is_compatible(np, "qcom,qcs404-apcs-apps-global"))
> 
> If the remainder of the function was a long snippet I think this would
> motivate the somewhat unusual early return. But I think it would be
> cleaner to just add to the existing conditional.

sure can do that. I dont agree (I wouldnt have bothered otherwise :))
but will do

> 
> Regards,
> Bjorn
> 
>> +		return 0;
>> +
>> +	apcs->clk = platform_device_register_data(&pdev->dev,
>> +						  "qcom-apcs-msm8916-clk",
>> +						  -1, NULL, 0);
>> +	if (IS_ERR(apcs->clk))
>> +		dev_err(&pdev->dev, "failed to register APCS clk\n");
>> +
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.21.0
>>
> 


^ permalink raw reply	[flat|nested] 33+ messages in thread

* Re: [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED
  2019-07-11 15:16   ` Bjorn Andersson
@ 2019-07-31 14:30     ` Jorge Ramirez
  0 siblings, 0 replies; 33+ messages in thread
From: Jorge Ramirez @ 2019-07-31 14:30 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: sboyd, david.brown, jassisinghbrar, mark.rutland, mturquette,
	robh+dt, will.deacon, arnd, horms+renesas, heiko, sibis,
	enric.balletbo, jagan, olof, vkoul, niklas.cassel, georgi.djakov,
	amit.kucheria, devicetree, linux-kernel, linux-arm-kernel,
	linux-clk, linux-arm-msm, khasim.mohammed

On 7/11/19 17:16, Bjorn Andersson wrote:
> On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote:
> 
>> When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and
>> to keep the software model of the clock in line with reality, the
>> framework transverses the clock tree and disables those clocks that
>> were enabled by the firmware but have not been enabled by any device
>> driver.
>>
>> If CPUFREQ is enabled, early during the system boot, it might attempt
>> to change the CPU frequency ("set_rate"). If the HFPLL is selected as
>> a provider, it will then change the rate for this clock.
>>
>> As boot continues, clk_disable_unused_subtree will run. Since it wont
>> find a valid counter (enable_count) for a clock that is actually
>> enabled it will attempt to disable it which will cause the CPU to
>> stop.
> 
> But if CPUfreq has acquired the CPU clock and the hfpll is the currently
> selected input, why does the clock framework not know about this clock
> being used?

right, see the comment right below - maybe I should have been more
explicit at the time. sorry about it.

> 
>> Notice that in this driver, calls to check whether the clock is
>> enabled are routed via the is_enabled callback which queries the
>> hardware.

calls to check whether the clock is enabled dont use the usage counter
but a hardware read. IIRC the clock framework will check some counter to
know if the clock is being used.

>>
>> The following commit, rather than marking the clock critical and
>> forcing the clock to be always enabled, addresses the above scenario
>> making sure the clock is not disabled but it continues to rely on the
>> firmware to enable the clock.
>>
>> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
>> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> 
> 
> I can see that we have a real issue in the case where CPUfreq is not
> enabled and hence there are no clients, according to Linux. And that I
> don't know another way to guard against.

the issue is there when CPUfreq is enabled that is for sure (if we just
remove this commit the system will not boot due to the situation I tried
to describe above).

> 
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> Regards,
> Bjorn
> 
>> ---
>>  drivers/clk/qcom/hfpll.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
>> index 0ffed0d41c50..d5fd27938e7b 100644
>> --- a/drivers/clk/qcom/hfpll.c
>> +++ b/drivers/clk/qcom/hfpll.c
>> @@ -58,6 +58,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
>>  		.parent_names = (const char *[]){ "xo" },
>>  		.num_parents = 1,
>>  		.ops = &clk_ops_hfpll,
>> +		/*
>> +		 * rather than marking the clock critical and forcing the clock
>> +		 * to be always enabled, we make sure that the clock is not
>> +		 * disabled: the firmware remains responsible of enabling this
>> +		 * clock (for more info check the commit log)
>> +		 */
>> +		.flags = CLK_IGNORE_UNUSED,
>>  	};
>>  
>>  	h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
>> -- 
>> 2.21.0
>>
> 


^ permalink raw reply	[flat|nested] 33+ messages in thread

end of thread, back to index

Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-25 16:47 [PATCH v3 00/14] Support CPU frequency scaling on QCS404 Jorge Ramirez-Ortiz
2019-06-25 16:47 ` [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Jorge Ramirez-Ortiz
2019-07-11 15:30   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 02/14] mbox: qcom: add APCS child device for QCS404 Jorge Ramirez-Ortiz
2019-07-11 14:44   ` Bjorn Andersson
2019-07-31 14:10     ` Jorge Ramirez
2019-06-25 16:47 ` [PATCH v3 03/14] mbox: qcom: replace integer with valid macro Jorge Ramirez-Ortiz
2019-07-11 14:37   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 04/14] dt-bindings: mailbox: qcom: Add clock-name optional property Jorge Ramirez-Ortiz
2019-07-11 14:45   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT Jorge Ramirez-Ortiz
2019-07-11 14:58   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 06/14] clk: qcom: hfpll: " Jorge Ramirez-Ortiz
2019-07-11 15:07   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider Jorge Ramirez-Ortiz
2019-07-11 15:07   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 08/14] clk: qcom: hfpll: CLK_IGNORE_UNUSED Jorge Ramirez-Ortiz
2019-07-11 15:16   ` Bjorn Andersson
2019-07-31 14:30     ` Jorge Ramirez
2019-06-25 16:47 ` [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Jorge Ramirez-Ortiz
2019-07-11 15:24   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table Jorge Ramirez-Ortiz
2019-07-11 15:25   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node Jorge Ramirez-Ortiz
2019-07-11 15:25   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 12/14] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Jorge Ramirez-Ortiz
2019-07-11 15:27   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 13/14] arm64: dts: qcom: qcs404: Add DVFS support Jorge Ramirez-Ortiz
2019-06-26  9:08   ` Niklas Cassel
2019-06-26  9:10     ` Niklas Cassel
2019-07-11 15:29   ` Bjorn Andersson
2019-06-25 16:47 ` [PATCH v3 14/14] arm64: defconfig: Enable HFPLL Jorge Ramirez-Ortiz
2019-07-11 15:27   ` Bjorn Andersson

Linux-ARM-MSM Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
		linux-arm-msm@vger.kernel.org
	public-inbox-index linux-arm-msm

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git