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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id z4sm132422580pfg.166.2019.08.05.17.43.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Aug 2019 17:43:44 -0700 (PDT) Date: Mon, 5 Aug 2019 17:43:42 -0700 From: Bjorn Andersson To: Marc Gonzalez Cc: Kishon Vijay Abraham I , MSM , LKML , Evan Green , Vivek Gautam , Niklas Cassel , Stanimir Varbanov Subject: Re: [PATCH] phy: qcom-qmp: Correct READY_STATUS poll break condition Message-ID: <20190806004342.GD6470@builder> References: <20190604232443.3417-1-bjorn.andersson@linaro.org> <619d2559-6d88-e795-76e0-3078236933ef@free.fr> <20190612172501.GY4814@minitux> <3570d880-2b76-88ae-8721-e75cf5acec4c@free.fr> <5b252fe6-9435-2aad-d0db-f6170a07b5e9@free.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5b252fe6-9435-2aad-d0db-f6170a07b5e9@free.fr> User-Agent: Mutt/1.10.0 (2018-05-17) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 19 Jul 08:50 PDT 2019, Marc Gonzalez wrote: > On 13/06/2019 11:10, Marc Gonzalez wrote: > > > Here are my observations for a 8998 board: > > > > 1) If I apply only the readl_poll_timeout() fix (not the mask_pcs_ready fixup) > > qcom_pcie_probe() fails with a timeout in phy_init. > > => this is in line with your regression analysis. > > > > 2) Your patch also fixes a long-standing bug in UFS init whereby sending > > lots of information to the console during phy init would lead to an > > incorrectly diagnosed time-out. > > > > Good stuff! > > > > Reviewed-by: Marc Gonzalez > > Tested-by: Marc Gonzalez > > It looks like this patch fixed UFS, but broke PCIe and USB3 ^_^ > > qcom-qmp-phy 1c06000.phy: Registered Qcom-QMP phy > qcom-qmp-phy c010000.phy: Registered Qcom-QMP phy > qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy > > qcom-qmp-phy 1c06000.phy: BEFORE=000000a6 AFTER=000000a6 > qcom-qmp-phy 1c06000.phy: phy initialization timed-out > phy phy-1c06000.phy.0: phy init failed --> -110 > qcom-pcie: probe of 1c00000.pci failed with error -110 > > qcom-qmp-phy 1da7000.phy: BEFORE=00000040 AFTER=0000000d > > qcom-qmp-phy c010000.phy: BEFORE=69696969 AFTER=b7b7b7b7 > qcom-qmp-phy c010000.phy: phy initialization timed-out > phy phy-c010000.phy.1: phy init failed --> -110 > dwc3 a800000.dwc3: failed to initialize core: -110 > dwc3: probe of a800000.dwc3 failed with error -110 > > > Downstream code for PCIe is: > > static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) > { > if (dev->phy_ver >= 0x20) { > if (readl_relaxed(dev->phy + PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) & BIT(6)) > return false; > else > return true; > } > > if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1)) > return false; > else > return true; > } > > AFAICT: > PCIe and USB3 QMP PHYs are ready when PHYSTATUS=BIT(6) goes to 0. > But UFS is ready when PCS_READY=BIT(0) goes to 1. > > > Can someone verify that USB3 is broken on 845 with 885bd765963b? > Both USB3 and PCIe still works for me on 845, but you are correct; PHYSTATUS is ready low, while PCS_READY is ready high. I posted a patch that attempts to clean up the differences, please give it a spin (and review). Regards, Bjorn