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* [PATCH v2 00/14] Add support for QCOM Core Power Reduction
@ 2019-07-25 10:41 Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Niklas Cassel
                   ` (14 more replies)
  0 siblings, 15 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: linux-pm, linux-arm-msm
  Cc: jorge.ramirez-ortiz, sboyd, vireshk, bjorn.andersson,
	ulf.hansson, Niklas Cassel, devicetree, linux-kernel,
	linux-arm-kernel

This series adds support for Core Power Reduction (CPR), a form of
Adaptive Voltage Scaling (AVS), found on certain Qualcomm SoCs.

This series is based on top of the qcs404 cpufreq patch series that
hasn't landed yet:
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=137809

CPR is a technology that reduces core power on a CPU or on other device.
It reads voltage settings from efuses (that have been written in
production), it uses these voltage settings as initial values, for each
OPP.

After moving to a certain OPP, CPR monitors dynamic factors such as
temperature, etc. and adjusts the voltage for that frequency accordingly
to save power and meet silicon characteristic requirements.

This driver has been developed together with Jorge Ramirez-Ortiz, and
is based on an RFC by Stephen Boyd[1], which in turn is based on work
by others on codeaurora.org[2].

[1] https://lkml.org/lkml/2015/9/18/833
[2] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/cpr-regulator.c?h=msm-3.10

Changes since V1:
Added a new patch implementing dev_pm_opp_find_level_exact() in order to
make the CPR OPP table in device tree cleaner.
For more detailed changes, check the "Changes since V1" as comments in
the individual patches, where applicable.

Jorge Ramirez-Ortiz (1):
  cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist

Niklas Cassel (11):
  opp: Add dev_pm_opp_find_level_exact()
  dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties
    optional
  cpufreq: qcom: Refactor the driver to make it easier to extend
  dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power
    domain
  cpufreq: qcom: Add support for qcs404 on nvmem driver
  dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  dt-bindings: power: avs: Add support for CPR (Core Power Reduction)
  power: avs: Add support for CPR (Core Power Reduction)
  arm64: dts: qcom: qcs404: Add CPR and populate OPP table
  arm64: defconfig: enable CONFIG_QCOM_CPR
  arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM

Sricharan R (2):
  dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other
    nvmem based qcom socs
  cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem
    based qcom socs

 ...ryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} |  125 +-
 .../devicetree/bindings/opp/qcom-opp.txt      |   19 +
 .../bindings/power/avs/qcom,cpr.txt           |  193 ++
 MAINTAINERS                                   |   13 +-
 arch/arm64/boot/dts/qcom/qcs404.dtsi          |  142 +-
 arch/arm64/configs/defconfig                  |    2 +
 drivers/cpufreq/Kconfig.arm                   |    4 +-
 drivers/cpufreq/Makefile                      |    2 +-
 drivers/cpufreq/cpufreq-dt-platdev.c          |    1 +
 drivers/cpufreq/qcom-cpufreq-kryo.c           |  249 ---
 drivers/cpufreq/qcom-cpufreq-nvmem.c          |  352 +++
 drivers/opp/core.c                            |   48 +
 drivers/power/avs/Kconfig                     |   15 +
 drivers/power/avs/Makefile                    |    1 +
 drivers/power/avs/qcom-cpr.c                  | 1885 +++++++++++++++++
 include/linux/pm_opp.h                        |    8 +
 16 files changed, 2792 insertions(+), 267 deletions(-)
 rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (87%)
 create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt
 create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
 delete mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
 create mode 100644 drivers/cpufreq/qcom-cpufreq-nvmem.c
 create mode 100644 drivers/power/avs/qcom-cpr.c

-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact()
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-26  8:03   ` Viresh Kumar
  2019-07-25 10:41 ` [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Niklas Cassel
                   ` (13 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Viresh Kumar, Nishanth Menon, Stephen Boyd, Rafael J. Wysocki
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, linux-pm, linux-kernel

When using performance states, there is usually not any opp-hz property
specified, so the dev_pm_opp_find_freq_exact() function cannot be used.
Since the performance states in the OPP table are unique, implement a
dev_pm_opp_find_level_exact() in order to be able to fetch a specific OPP.

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 drivers/opp/core.c     | 48 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/pm_opp.h |  8 +++++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index cac3e4005045..3b7ffd0234e9 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -401,6 +401,54 @@ struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
 }
 EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_exact);
 
+/**
+ * dev_pm_opp_find_level_exact() - search for an exact level
+ * @dev:		device for which we do this operation
+ * @level:		level to search for
+ *
+ * Return: Searches for exact match in the opp table and returns pointer to the
+ * matching opp if found, else returns ERR_PTR in case of error and should
+ * be handled using IS_ERR. Error return values can be:
+ * EINVAL:	for bad pointer
+ * ERANGE:	no match found for search
+ * ENODEV:	if device not found in list of registered devices
+ *
+ * The callers are required to call dev_pm_opp_put() for the returned OPP after
+ * use.
+ */
+struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev,
+					       unsigned int level)
+{
+	struct opp_table *opp_table;
+	struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE);
+
+	opp_table = _find_opp_table(dev);
+	if (IS_ERR(opp_table)) {
+		int r = PTR_ERR(opp_table);
+
+		dev_err(dev, "%s: OPP table not found (%d)\n", __func__, r);
+		return ERR_PTR(r);
+	}
+
+	mutex_lock(&opp_table->lock);
+
+	list_for_each_entry(temp_opp, &opp_table->opp_list, node) {
+		if (temp_opp->level == level) {
+			opp = temp_opp;
+
+			/* Increment the reference count of OPP */
+			dev_pm_opp_get(opp);
+			break;
+		}
+	}
+
+	mutex_unlock(&opp_table->lock);
+	dev_pm_opp_put_opp_table(opp_table);
+
+	return opp;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_exact);
+
 static noinline struct dev_pm_opp *_find_freq_ceil(struct opp_table *opp_table,
 						   unsigned long *freq)
 {
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index 5bdceca5125d..b8197ab014f2 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -96,6 +96,8 @@ unsigned long dev_pm_opp_get_suspend_opp_freq(struct device *dev);
 struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
 					      unsigned long freq,
 					      bool available);
+struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev,
+					       unsigned int level);
 
 struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev,
 					      unsigned long *freq);
@@ -200,6 +202,12 @@ static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev,
 	return ERR_PTR(-ENOTSUPP);
 }
 
+static inline struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev,
+					unsigned int level)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
 static inline struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev,
 					unsigned long *freq)
 {
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-26  8:04   ` Viresh Kumar
  2019-07-25 10:41 ` [PATCH v2 03/14] cpufreq: qcom: " Niklas Cassel
                   ` (12 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Viresh Kumar, Nishanth Menon, Stephen Boyd, Andy Gross, Ilia Lin
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Sricharan R, Niklas Cassel, Rob Herring, Rob Herring,
	Mark Rutland, linux-pm, devicetree, linux-kernel

From: Sricharan R <sricharan@codeaurora.org>

The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[niklas.cassel@linaro.org: split dt-binding into a separate patch and
do not rename the compatible string.]
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since V1:
-Picked up tags.

 .../opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt}   | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/opp/{kryo-cpufreq.txt => qcom-nvmem-cpufreq.txt} (98%)

diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
similarity index 98%
rename from Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
rename to Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c2127b96805a..198441e80ba8 100644
--- a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -1,13 +1,13 @@
-Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
+Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
 ===================================
 
-In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
-that have KRYO processors, the CPU ferequencies subset and voltage value
-of each OPP varies based on the silicon variant in use.
+In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
+the CPU frequencies subset and voltage value of each OPP varies based on
+the silicon variant in use.
 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
 defines the voltage and frequency value based on the msm-id in SMEM
 and speedbin blown in the efuse combination.
-The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
 to provide the OPP framework with required information (existing HW bitmap).
 This is used to determine the voltage and frequency value for each OPP of
 operating-points-v2 table when it is parsed by the OPP framework.
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 03/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Niklas Cassel
@ 2019-07-25 10:41 ` " Niklas Cassel
  2019-08-18  1:06   ` Stephen Boyd
  2019-07-25 10:41 ` [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Niklas Cassel
                   ` (11 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Rafael J. Wysocki, Viresh Kumar, Andy Gross, Ilia Lin
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Sricharan R, Niklas Cassel,
	linux-kernel, linux-pm

From: Sricharan R <sricharan@codeaurora.org>

The kryo cpufreq driver reads the nvmem cell and uses that data to
populate the opps. There are other qcom cpufreq socs like krait which
does similar thing. Except for the interpretation of the read data,
rest of the driver is same for both the cases. So pull the common things
out for reuse.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[niklas.cassel@linaro.org: split dt-binding into a separate patch and
do not rename the compatible string. Update MAINTAINERS file.]
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
---
Changes since V1:
-Picked up tags.
-Renamed .driver .name to "qcom-cpufreq-nvmem".

 MAINTAINERS                                   |   4 +-
 drivers/cpufreq/Kconfig.arm                   |   4 +-
 drivers/cpufreq/Makefile                      |   2 +-
 ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 122 +++++++++++-------
 4 files changed, 78 insertions(+), 54 deletions(-)
 rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%)

diff --git a/MAINTAINERS b/MAINTAINERS
index 711b5d07f73d..d6b42e2413e4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13320,8 +13320,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
 M:	Ilia Lin <ilia.lin@kernel.org>
 L:	linux-pm@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
-F:	drivers/cpufreq/qcom-cpufreq-kryo.c
+F:	Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+F:	drivers/cpufreq/qcom-cpufreq-nvmem.c
 
 QUALCOMM EMAC GIGABIT ETHERNET DRIVER
 M:	Timur Tabi <timur@kernel.org>
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 70c2b4bea55c..a905796f7f85 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -132,8 +132,8 @@ config ARM_OMAP2PLUS_CPUFREQ
 	depends on ARCH_OMAP2PLUS
 	default ARCH_OMAP2PLUS
 
-config ARM_QCOM_CPUFREQ_KRYO
-	tristate "Qualcomm Kryo based CPUFreq"
+config ARM_QCOM_CPUFREQ_NVMEM
+	tristate "Qualcomm nvmem based CPUFreq"
 	depends on ARM64
 	depends on QCOM_QFPROM
 	depends on QCOM_SMEM
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 7f2d2e1079d4..9a9f5ccd13d9 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -64,7 +64,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o
 obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o
 obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq.o
 obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)	+= qcom-cpufreq-hw.o
-obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO)	+= qcom-cpufreq-kryo.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)	+= qcom-cpufreq-nvmem.o
 obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) 	+= raspberrypi-cpufreq.o
 obj-$(CONFIG_ARM_S3C2410_CPUFREQ)	+= s3c2410-cpufreq.o
 obj-$(CONFIG_ARM_S3C2412_CPUFREQ)	+= s3c2412-cpufreq.o
diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
similarity index 69%
rename from drivers/cpufreq/qcom-cpufreq-kryo.c
rename to drivers/cpufreq/qcom-cpufreq-nvmem.c
index dd64dcf89c74..fd08120768af 100644
--- a/drivers/cpufreq/qcom-cpufreq-kryo.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -9,7 +9,7 @@
  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  * defines the voltage and frequency value based on the msm-id in SMEM
  * and speedbin blown in the efuse combination.
- * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
+ * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  * to provide the OPP framework with required information.
  * This is used to determine the voltage and frequency value for each OPP of
  * operating-points-v2 table when it is parsed by the OPP framework.
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_opp.h>
 #include <linux/slab.h>
@@ -42,9 +43,9 @@ enum _msm8996_version {
 	NUM_OF_MSM8996_VERSIONS,
 };
 
-static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev;
+static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
-static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void)
+static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
 {
 	size_t len;
 	u32 *msm_id;
@@ -73,28 +74,62 @@ static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void)
 	return version;
 }
 
-static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
+static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
+					  struct nvmem_cell *speedbin_nvmem,
+					  u32 *versions)
 {
-	struct opp_table **opp_tables;
+	size_t len;
+	u8 *speedbin;
 	enum _msm8996_version msm8996_version;
+
+	msm8996_version = qcom_cpufreq_get_msm_id();
+	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
+		dev_err(cpu_dev, "Not Snapdragon 820/821!");
+		return -ENODEV;
+	}
+
+	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	if (IS_ERR(speedbin))
+		return PTR_ERR(speedbin);
+
+	switch (msm8996_version) {
+	case MSM8996_V3:
+		*versions = 1 << (unsigned int)(*speedbin);
+		break;
+	case MSM8996_SG:
+		*versions = 1 << ((unsigned int)(*speedbin) + 4);
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	kfree(speedbin);
+	return 0;
+}
+
+static int qcom_cpufreq_probe(struct platform_device *pdev)
+{
+	struct opp_table **opp_tables;
+	int (*get_version)(struct device *cpu_dev,
+			   struct nvmem_cell *speedbin_nvmem,
+			   u32 *versions);
 	struct nvmem_cell *speedbin_nvmem;
 	struct device_node *np;
 	struct device *cpu_dev;
 	unsigned cpu;
-	u8 *speedbin;
 	u32 versions;
-	size_t len;
+	const struct of_device_id *match;
 	int ret;
 
 	cpu_dev = get_cpu_device(0);
 	if (!cpu_dev)
 		return -ENODEV;
 
-	msm8996_version = qcom_cpufreq_kryo_get_msm_id();
-	if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
-		dev_err(cpu_dev, "Not Snapdragon 820/821!");
+	match = pdev->dev.platform_data;
+	get_version = match->data;
+	if (!get_version)
 		return -ENODEV;
-	}
 
 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 	if (!np)
@@ -115,23 +150,10 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
 		return PTR_ERR(speedbin_nvmem);
 	}
 
-	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	ret = get_version(cpu_dev, speedbin_nvmem, &versions);
 	nvmem_cell_put(speedbin_nvmem);
-	if (IS_ERR(speedbin))
-		return PTR_ERR(speedbin);
-
-	switch (msm8996_version) {
-	case MSM8996_V3:
-		versions = 1 << (unsigned int)(*speedbin);
-		break;
-	case MSM8996_SG:
-		versions = 1 << ((unsigned int)(*speedbin) + 4);
-		break;
-	default:
-		BUG();
-		break;
-	}
-	kfree(speedbin);
+	if (ret)
+		return ret;
 
 	opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL);
 	if (!opp_tables)
@@ -174,7 +196,7 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static int qcom_cpufreq_kryo_remove(struct platform_device *pdev)
+static int qcom_cpufreq_remove(struct platform_device *pdev)
 {
 	struct opp_table **opp_tables = platform_get_drvdata(pdev);
 	unsigned int cpu;
@@ -189,18 +211,20 @@ static int qcom_cpufreq_kryo_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver qcom_cpufreq_kryo_driver = {
-	.probe = qcom_cpufreq_kryo_probe,
-	.remove = qcom_cpufreq_kryo_remove,
+static struct platform_driver qcom_cpufreq_driver = {
+	.probe = qcom_cpufreq_probe,
+	.remove = qcom_cpufreq_remove,
 	.driver = {
-		.name = "qcom-cpufreq-kryo",
+		.name = "qcom-cpufreq-nvmem",
 	},
 };
 
-static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = {
-	{ .compatible = "qcom,apq8096", },
-	{ .compatible = "qcom,msm8996", },
-	{}
+static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
+	{ .compatible = "qcom,apq8096",
+	  .data = qcom_cpufreq_kryo_name_version },
+	{ .compatible = "qcom,msm8996",
+	  .data = qcom_cpufreq_kryo_name_version },
+	{},
 };
 
 /*
@@ -209,7 +233,7 @@ static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = {
  * which may be defered as well. The init here is only registering
  * the driver and the platform device.
  */
-static int __init qcom_cpufreq_kryo_init(void)
+static int __init qcom_cpufreq_init(void)
 {
 	struct device_node *np = of_find_node_by_path("/");
 	const struct of_device_id *match;
@@ -218,32 +242,32 @@ static int __init qcom_cpufreq_kryo_init(void)
 	if (!np)
 		return -ENODEV;
 
-	match = of_match_node(qcom_cpufreq_kryo_match_list, np);
+	match = of_match_node(qcom_cpufreq_match_list, np);
 	of_node_put(np);
 	if (!match)
 		return -ENODEV;
 
-	ret = platform_driver_register(&qcom_cpufreq_kryo_driver);
+	ret = platform_driver_register(&qcom_cpufreq_driver);
 	if (unlikely(ret < 0))
 		return ret;
 
-	kryo_cpufreq_pdev = platform_device_register_simple(
-		"qcom-cpufreq-kryo", -1, NULL, 0);
-	ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev);
+	cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
+						     -1, match, sizeof(*match));
+	ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
 	if (0 == ret)
 		return 0;
 
-	platform_driver_unregister(&qcom_cpufreq_kryo_driver);
+	platform_driver_unregister(&qcom_cpufreq_driver);
 	return ret;
 }
-module_init(qcom_cpufreq_kryo_init);
+module_init(qcom_cpufreq_init);
 
-static void __exit qcom_cpufreq_kryo_exit(void)
+static void __exit qcom_cpufreq_exit(void)
 {
-	platform_device_unregister(kryo_cpufreq_pdev);
-	platform_driver_unregister(&qcom_cpufreq_kryo_driver);
+	platform_device_unregister(cpufreq_pdev);
+	platform_driver_unregister(&qcom_cpufreq_driver);
 }
-module_exit(qcom_cpufreq_kryo_exit);
+module_exit(qcom_cpufreq_exit);
 
-MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
 MODULE_LICENSE("GPL v2");
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (2 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 03/14] cpufreq: qcom: " Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 05/14] cpufreq: qcom: Refactor the driver to make it easier to extend Niklas Cassel
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

Not all Qualcomm platforms need to care about the speedbin efuse,
nor the value blown into the speedbin efuse.
Therefore, make the nvmem-cells and opp-supported-hw properties
optional.

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since V1:
-Picked up tags.

 Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index 198441e80ba8..c5ea8b90e35d 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -20,6 +20,10 @@ In 'cpus' nodes:
 In 'operating-points-v2' table:
 - compatible: Should be
 	- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
+
+Optional properties:
+--------------------
+In 'operating-points-v2' table:
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
 		speedbin that is used to select the right frequency/voltage
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 05/14] cpufreq: qcom: Refactor the driver to make it easier to extend
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (3 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Niklas Cassel
                   ` (9 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Rafael J. Wysocki, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, linux-pm,
	linux-kernel

Refactor the driver to make it easier to extend in a later commit.

Create a driver struct to collect all common resources, in order to make
it easier to free up all common resources.
Create a driver match_data struct to make it easier to extend the driver
with support for new features that might only be supported on certain SoCs.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
---
Changes since V1:
-Picked up tags.
-Fixed an incorrectly placed of_node_put().

 drivers/cpufreq/qcom-cpufreq-nvmem.c | 123 +++++++++++++++++----------
 1 file changed, 79 insertions(+), 44 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index fd08120768af..2d798a1685c5 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -43,6 +43,20 @@ enum _msm8996_version {
 	NUM_OF_MSM8996_VERSIONS,
 };
 
+struct qcom_cpufreq_drv;
+
+struct qcom_cpufreq_match_data {
+	int (*get_version)(struct device *cpu_dev,
+			   struct nvmem_cell *speedbin_nvmem,
+			   struct qcom_cpufreq_drv *drv);
+};
+
+struct qcom_cpufreq_drv {
+	struct opp_table **opp_tables;
+	u32 versions;
+	const struct qcom_cpufreq_match_data *data;
+};
+
 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
 static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
@@ -76,7 +90,7 @@ static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
 
 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 					  struct nvmem_cell *speedbin_nvmem,
-					  u32 *versions)
+					  struct qcom_cpufreq_drv *drv)
 {
 	size_t len;
 	u8 *speedbin;
@@ -94,10 +108,10 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 
 	switch (msm8996_version) {
 	case MSM8996_V3:
-		*versions = 1 << (unsigned int)(*speedbin);
+		drv->versions = 1 << (unsigned int)(*speedbin);
 		break;
 	case MSM8996_SG:
-		*versions = 1 << ((unsigned int)(*speedbin) + 4);
+		drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
 		break;
 	default:
 		BUG();
@@ -108,17 +122,17 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 	return 0;
 }
 
+static const struct qcom_cpufreq_match_data match_data_kryo = {
+	.get_version = qcom_cpufreq_kryo_name_version,
+};
+
 static int qcom_cpufreq_probe(struct platform_device *pdev)
 {
-	struct opp_table **opp_tables;
-	int (*get_version)(struct device *cpu_dev,
-			   struct nvmem_cell *speedbin_nvmem,
-			   u32 *versions);
+	struct qcom_cpufreq_drv *drv;
 	struct nvmem_cell *speedbin_nvmem;
 	struct device_node *np;
 	struct device *cpu_dev;
 	unsigned cpu;
-	u32 versions;
 	const struct of_device_id *match;
 	int ret;
 
@@ -126,11 +140,6 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	if (!cpu_dev)
 		return -ENODEV;
 
-	match = pdev->dev.platform_data;
-	get_version = match->data;
-	if (!get_version)
-		return -ENODEV;
-
 	np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 	if (!np)
 		return -ENOENT;
@@ -141,23 +150,43 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 		return -ENOENT;
 	}
 
-	speedbin_nvmem = of_nvmem_cell_get(np, NULL);
-	of_node_put(np);
-	if (IS_ERR(speedbin_nvmem)) {
-		if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
-			dev_err(cpu_dev, "Could not get nvmem cell: %ld\n",
-				PTR_ERR(speedbin_nvmem));
-		return PTR_ERR(speedbin_nvmem);
+	drv = kzalloc(sizeof(*drv), GFP_KERNEL);
+	if (!drv)
+		return -ENOMEM;
+
+	match = pdev->dev.platform_data;
+	drv->data = match->data;
+	if (!drv->data) {
+		ret = -ENODEV;
+		goto free_drv;
 	}
 
-	ret = get_version(cpu_dev, speedbin_nvmem, &versions);
-	nvmem_cell_put(speedbin_nvmem);
-	if (ret)
-		return ret;
+	if (drv->data->get_version) {
+		speedbin_nvmem = of_nvmem_cell_get(np, NULL);
+		if (IS_ERR(speedbin_nvmem)) {
+			if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
+				dev_err(cpu_dev,
+					"Could not get nvmem cell: %ld\n",
+					PTR_ERR(speedbin_nvmem));
+			ret = PTR_ERR(speedbin_nvmem);
+			goto free_drv;
+		}
 
-	opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL);
-	if (!opp_tables)
-		return -ENOMEM;
+		ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
+		if (ret) {
+			nvmem_cell_put(speedbin_nvmem);
+			goto free_drv;
+		}
+		nvmem_cell_put(speedbin_nvmem);
+	}
+	of_node_put(np);
+
+	drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
+				  GFP_KERNEL);
+	if (!drv->opp_tables) {
+		ret = -ENOMEM;
+		goto free_drv;
+	}
 
 	for_each_possible_cpu(cpu) {
 		cpu_dev = get_cpu_device(cpu);
@@ -166,19 +195,23 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 			goto free_opp;
 		}
 
-		opp_tables[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
-							      &versions, 1);
-		if (IS_ERR(opp_tables[cpu])) {
-			ret = PTR_ERR(opp_tables[cpu]);
-			dev_err(cpu_dev, "Failed to set supported hardware\n");
-			goto free_opp;
+		if (drv->data->get_version) {
+			drv->opp_tables[cpu] =
+				dev_pm_opp_set_supported_hw(cpu_dev,
+							    &drv->versions, 1);
+			if (IS_ERR(drv->opp_tables[cpu])) {
+				ret = PTR_ERR(drv->opp_tables[cpu]);
+				dev_err(cpu_dev,
+					"Failed to set supported hardware\n");
+				goto free_opp;
+			}
 		}
 	}
 
 	cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
 							  NULL, 0);
 	if (!IS_ERR(cpufreq_dt_pdev)) {
-		platform_set_drvdata(pdev, opp_tables);
+		platform_set_drvdata(pdev, drv);
 		return 0;
 	}
 
@@ -187,26 +220,30 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 
 free_opp:
 	for_each_possible_cpu(cpu) {
-		if (IS_ERR_OR_NULL(opp_tables[cpu]))
+		if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
 			break;
-		dev_pm_opp_put_supported_hw(opp_tables[cpu]);
+		dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
 	}
-	kfree(opp_tables);
+	kfree(drv->opp_tables);
+free_drv:
+	kfree(drv);
 
 	return ret;
 }
 
 static int qcom_cpufreq_remove(struct platform_device *pdev)
 {
-	struct opp_table **opp_tables = platform_get_drvdata(pdev);
+	struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
 	unsigned int cpu;
 
 	platform_device_unregister(cpufreq_dt_pdev);
 
 	for_each_possible_cpu(cpu)
-		dev_pm_opp_put_supported_hw(opp_tables[cpu]);
+		if (drv->opp_tables[cpu])
+			dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
 
-	kfree(opp_tables);
+	kfree(drv->opp_tables);
+	kfree(drv);
 
 	return 0;
 }
@@ -220,10 +257,8 @@ static struct platform_driver qcom_cpufreq_driver = {
 };
 
 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
-	{ .compatible = "qcom,apq8096",
-	  .data = qcom_cpufreq_kryo_name_version },
-	{ .compatible = "qcom,msm8996",
-	  .data = qcom_cpufreq_kryo_name_version },
+	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
+	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
 	{},
 };
 
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (4 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 05/14] cpufreq: qcom: Refactor the driver to make it easier to extend Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-08-16 21:21   ` Rob Herring
  2019-08-19 10:09   ` [PATCH v3 " Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 07/14] cpufreq: qcom: Add support for qcs404 on nvmem driver Niklas Cassel
                   ` (8 subsequent siblings)
  14 siblings, 2 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 .../bindings/opp/qcom-nvmem-cpufreq.txt       | 111 ++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c5ea8b90e35d..e19a95318e98 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -23,6 +23,15 @@ In 'operating-points-v2' table:
 
 Optional properties:
 --------------------
+In 'cpus' nodes:
+- power-domains: A phandle pointing to the PM domain specifier which provides
+		the performance states available for active state management.
+		Please refer to the power-domains bindings
+		Documentation/devicetree/bindings/power/power_domain.txt
+		and also examples below.
+- power-domain-names: Should be
+	- 'cpr' for qcs404.
+
 In 'operating-points-v2' table:
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
@@ -682,3 +691,105 @@ soc {
 		};
 	};
 };
+
+Example 2:
+---------
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+	};
+
+	cpu_opp_table: cpu-opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		opp-1094400000 {
+			opp-hz = /bits/ 64 <1094400000>;
+			required-opps = <&cpr_opp1>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			required-opps = <&cpr_opp2>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			required-opps = <&cpr_opp3>;
+		};
+	};
+
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			....
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			....
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			....
+		};
+	};
+
+....
+
+soc {
+....
+	cprpd: cpr@b018000 {
+		compatible = "qcom,qcs404-cpr", "qcom,cpr";
+		reg = <0x0b018000 0x1000>;
+		....
+		vdd-apc-supply = <&pms405_s3>;
+		#power-domain-cells = <0>;
+		operating-points-v2 = <&cpr_opp_table>;
+		....
+	};
+};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 07/14] cpufreq: qcom: Add support for qcs404 on nvmem driver
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (5 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 08/14] cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Niklas Cassel
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Rafael J. Wysocki, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, linux-pm,
	linux-kernel

Add support for qcs404 on nvmem driver.

The qcs404 SoC has support for Core Power Reduction (CPR), which is
implemented as a power domain provider, therefore add optional support
in this driver to attach to a genpd power domain.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
Changes since V1:
-Adapt to dev_pm_opp_attach_genpd() API change.

 drivers/cpufreq/qcom-cpufreq-nvmem.c | 50 ++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 2d798a1685c5..f0d2d5035413 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -24,6 +24,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/pm_domain.h>
 #include <linux/pm_opp.h>
 #include <linux/slab.h>
 #include <linux/soc/qcom/smem.h>
@@ -49,10 +50,12 @@ struct qcom_cpufreq_match_data {
 	int (*get_version)(struct device *cpu_dev,
 			   struct nvmem_cell *speedbin_nvmem,
 			   struct qcom_cpufreq_drv *drv);
+	const char **genpd_names;
 };
 
 struct qcom_cpufreq_drv {
 	struct opp_table **opp_tables;
+	struct opp_table **genpd_opp_tables;
 	u32 versions;
 	const struct qcom_cpufreq_match_data *data;
 };
@@ -126,6 +129,12 @@ static const struct qcom_cpufreq_match_data match_data_kryo = {
 	.get_version = qcom_cpufreq_kryo_name_version,
 };
 
+static const char *qcs404_genpd_names[] = { "cpr", NULL };
+
+static const struct qcom_cpufreq_match_data match_data_qcs404 = {
+	.genpd_names = qcs404_genpd_names,
+};
+
 static int qcom_cpufreq_probe(struct platform_device *pdev)
 {
 	struct qcom_cpufreq_drv *drv;
@@ -188,11 +197,19 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 		goto free_drv;
 	}
 
+	drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
+					sizeof(*drv->genpd_opp_tables),
+					GFP_KERNEL);
+	if (!drv->genpd_opp_tables) {
+		ret = -ENOMEM;
+		goto free_opp;
+	}
+
 	for_each_possible_cpu(cpu) {
 		cpu_dev = get_cpu_device(cpu);
 		if (NULL == cpu_dev) {
 			ret = -ENODEV;
-			goto free_opp;
+			goto free_genpd_opp;
 		}
 
 		if (drv->data->get_version) {
@@ -203,7 +220,22 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 				ret = PTR_ERR(drv->opp_tables[cpu]);
 				dev_err(cpu_dev,
 					"Failed to set supported hardware\n");
-				goto free_opp;
+				goto free_genpd_opp;
+			}
+		}
+
+		if (drv->data->genpd_names) {
+			drv->genpd_opp_tables[cpu] =
+				dev_pm_opp_attach_genpd(cpu_dev,
+							drv->data->genpd_names,
+							NULL);
+			if (IS_ERR(drv->genpd_opp_tables[cpu])) {
+				ret = PTR_ERR(drv->genpd_opp_tables[cpu]);
+				if (ret != -EPROBE_DEFER)
+					dev_err(cpu_dev,
+						"Could not attach to pm_domain: %d\n",
+						ret);
+				goto free_genpd_opp;
 			}
 		}
 	}
@@ -218,6 +250,13 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	ret = PTR_ERR(cpufreq_dt_pdev);
 	dev_err(cpu_dev, "Failed to register platform device\n");
 
+free_genpd_opp:
+	for_each_possible_cpu(cpu) {
+		if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu]))
+			break;
+		dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
+	}
+	kfree(drv->genpd_opp_tables);
 free_opp:
 	for_each_possible_cpu(cpu) {
 		if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
@@ -238,11 +277,15 @@ static int qcom_cpufreq_remove(struct platform_device *pdev)
 
 	platform_device_unregister(cpufreq_dt_pdev);
 
-	for_each_possible_cpu(cpu)
+	for_each_possible_cpu(cpu) {
 		if (drv->opp_tables[cpu])
 			dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
+		if (drv->genpd_opp_tables[cpu])
+			dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
+	}
 
 	kfree(drv->opp_tables);
+	kfree(drv->genpd_opp_tables);
 	kfree(drv);
 
 	return 0;
@@ -259,6 +302,7 @@ static struct platform_driver qcom_cpufreq_driver = {
 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
+	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 	{},
 };
 
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 08/14] cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (6 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 07/14] cpufreq: qcom: Add support for qcs404 on nvmem driver Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Niklas Cassel
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Rafael J. Wysocki, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, linux-pm,
	linux-kernel

From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>

Add qcs404 to cpufreq-dt-platdev blacklist.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index f9444ddd35ab..ec2057ddb4f4 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -125,6 +125,7 @@ static const struct of_device_id blacklist[] __initconst = {
 
 	{ .compatible = "qcom,apq8096", },
 	{ .compatible = "qcom,msm8996", },
+	{ .compatible = "qcom,qcs404", },
 
 	{ .compatible = "st,stih407", },
 	{ .compatible = "st,stih410", },
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (7 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 08/14] cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-08-19 10:12   ` [PATCH v3 " Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Niklas Cassel
                   ` (5 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Add qcom-opp bindings with properties needed for Core Power Reduction
(CPR).

CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and
msm8996. CPR was first introduced in msm8974.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 .../devicetree/bindings/opp/qcom-opp.txt      | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt

diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt
new file mode 100644
index 000000000000..f204685d029c
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt
@@ -0,0 +1,19 @@
+Qualcomm OPP bindings to describe OPP nodes
+
+The bindings are based on top of the operating-points-v2 bindings
+described in Documentation/devicetree/bindings/opp/opp.txt
+Additional properties are described below.
+
+* OPP Table Node
+
+Required properties:
+- compatible: Allow OPPs to express their compatibility. It should be:
+  "operating-points-v2-qcom-level"
+
+* OPP Node
+
+Optional properties:
+- qcom,opp-fuse-level: A positive value representing the fuse corner/level
+  associated with this OPP node. Sometimes several corners/levels shares
+  a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
+  min uV, and max uV.
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction)
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (8 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-08-17  6:14   ` Stephen Boyd
  2019-07-25 10:41 ` [PATCH v2 11/14] " Niklas Cassel
                   ` (4 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Niklas Cassel, Jorge Ramirez-Ortiz
  Cc: linux-arm-msm, sboyd, vireshk, bjorn.andersson, ulf.hansson,
	Rob Herring, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since V1:
-Picked up tags.

 .../bindings/power/avs/qcom,cpr.txt           | 193 ++++++++++++++++++
 1 file changed, 193 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt

diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
new file mode 100644
index 000000000000..93be67fa8f38
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
@@ -0,0 +1,193 @@
+QCOM CPR (Core Power Reduction)
+
+CPR (Core Power Reduction) is a technology to reduce core power on a CPU
+or other device. Each OPP of a device corresponds to a "corner" that has
+a range of valid voltages for a particular frequency. While the device is
+running at a particular frequency, CPR monitors dynamic factors such as
+temperature, etc. and suggests adjustments to the voltage to save power
+and meet silicon characteristic requirements.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: base address and size of the rbcpr register region
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the CPR interrupt
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: phandle to the reference clock
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: must be "ref"
+
+- vdd-apc-supply:
+	Usage: required
+	Value type: <phandle>
+	Definition: phandle to the vdd-apc-supply regulator
+
+- #power-domain-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: should be 0
+
+- operating-points-v2:
+	Usage: required
+	Value type: <phandle>
+	Definition: A phandle to the OPP table containing the
+		    performance states supported by the CPR
+		    power domain
+
+- acc-syscon:
+	Usage: optional
+	Value type: <phandle>
+	Definition: phandle to syscon for writing ACC settings
+
+- nvmem-cells:
+	Usage: required
+	Value type: <phandle>
+	Definition: phandle to nvmem cells containing the data
+		    that makes up a fuse corner, for each fuse corner.
+		    As well as the CPR fuse revision.
+
+- nvmem-cell-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2",
+		    "cpr_quotient_offset3", "cpr_init_voltage1",
+		    "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1",
+		    "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1",
+		    "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision"
+		    for qcs404.
+
+- qcom,cpr-timer-delay-us:
+	Usage: required
+	Value type: <u32>
+	Definition: delay in uS for the timer interval
+
+- qcom,cpr-timer-cons-up:
+	Usage: required
+	Value type: <u32>
+	Definition: Consecutive number of timer intervals, or units of
+		    qcom,cpr-timer-delay-us, that occur before issuing an up
+		    interrupt
+
+- qcom,cpr-timer-cons-down:
+	Usage: required
+	Value type: <u32>
+	Definition: Consecutive number of timer intervals, or units of
+		    qcom,cpr-timer-delay-us, that occur before issuing a down
+		    interrupt
+
+- qcom,cpr-up-threshold:
+	Usage: optional
+	Value type: <u32>
+	Definition: The threshold for CPR to issue interrupt when error_steps
+		    is greater than it when stepping up
+
+- qcom,cpr-down-threshold:
+	Usage: optional
+	Value type: <u32>
+	Definition: The threshold for CPR to issue interrupt when error_steps
+		    is greater than it when stepping down
+
+- qcom,cpr-idle-clocks:
+	Usage: optional
+	Value type: <u32>
+	Definition: Idle clock cycles ring oscillator can be in
+
+- qcom,cpr-gcnt-us:
+	Usage: required
+	Value type: <u32>
+	Definition: The time for gate count in uS
+
+- qcom,vdd-apc-step-up-limit:
+	Usage: required
+	Value type: <u32>
+	Definition: Limit of number of vdd-apc-supply regulator steps for
+		    scaling up
+
+- qcom,vdd-apc-step-down-limit:
+	Usage: required
+	Value type: <u32>
+	Definition: Limit of number of vdd-apc-supply regulator steps for
+		    scaling down
+
+Example:
+
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			....
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			....
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			....
+		};
+	};
+
+	cpr@b018000 {
+		compatible = "qcom,qcs404-cpr", "qcom,cpr";
+		reg = <0x0b018000 0x1000>;
+		interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&xo_board>;
+		clock-names = "ref";
+		vdd-apc-supply = <&pms405_s3>;
+		#power-domain-cells = <0>;
+		operating-points-v2 = <&cpr_opp_table>;
+		acc-syscon = <&tcsr>;
+
+		nvmem-cells = <&cpr_efuse_quot_offset1>,
+			<&cpr_efuse_quot_offset2>,
+			<&cpr_efuse_quot_offset3>,
+			<&cpr_efuse_init_voltage1>,
+			<&cpr_efuse_init_voltage2>,
+			<&cpr_efuse_init_voltage3>,
+			<&cpr_efuse_quot1>,
+			<&cpr_efuse_quot2>,
+			<&cpr_efuse_quot3>,
+			<&cpr_efuse_ring1>,
+			<&cpr_efuse_ring2>,
+			<&cpr_efuse_ring3>,
+			<&cpr_efuse_revision>;
+		nvmem-cell-names = "cpr_quotient_offset1",
+			"cpr_quotient_offset2",
+			"cpr_quotient_offset3",
+			"cpr_init_voltage1",
+			"cpr_init_voltage2",
+			"cpr_init_voltage3",
+			"cpr_quotient1",
+			"cpr_quotient2",
+			"cpr_quotient3",
+			"cpr_ring_osc1",
+			"cpr_ring_osc2",
+			"cpr_ring_osc3",
+			"cpr_fuse_revision";
+
+		qcom,cpr-timer-delay-us = <5000>;
+		qcom,cpr-timer-cons-up = <0>;
+		qcom,cpr-timer-cons-down = <2>;
+		qcom,cpr-up-threshold = <1>;
+		qcom,cpr-down-threshold = <3>;
+		qcom,cpr-idle-clocks = <15>;
+		qcom,cpr-gcnt-us = <1>;
+		qcom,vdd-apc-step-up-limit = <1>;
+		qcom,vdd-apc-step-down-limit = <1>;
+	};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 11/14] power: avs: Add support for CPR (Core Power Reduction)
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (9 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Niklas Cassel
@ 2019-07-25 10:41 ` " Niklas Cassel
  2019-08-18  1:04   ` Stephen Boyd
  2019-07-25 10:41 ` [PATCH v2 12/14] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Niklas Cassel
                   ` (3 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Kevin Hilman, Nishanth Menon, Andy Gross, Niklas Cassel,
	Jorge Ramirez-Ortiz
  Cc: linux-arm-msm, sboyd, vireshk, bjorn.andersson, ulf.hansson,
	linux-kernel, linux-pm

CPR (Core Power Reduction) is a technology that reduces core power on a
CPU or other device. It reads voltage settings in efuse from product
test process as initial settings.
Each OPP corresponds to a "corner" that has a range of valid voltages
for a particular frequency. While the device is running at a particular
frequency, CPR monitors dynamic factors such as temperature, etc. and
adjusts the voltage for that frequency accordingly to save power
and meet silicon characteristic requirements.

This driver is based on an RFC by Stephen Boyd[1], which in turn is
based on work by others on codeaurora.org[2].

[1] https://lkml.org/lkml/2015/9/18/833
[2] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/cpr-regulator.c?h=msm-3.10

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
Changes since V1:
-Implemented cpr_get_opp_hz_for_req() that uses
dev_pm_opp_find_level_exact(), in order to get the opp-hz
from the OPP's "required-opps" property, rather than duplicating the
opp-hz property in both the CPR OPP table and the CPU OPP table.

 MAINTAINERS                  |    9 +
 drivers/power/avs/Kconfig    |   15 +
 drivers/power/avs/Makefile   |    1 +
 drivers/power/avs/qcom-cpr.c | 1885 ++++++++++++++++++++++++++++++++++
 4 files changed, 1910 insertions(+)
 create mode 100644 drivers/power/avs/qcom-cpr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index d6b42e2413e4..a8177ff9f080 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13323,6 +13323,15 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
 F:	drivers/cpufreq/qcom-cpufreq-nvmem.c
 
+QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
+M:	Niklas Cassel <niklas.cassel@linaro.org>
+M:	Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+L:	linux-pm@vger.kernel.org
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
+F:	drivers/power/avs/qcom-cpr.c
+
 QUALCOMM EMAC GIGABIT ETHERNET DRIVER
 M:	Timur Tabi <timur@kernel.org>
 L:	netdev@vger.kernel.org
diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
index b5a217b828dc..4d4d742b3c6f 100644
--- a/drivers/power/avs/Kconfig
+++ b/drivers/power/avs/Kconfig
@@ -12,6 +12,21 @@ menuconfig POWER_AVS
 
 	  Say Y here to enable Adaptive Voltage Scaling class support.
 
+config QCOM_CPR
+	tristate "QCOM Core Power Reduction (CPR) support"
+	depends on POWER_AVS
+	select PM_OPP
+	help
+	  Say Y here to enable support for the CPR hardware found on Qualcomm
+	  SoCs like MSM8916.
+
+	  This driver populates CPU OPPs tables and makes adjustments to the
+	  tables based on feedback from the CPR hardware. If you want to do
+	  CPUfrequency scaling say Y here.
+
+	  To compile this driver as a module, choose M here: the module will
+	  be called qcom-cpr
+
 config ROCKCHIP_IODOMAIN
         tristate "Rockchip IO domain support"
         depends on POWER_AVS && ARCH_ROCKCHIP && OF
diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
index a1b8cd453f19..8cd17e6660ee 100644
--- a/drivers/power/avs/Makefile
+++ b/drivers/power/avs/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_POWER_AVS_OMAP)		+= smartreflex.o
 obj-$(CONFIG_ROCKCHIP_IODOMAIN)		+= rockchip-io-domain.o
+obj-$(CONFIG_QCOM_CPR)			+= qcom-cpr.o
diff --git a/drivers/power/avs/qcom-cpr.c b/drivers/power/avs/qcom-cpr.c
new file mode 100644
index 000000000000..d6bce2832589
--- /dev/null
+++ b/drivers/power/avs/qcom-cpr.c
@@ -0,0 +1,1885 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/bitops.h>
+
+/* Register Offsets for RB-CPR and Bit Definitions */
+
+/* RBCPR Version Register */
+#define REG_RBCPR_VERSION		0
+#define RBCPR_VER_2			0x02
+#define FLAGS_IGNORE_1ST_IRQ_STATUS	BIT(0)
+
+/* RBCPR Gate Count and Target Registers */
+#define REG_RBCPR_GCNT_TARGET(n)	(0x60 + 4 * (n))
+
+#define RBCPR_GCNT_TARGET_TARGET_SHIFT	0
+#define RBCPR_GCNT_TARGET_TARGET_MASK	GENMASK(11, 0)
+#define RBCPR_GCNT_TARGET_GCNT_SHIFT	12
+#define RBCPR_GCNT_TARGET_GCNT_MASK	GENMASK(9, 0)
+
+/* RBCPR Timer Control */
+#define REG_RBCPR_TIMER_INTERVAL	0x44
+#define REG_RBIF_TIMER_ADJUST		0x4c
+
+#define RBIF_TIMER_ADJ_CONS_UP_MASK	GENMASK(3, 0)
+#define RBIF_TIMER_ADJ_CONS_UP_SHIFT	0
+#define RBIF_TIMER_ADJ_CONS_DOWN_MASK	GENMASK(3, 0)
+#define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT	4
+#define RBIF_TIMER_ADJ_CLAMP_INT_MASK	GENMASK(7, 0)
+#define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT	8
+
+/* RBCPR Config Register */
+#define REG_RBIF_LIMIT			0x48
+#define RBIF_LIMIT_CEILING_MASK		GENMASK(5, 0)
+#define RBIF_LIMIT_CEILING_SHIFT	6
+#define RBIF_LIMIT_FLOOR_BITS		6
+#define RBIF_LIMIT_FLOOR_MASK		GENMASK(5, 0)
+
+#define RBIF_LIMIT_CEILING_DEFAULT	RBIF_LIMIT_CEILING_MASK
+#define RBIF_LIMIT_FLOOR_DEFAULT	0
+
+#define REG_RBIF_SW_VLEVEL		0x94
+#define RBIF_SW_VLEVEL_DEFAULT		0x20
+
+#define REG_RBCPR_STEP_QUOT		0x80
+#define RBCPR_STEP_QUOT_STEPQUOT_MASK	GENMASK(7, 0)
+#define RBCPR_STEP_QUOT_IDLE_CLK_MASK	GENMASK(3, 0)
+#define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT	8
+
+/* RBCPR Control Register */
+#define REG_RBCPR_CTL			0x90
+
+#define RBCPR_CTL_LOOP_EN			BIT(0)
+#define RBCPR_CTL_TIMER_EN			BIT(3)
+#define RBCPR_CTL_SW_AUTO_CONT_ACK_EN		BIT(5)
+#define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN	BIT(6)
+#define RBCPR_CTL_COUNT_MODE			BIT(10)
+#define RBCPR_CTL_UP_THRESHOLD_MASK	GENMASK(3, 0)
+#define RBCPR_CTL_UP_THRESHOLD_SHIFT	24
+#define RBCPR_CTL_DN_THRESHOLD_MASK	GENMASK(3, 0)
+#define RBCPR_CTL_DN_THRESHOLD_SHIFT	28
+
+/* RBCPR Ack/Nack Response */
+#define REG_RBIF_CONT_ACK_CMD		0x98
+#define REG_RBIF_CONT_NACK_CMD		0x9c
+
+/* RBCPR Result status Register */
+#define REG_RBCPR_RESULT_0		0xa0
+
+#define RBCPR_RESULT0_BUSY_SHIFT	19
+#define RBCPR_RESULT0_BUSY_MASK		BIT(RBCPR_RESULT0_BUSY_SHIFT)
+#define RBCPR_RESULT0_ERROR_LT0_SHIFT	18
+#define RBCPR_RESULT0_ERROR_SHIFT	6
+#define RBCPR_RESULT0_ERROR_MASK	GENMASK(11, 0)
+#define RBCPR_RESULT0_ERROR_STEPS_SHIFT	2
+#define RBCPR_RESULT0_ERROR_STEPS_MASK	GENMASK(3, 0)
+#define RBCPR_RESULT0_STEP_UP_SHIFT	1
+
+/* RBCPR Interrupt Control Register */
+#define REG_RBIF_IRQ_EN(n)		(0x100 + 4 * (n))
+#define REG_RBIF_IRQ_CLEAR		0x110
+#define REG_RBIF_IRQ_STATUS		0x114
+
+#define CPR_INT_DONE		BIT(0)
+#define CPR_INT_MIN		BIT(1)
+#define CPR_INT_DOWN		BIT(2)
+#define CPR_INT_MID		BIT(3)
+#define CPR_INT_UP		BIT(4)
+#define CPR_INT_MAX		BIT(5)
+#define CPR_INT_CLAMP		BIT(6)
+#define CPR_INT_ALL	(CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
+			CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
+#define CPR_INT_DEFAULT	(CPR_INT_UP | CPR_INT_DOWN)
+
+#define CPR_NUM_RING_OSC	8
+
+/* CPR eFuse parameters */
+#define CPR_FUSE_TARGET_QUOT_BITS_MASK	GENMASK(11, 0)
+
+#define CPR_FUSE_MIN_QUOT_DIFF		50
+
+#define FUSE_REVISION_UNKNOWN		(-1)
+
+enum voltage_change_dir {
+	NO_CHANGE,
+	DOWN,
+	UP,
+};
+
+struct cpr_fuse {
+	char *ring_osc;
+	char *init_voltage;
+	char *quotient;
+	char *quotient_offset;
+};
+
+struct fuse_corner_data {
+	int ref_uV;
+	int max_uV;
+	int min_uV;
+	int max_volt_scale;
+	int max_quot_scale;
+	/* fuse quot */
+	int quot_offset;
+	int quot_scale;
+	int quot_adjust;
+	/* fuse quot_offset */
+	int quot_offset_scale;
+	int quot_offset_adjust;
+};
+
+struct cpr_fuses {
+	int init_voltage_step;
+	int init_voltage_width;
+	struct fuse_corner_data *fuse_corner_data;
+};
+
+struct pvs_bin {
+	int *uV;
+};
+
+struct pvs_fuses {
+	char **pvs_fuse;
+	struct pvs_bin *pvs_bins;
+};
+
+struct corner_data {
+	unsigned int fuse_corner;
+	unsigned long freq;
+};
+
+struct cpr_desc {
+	unsigned int num_fuse_corners;
+	int min_diff_quot;
+	int *step_quot;
+	struct cpr_fuses cpr_fuses;
+	struct pvs_fuses *pvs_fuses;
+	bool reduce_to_fuse_uV;
+	bool reduce_to_corner_uV;
+};
+
+struct acc_desc {
+	unsigned int	enable_reg;
+	u32		enable_mask;
+
+	struct reg_sequence	*config;
+	struct reg_sequence	*settings;
+	int			num_regs_per_fuse;
+};
+
+struct cpr_acc_desc {
+	const struct cpr_desc *cpr_desc;
+	const struct acc_desc *acc_desc;
+};
+
+struct fuse_corner {
+	int min_uV;
+	int max_uV;
+	int uV;
+	int quot;
+	int step_quot;
+	const struct reg_sequence *accs;
+	int num_accs;
+	unsigned long max_freq;
+	u32 ring_osc_idx;
+};
+
+struct corner {
+	int min_uV;
+	int max_uV;
+	int uV;
+	int last_uV;
+	int quot_adjust;
+	u32 save_ctl;
+	u32 save_irq;
+	unsigned long freq;
+	struct fuse_corner *fuse_corner;
+};
+
+struct cpr_drv {
+	unsigned int		num_corners;
+
+	unsigned int		ref_clk_khz;
+	unsigned int		timer_delay_us;
+	unsigned int		timer_cons_up;
+	unsigned int		timer_cons_down;
+	unsigned int		up_threshold;
+	unsigned int		down_threshold;
+	unsigned int		idle_clocks;
+	unsigned int		gcnt_us;
+	unsigned int		vdd_apc_step_up_limit;
+	unsigned int		vdd_apc_step_down_limit;
+	unsigned int		clamp_timer_interval;
+	unsigned int		performance_state;
+
+	struct generic_pm_domain pd;
+	struct device		*dev;
+	struct mutex		lock;
+	void __iomem		*base;
+	struct corner		*corner;
+	struct regulator	*vdd_apc;
+	struct clk		*cpu_clk;
+	struct regmap		*tcsr;
+	bool			loop_disabled;
+	bool			suspended;
+	u32			gcnt;
+	unsigned long		flags;
+
+	struct fuse_corner	*fuse_corners;
+	struct corner		*corners;
+
+	const struct cpr_desc *desc;
+	const struct acc_desc *acc_desc;
+	const struct cpr_fuse *cpr_fuses;
+
+	struct dentry *debugfs;
+};
+
+static bool cpr_is_allowed(struct cpr_drv *drv)
+{
+	if (drv->loop_disabled)
+		return false;
+	else
+		return true;
+}
+
+static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
+{
+	writel_relaxed(value, drv->base + offset);
+}
+
+static u32 cpr_read(struct cpr_drv *drv, u32 offset)
+{
+	return readl_relaxed(drv->base + offset);
+}
+
+static void
+cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
+{
+	u32 val;
+
+	val = readl_relaxed(drv->base + offset);
+	val &= ~mask;
+	val |= value & mask;
+	writel_relaxed(val, drv->base + offset);
+}
+
+static void cpr_irq_clr(struct cpr_drv *drv)
+{
+	cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
+}
+
+static void cpr_irq_clr_nack(struct cpr_drv *drv)
+{
+	cpr_irq_clr(drv);
+	cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
+}
+
+static void cpr_irq_clr_ack(struct cpr_drv *drv)
+{
+	cpr_irq_clr(drv);
+	cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
+}
+
+static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
+{
+	cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
+}
+
+static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
+{
+	cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
+}
+
+static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
+{
+	u32 val, mask;
+
+	if (drv->suspended)
+		return;
+
+	/* Program Consecutive Up & Down */
+	val = drv->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
+	val |= drv->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
+	mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
+	cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
+	cpr_masked_write(drv, REG_RBCPR_CTL,
+			 RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
+			 RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
+			 corner->save_ctl);
+	cpr_irq_set(drv, corner->save_irq);
+
+	if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
+		val = RBCPR_CTL_LOOP_EN;
+	else
+		val = 0;
+	cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
+}
+
+static void cpr_ctl_disable(struct cpr_drv *drv)
+{
+	if (drv->suspended)
+		return;
+
+	cpr_irq_set(drv, 0);
+	cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
+		       RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
+	cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
+			 RBIF_TIMER_ADJ_CONS_UP_MASK |
+			 RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
+	cpr_irq_clr(drv);
+	cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
+	cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
+	cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
+}
+
+static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
+{
+	u32 reg_val;
+
+	reg_val = cpr_read(drv, REG_RBCPR_CTL);
+	return reg_val & RBCPR_CTL_LOOP_EN;
+}
+
+static bool cpr_ctl_is_busy(struct cpr_drv *drv)
+{
+	u32 reg_val;
+
+	reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
+	return reg_val & RBCPR_RESULT0_BUSY_MASK;
+}
+
+static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
+{
+	corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
+	corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
+}
+
+static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
+{
+	u32 gcnt, ctl, irq, ro_sel, step_quot;
+	struct fuse_corner *fuse = corner->fuse_corner;
+	int i;
+
+	ro_sel = fuse->ring_osc_idx;
+	gcnt = drv->gcnt;
+	gcnt |= fuse->quot - corner->quot_adjust;
+
+	/* Program the step quotient and idle clocks */
+	step_quot = drv->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
+	step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
+	cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
+
+	/* Clear the target quotient value and gate count of all ROs */
+	for (i = 0; i < CPR_NUM_RING_OSC; i++)
+		cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
+
+	cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
+	ctl = corner->save_ctl;
+	cpr_write(drv, REG_RBCPR_CTL, ctl);
+	irq = corner->save_irq;
+	cpr_irq_set(drv, irq);
+	dev_dbg(drv->dev, "gcnt = 0x%08x, ctl = 0x%08x, irq = 0x%08x\n", gcnt,
+		ctl, irq);
+}
+
+static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
+			struct fuse_corner *end)
+{
+	if (f < end) {
+		for (f += 1; f <= end; f++)
+			regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
+	} else {
+		for (f -= 1; f >= end; f--)
+			regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
+	}
+}
+
+static int cpr_pre_voltage(struct cpr_drv *drv,
+			   struct fuse_corner *fuse_corner,
+			   enum voltage_change_dir dir)
+{
+	int ret = 0;
+	struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
+
+	if (drv->tcsr && dir == DOWN)
+		cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
+
+	return ret;
+}
+
+static int cpr_post_voltage(struct cpr_drv *drv,
+			    struct fuse_corner *fuse_corner,
+			    enum voltage_change_dir dir)
+{
+	int ret = 0;
+	struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
+
+	if (drv->tcsr && dir == UP)
+		cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
+
+	return ret;
+}
+
+static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
+			     int new_uV, enum voltage_change_dir dir)
+{
+	int ret = 0;
+	struct fuse_corner *fuse_corner = corner->fuse_corner;
+
+	ret = cpr_pre_voltage(drv, fuse_corner, dir);
+	if (ret)
+		return ret;
+
+	ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
+	if (ret) {
+		dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
+				    new_uV);
+		return ret;
+	}
+
+	ret = cpr_post_voltage(drv, fuse_corner, dir);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
+{
+	u32 val, error_steps, reg_mask;
+	int last_uV, new_uV, step_uV, ret;
+	struct corner *corner;
+
+	if (dir != UP && dir != DOWN)
+		return 0;
+
+	step_uV = regulator_get_linear_step(drv->vdd_apc);
+	if (!step_uV)
+		return -EINVAL;
+
+	corner = drv->corner;
+
+	val = cpr_read(drv, REG_RBCPR_RESULT_0);
+
+	error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
+	error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
+	last_uV = corner->last_uV;
+
+	if (dir == UP) {
+		if (drv->clamp_timer_interval &&
+		    error_steps < drv->up_threshold) {
+			/*
+			 * Handle the case where another measurement started
+			 * after the interrupt was triggered due to a core
+			 * exiting from power collapse.
+			 */
+			error_steps = max(drv->up_threshold,
+					  drv->vdd_apc_step_up_limit);
+		}
+
+		if (last_uV >= corner->max_uV) {
+			cpr_irq_clr_nack(drv);
+
+			/* Maximize the UP threshold */
+			reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
+			reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+			val = reg_mask;
+			cpr_ctl_modify(drv, reg_mask, val);
+
+			/* Disable UP interrupt */
+			cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
+
+			return 0;
+		}
+
+		if (error_steps > drv->vdd_apc_step_up_limit)
+			error_steps = drv->vdd_apc_step_up_limit;
+
+		/* Calculate new voltage */
+		new_uV = last_uV + error_steps * step_uV;
+		new_uV = min(new_uV, corner->max_uV);
+
+		dev_dbg(drv->dev,
+			"UP: -> new_uV: %d last_uV: %d perf state: %d\n",
+			new_uV, last_uV, drv->performance_state);
+	} else if (dir == DOWN) {
+		if (drv->clamp_timer_interval &&
+		    error_steps < drv->down_threshold) {
+			/*
+			 * Handle the case where another measurement started
+			 * after the interrupt was triggered due to a core
+			 * exiting from power collapse.
+			 */
+			error_steps = max(drv->down_threshold,
+					  drv->vdd_apc_step_down_limit);
+		}
+
+		if (last_uV <= corner->min_uV) {
+			cpr_irq_clr_nack(drv);
+
+			/* Enable auto nack down */
+			reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+			val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+
+			cpr_ctl_modify(drv, reg_mask, val);
+
+			/* Disable DOWN interrupt */
+			cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
+
+			return 0;
+		}
+
+		if (error_steps > drv->vdd_apc_step_down_limit)
+			error_steps = drv->vdd_apc_step_down_limit;
+
+		/* Calculate new voltage */
+		new_uV = last_uV - error_steps * step_uV;
+		new_uV = max(new_uV, corner->min_uV);
+
+		dev_dbg(drv->dev,
+			"DOWN: -> new_uV: %d last_uV: %d perf state: %d\n",
+			new_uV, last_uV, drv->performance_state);
+	}
+
+	ret = cpr_scale_voltage(drv, corner, new_uV, dir);
+	if (ret) {
+		cpr_irq_clr_nack(drv);
+		return ret;
+	}
+	drv->corner->last_uV = new_uV;
+
+	if (dir == UP) {
+		/* Disable auto nack down */
+		reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
+		val = 0;
+	} else if (dir == DOWN) {
+		/* Restore default threshold for UP */
+		reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
+		reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+		val = drv->up_threshold;
+		val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
+	}
+
+	cpr_ctl_modify(drv, reg_mask, val);
+
+	/* Re-enable default interrupts */
+	cpr_irq_set(drv, CPR_INT_DEFAULT);
+
+	/* Ack */
+	cpr_irq_clr_ack(drv);
+
+	return 0;
+}
+
+static irqreturn_t cpr_irq_handler(int irq, void *dev)
+{
+	struct cpr_drv *drv = dev;
+	u32 val;
+
+	mutex_lock(&drv->lock);
+
+	val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+	if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
+		val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+
+	dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
+
+	if (!cpr_ctl_is_enabled(drv)) {
+		dev_dbg(drv->dev, "CPR is disabled\n");
+		goto unlock;
+	} else if (cpr_ctl_is_busy(drv) && !drv->clamp_timer_interval) {
+		dev_dbg(drv->dev, "CPR measurement is not ready\n");
+		goto unlock;
+	} else if (!cpr_is_allowed(drv)) {
+		val = cpr_read(drv, REG_RBCPR_CTL);
+		dev_err_ratelimited(drv->dev,
+				    "Interrupt broken? RBCPR_CTL = %#02x\n",
+				    val);
+		goto unlock;
+	}
+
+	/* Following sequence of handling is as per each IRQ's priority */
+	if (val & CPR_INT_UP) {
+		cpr_scale(drv, UP);
+	} else if (val & CPR_INT_DOWN) {
+		cpr_scale(drv, DOWN);
+	} else if (val & CPR_INT_MIN) {
+		cpr_irq_clr_nack(drv);
+	} else if (val & CPR_INT_MAX) {
+		cpr_irq_clr_nack(drv);
+	} else if (val & CPR_INT_MID) {
+		/* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
+		dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
+	} else {
+		dev_dbg(drv->dev, "IRQ occurred for unknown flag (%#08x)\n",
+			val);
+	}
+
+	/* Save register values for the corner */
+	cpr_corner_save(drv, drv->corner);
+
+unlock:
+	mutex_unlock(&drv->lock);
+
+	return IRQ_HANDLED;
+}
+
+static int cpr_enable(struct cpr_drv *drv)
+{
+	int ret;
+
+	ret = regulator_enable(drv->vdd_apc);
+	if (ret)
+		return ret;
+
+	mutex_lock(&drv->lock);
+
+	if (cpr_is_allowed(drv) && drv->corner) {
+		cpr_irq_clr(drv);
+		cpr_corner_restore(drv, drv->corner);
+		cpr_ctl_enable(drv, drv->corner);
+	}
+	mutex_unlock(&drv->lock);
+
+	return 0;
+}
+
+static int cpr_disable(struct cpr_drv *drv)
+{
+	int ret;
+
+	ret = regulator_disable(drv->vdd_apc);
+	if (ret)
+		return ret;
+
+	mutex_lock(&drv->lock);
+
+	if (cpr_is_allowed(drv))
+		cpr_ctl_disable(drv);
+	mutex_unlock(&drv->lock);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int cpr_suspend(struct device *dev)
+{
+	struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
+
+	if (cpr_is_allowed(drv)) {
+		mutex_lock(&drv->lock);
+		cpr_ctl_disable(drv);
+		cpr_irq_clr(drv);
+		drv->suspended = true;
+		mutex_unlock(&drv->lock);
+	}
+
+	return 0;
+}
+
+static int cpr_resume(struct device *dev)
+{
+	struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
+
+	if (cpr_is_allowed(drv)) {
+		mutex_lock(&drv->lock);
+		drv->suspended = false;
+		cpr_irq_clr(drv);
+		cpr_ctl_enable(drv, drv->corner);
+		mutex_unlock(&drv->lock);
+	}
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(cpr_pm_ops, cpr_suspend, cpr_resume);
+
+static int cpr_config(struct cpr_drv *drv)
+{
+	int i;
+	u32 val, gcnt;
+	struct corner *corner;
+
+	/* Disable interrupt and CPR */
+	cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
+	cpr_write(drv, REG_RBCPR_CTL, 0);
+
+	/* Program the default HW Ceiling, Floor and vlevel */
+	val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
+		<< RBIF_LIMIT_CEILING_SHIFT;
+	val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
+	cpr_write(drv, REG_RBIF_LIMIT, val);
+	cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
+
+	/* Clear the target quotient value and gate count of all ROs */
+	for (i = 0; i < CPR_NUM_RING_OSC; i++)
+		cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
+
+	/* Init and save gcnt */
+	gcnt = (drv->ref_clk_khz * drv->gcnt_us) / 1000;
+	gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
+	gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
+	drv->gcnt = gcnt;
+
+	/* Program the delay count for the timer */
+	val = (drv->ref_clk_khz * drv->timer_delay_us) / 1000;
+	cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
+	dev_dbg(drv->dev, "Timer count: 0x%0x (for %d us)\n", val,
+		drv->timer_delay_us);
+
+	/* Program Consecutive Up & Down */
+	val = drv->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
+	val |= drv->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
+	val |= drv->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
+	cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
+
+	/* Program the control register */
+	val = drv->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
+	val |= drv->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
+	val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
+	val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
+	cpr_write(drv, REG_RBCPR_CTL, val);
+
+	for (i = 0; i < drv->num_corners; i++) {
+		corner = &drv->corners[i];
+		corner->save_ctl = val;
+		corner->save_irq = CPR_INT_DEFAULT;
+	}
+
+	cpr_irq_set(drv, CPR_INT_DEFAULT);
+
+	val = cpr_read(drv, REG_RBCPR_VERSION);
+	if (val <= RBCPR_VER_2)
+		drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
+
+	return 0;
+}
+
+static int cpr_set_performance(struct generic_pm_domain *domain,
+			       unsigned int state)
+{
+	struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+	struct corner *corner, *end;
+	enum voltage_change_dir dir;
+	int ret = 0, new_uV;
+
+	mutex_lock(&drv->lock);
+
+	dev_dbg(drv->dev, "%s: setting perf state: %d (prev state: %d)\n",
+		__func__, state, drv->performance_state);
+
+	/* Determine new corner we're going to */
+	/* Remove one since lowest performance state is 1.
+	 */
+	corner = drv->corners + state - 1;
+	end = &drv->corners[drv->num_corners - 1];
+	if (corner > end || corner < drv->corners) {
+		ret = -EINVAL;
+		goto unlock;
+	}
+
+	/* Determine direction */
+	if (drv->corner > corner)
+		dir = DOWN;
+	else if (drv->corner < corner)
+		dir = UP;
+	else
+		dir = NO_CHANGE;
+
+	if (cpr_is_allowed(drv))
+		new_uV = corner->last_uV;
+	else
+		new_uV = corner->uV;
+
+	if (cpr_is_allowed(drv))
+		cpr_ctl_disable(drv);
+
+	ret = cpr_scale_voltage(drv, corner, new_uV, dir);
+	if (ret)
+		goto unlock;
+
+	if (cpr_is_allowed(drv)) {
+		cpr_irq_clr(drv);
+		if (drv->corner != corner)
+			cpr_corner_restore(drv, corner);
+		cpr_ctl_enable(drv, corner);
+	}
+
+	drv->corner = corner;
+	drv->performance_state = state;
+
+unlock:
+	mutex_unlock(&drv->lock);
+
+	return ret;
+}
+
+static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
+{
+	struct nvmem_cell *cell;
+	ssize_t len;
+	char *ret;
+	int i;
+
+	if (!data) {
+		dev_err(dev, "invalid storage to read cell %s\n", cname);
+		return -EINVAL;
+	}
+
+	/* Optional cells will use their initialition values */
+	if (!cname)
+		return 0;
+
+	*data = 0;
+
+	cell = nvmem_cell_get(dev, cname);
+	if (IS_ERR(cell)) {
+		if (PTR_ERR(cell) != -EPROBE_DEFER)
+			dev_info(dev, "undefined cell %s\n", cname);
+		return PTR_ERR(cell);
+	}
+
+	ret = nvmem_cell_read(cell, &len);
+	nvmem_cell_put(cell);
+	if (IS_ERR(ret)) {
+		dev_err(dev, "can't read cell %s\n", cname);
+		return PTR_ERR(ret);
+	}
+
+	for (i = 0; i < len; i++)
+		*data |= ret[i] << (8 * i);
+
+	kfree(ret);
+	dev_dbg(dev, "efuse read(%s) = %x, bytes %ld\n", cname, *data, len);
+
+	return 0;
+}
+
+static int
+cpr_populate_ring_osc_idx(struct cpr_drv *drv)
+{
+	struct fuse_corner *fuse = drv->fuse_corners;
+	struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
+	const struct cpr_fuse *fuses = drv->cpr_fuses;
+	int ret;
+
+	for (; fuse < end; fuse++, fuses++) {
+		ret = cpr_read_efuse(drv->dev, fuses->ring_osc,
+				     &fuse->ring_osc_idx);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int cpr_read_fuse_uV(const struct cpr_desc *desc,
+			    const struct fuse_corner_data *fdata,
+			    const char *init_v_efuse,
+			    int step_volt,
+			    struct cpr_drv *drv)
+{
+	int step_size_uV, steps, uV;
+	u32 bits = 0;
+	int ret;
+
+	ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits);
+	if (ret)
+		return ret;
+
+	steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
+	/* Not two's complement.. instead highest bit is sign bit */
+	if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
+		steps = -steps;
+
+	step_size_uV = desc->cpr_fuses.init_voltage_step;
+
+	uV = fdata->ref_uV + steps * step_size_uV;
+	return DIV_ROUND_UP(uV, step_volt) * step_volt;
+}
+
+static int cpr_fuse_corner_init(struct cpr_drv *drv)
+{
+	const struct cpr_desc *desc = drv->desc;
+	const struct cpr_fuse *fuses = drv->cpr_fuses;
+	const struct acc_desc *acc_desc = drv->acc_desc;
+	int i;
+	unsigned int step_volt;
+	struct fuse_corner_data *fdata;
+	struct fuse_corner *fuse, *end, *prev;
+	int uV;
+	const struct reg_sequence *accs;
+	int ret;
+
+	accs = acc_desc->settings;
+
+	step_volt = regulator_get_linear_step(drv->vdd_apc);
+	if (!step_volt)
+		return -EINVAL;
+
+	/* Populate fuse_corner members */
+	fuse = drv->fuse_corners;
+	end = &fuse[desc->num_fuse_corners - 1];
+	fdata = desc->cpr_fuses.fuse_corner_data;
+
+	for (i = 0, prev = NULL; fuse <= end; fuse++, fuses++, i++, fdata++) {
+		/* Update SoC voltages: platforms might choose a different
+		 * regulators than the one used to characterize the algorithms
+		 * (ie, init_voltage_step).
+		 */
+		fdata->min_uV = roundup(fdata->min_uV, step_volt);
+		fdata->max_uV = roundup(fdata->max_uV, step_volt);
+
+		/* Populate uV */
+		uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
+				      step_volt, drv);
+		if (uV < 0)
+			return ret;
+
+		fuse->min_uV = fdata->min_uV;
+		fuse->max_uV = fdata->max_uV;
+		fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
+
+		if (fuse == end) {
+			/*
+			 * Allow the highest fuse corner's PVS voltage to
+			 * define the ceiling voltage for that corner in order
+			 * to support SoC's in which variable ceiling values
+			 * are required.
+			 */
+			end->max_uV = max(end->max_uV, end->uV);
+		}
+
+		/* Populate target quotient by scaling */
+		ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot);
+		if (ret)
+			return ret;
+
+		fuse->quot *= fdata->quot_scale;
+		fuse->quot += fdata->quot_offset;
+		fuse->quot += fdata->quot_adjust;
+		fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
+
+		/* Populate acc settings */
+		fuse->accs = accs;
+		fuse->num_accs = acc_desc->num_regs_per_fuse;
+		accs += acc_desc->num_regs_per_fuse;
+	}
+
+	/*
+	 * Restrict all fuse corner PVS voltages based upon per corner
+	 * ceiling and floor voltages.
+	 */
+	for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
+		if (fuse->uV > fuse->max_uV)
+			fuse->uV = fuse->max_uV;
+		else if (fuse->uV < fuse->min_uV)
+			fuse->uV = fuse->min_uV;
+
+		ret = regulator_is_supported_voltage(drv->vdd_apc,
+						     fuse->min_uV,
+						     fuse->min_uV);
+		if (!ret) {
+			dev_err(drv->dev,
+				"min uV: %d (fuse corner: %d) not supported by regulator\n",
+				fuse->min_uV, i);
+			return -EINVAL;
+		}
+
+		ret = regulator_is_supported_voltage(drv->vdd_apc,
+						     fuse->max_uV,
+						     fuse->max_uV);
+		if (!ret) {
+			dev_err(drv->dev,
+				"max uV: %d (fuse corner: %d) not supported by regulator\n",
+				fuse->max_uV, i);
+			return -EINVAL;
+		}
+
+		dev_dbg(drv->dev,
+			"fuse corner %d: [%d %d %d] RO%d quot %d squot %d\n",
+			i, fuse->min_uV, fuse->uV, fuse->max_uV,
+			fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
+	}
+
+	return 0;
+}
+
+static int cpr_calculate_scaling(const char *quot_offset,
+				 struct cpr_drv *drv,
+				 const struct fuse_corner_data *fdata,
+				 const struct corner *corner)
+{
+	u32 quot_diff = 0;
+	unsigned long freq_diff;
+	int scaling;
+	const struct fuse_corner *fuse, *prev_fuse;
+	int ret;
+
+	fuse = corner->fuse_corner;
+	prev_fuse = fuse - 1;
+
+	if (quot_offset) {
+		ret = cpr_read_efuse(drv->dev, quot_offset, &quot_diff);
+		if (ret)
+			return ret;
+
+		quot_diff *= fdata->quot_offset_scale;
+		quot_diff += fdata->quot_offset_adjust;
+	} else {
+		quot_diff = fuse->quot - prev_fuse->quot;
+	}
+
+	freq_diff = fuse->max_freq - prev_fuse->max_freq;
+	freq_diff /= 1000000; /* Convert to MHz */
+	scaling = 1000 * quot_diff / freq_diff;
+	return min(scaling, fdata->max_quot_scale);
+}
+
+static int cpr_interpolate(const struct corner *corner, int step_volt,
+			   const struct fuse_corner_data *fdata)
+{
+	unsigned long f_high, f_low, f_diff;
+	int uV_high, uV_low, uV;
+	u64 temp, temp_limit;
+	const struct fuse_corner *fuse, *prev_fuse;
+
+	fuse = corner->fuse_corner;
+	prev_fuse = fuse - 1;
+
+	f_high = fuse->max_freq;
+	f_low = prev_fuse->max_freq;
+	uV_high = fuse->uV;
+	uV_low = prev_fuse->uV;
+	f_diff = fuse->max_freq - corner->freq;
+
+	/*
+	 * Don't interpolate in the wrong direction. This could happen
+	 * if the adjusted fuse voltage overlaps with the previous fuse's
+	 * adjusted voltage.
+	 */
+	if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
+		return corner->uV;
+
+	temp = f_diff * (uV_high - uV_low);
+	do_div(temp, f_high - f_low);
+
+	/*
+	 * max_volt_scale has units of uV/MHz while freq values
+	 * have units of Hz.  Divide by 1000000 to convert to.
+	 */
+	temp_limit = f_diff * fdata->max_volt_scale;
+	do_div(temp_limit, 1000000);
+
+	uV = uV_high - min(temp, temp_limit);
+	return roundup(uV, step_volt);
+}
+
+static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
+{
+	struct device_node *np;
+	unsigned int fuse_corner = 0;
+
+	np = dev_pm_opp_get_of_node(opp);
+	if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner)) {
+		pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
+		       __func__);
+		return 0;
+	}
+
+	of_node_put(np);
+
+	return fuse_corner;
+}
+
+unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref)
+{
+	u64 rate = 0;
+	struct device *cpu_dev;
+	struct device_node *ref_np;
+	struct device_node *desc_np;
+	struct device_node *child_np = NULL;
+	struct device_node *child_req_np = NULL;
+
+	cpu_dev = get_cpu_device(0);
+	if (!cpu_dev)
+		return 0;
+
+	desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
+	if (!desc_np)
+		return 0;
+
+	ref_np = dev_pm_opp_get_of_node(ref);
+	if (!ref_np)
+		goto out_ref;
+
+	do {
+		of_node_put(child_req_np);
+		child_np = of_get_next_available_child(desc_np, child_np);
+		child_req_np = of_parse_phandle(child_np, "required-opps", 0);
+	} while (child_np && child_req_np != ref_np);
+
+	if (child_np && child_req_np == ref_np)
+		of_property_read_u64(child_np, "opp-hz", &rate);
+
+	of_node_put(child_req_np);
+	of_node_put(child_np);
+	of_node_put(ref_np);
+out_ref:
+	of_node_put(desc_np);
+
+	return (unsigned long) rate;
+}
+
+static int cpr_corner_init(struct cpr_drv *drv)
+{
+	const struct cpr_desc *desc = drv->desc;
+	const struct cpr_fuse *fuses = drv->cpr_fuses;
+	int i, level, count, scaling = 0;
+	unsigned int fnum, fc;
+	const char *quot_offset;
+	struct fuse_corner *fuse, *prev_fuse;
+	struct corner *corner, *end;
+	struct corner_data *cdata;
+	const struct fuse_corner_data *fdata;
+	bool apply_scaling;
+	unsigned long freq_diff, freq_diff_mhz;
+	unsigned long freq;
+	int step_volt = regulator_get_linear_step(drv->vdd_apc);
+	struct dev_pm_opp *opp;
+	struct device *pd_dev;
+
+	if (!step_volt)
+		return -EINVAL;
+
+	corner = drv->corners;
+	end = &corner[drv->num_corners - 1];
+
+	pd_dev = &drv->pd.dev;
+	cdata = devm_kzalloc(drv->dev,
+			     sizeof(struct corner_data) * drv->num_corners,
+			     GFP_KERNEL);
+	if (!cdata)
+		return -ENOMEM;
+
+	/*
+	 * Store maximum frequency for each fuse corner based on the frequency
+	 * plan
+	 */
+	count = dev_pm_opp_get_opp_count(pd_dev);
+	for (level = 1; level <= count; level++) {
+		opp = dev_pm_opp_find_level_exact(pd_dev, level);
+		if (IS_ERR(opp))
+			return -EINVAL;
+		fc = cpr_get_fuse_corner(opp);
+		if (!fc) {
+			dev_pm_opp_put(opp);
+			return -EINVAL;
+		}
+		fnum = fc - 1;
+		freq = cpr_get_opp_hz_for_req(opp);
+		if (!freq) {
+			dev_pm_opp_put(opp);
+			return -EINVAL;
+		}
+		cdata[level - 1].fuse_corner = fnum;
+		cdata[level - 1].freq = freq;
+
+		fuse = &drv->fuse_corners[fnum];
+		dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
+			freq, dev_pm_opp_get_level(opp) - 1, fnum);
+		if (freq > fuse->max_freq)
+			fuse->max_freq = freq;
+		dev_pm_opp_put(opp);
+	}
+
+	/*
+	 * Get the quotient adjustment scaling factor, according to:
+	 *
+	 * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
+	 *		/ (freq(corner_N) - freq(corner_N-1)), max_factor)
+	 *
+	 * QUOT(corner_N):	quotient read from fuse for fuse corner N
+	 * QUOT(corner_N-1):	quotient read from fuse for fuse corner (N - 1)
+	 * freq(corner_N):	max frequency in MHz supported by fuse corner N
+	 * freq(corner_N-1):	max frequency in MHz supported by fuse corner
+	 *			 (N - 1)
+	 *
+	 * Then walk through the corners mapped to each fuse corner
+	 * and calculate the quotient adjustment for each one using the
+	 * following formula:
+	 *
+	 * quot_adjust = (freq_max - freq_corner) * scaling / 1000
+	 *
+	 * freq_max: max frequency in MHz supported by the fuse corner
+	 * freq_corner: frequency in MHz corresponding to the corner
+	 * scaling: calculated from above equation
+	 *
+	 *
+	 *     +                           +
+	 *     |                         v |
+	 *   q |           f c           o |           f c
+	 *   u |         c               l |         c
+	 *   o |       f                 t |       f
+	 *   t |     c                   a |     c
+	 *     | c f                     g | c f
+	 *     |                         e |
+	 *     +---------------            +----------------
+	 *       0 1 2 3 4 5 6               0 1 2 3 4 5 6
+	 *          corner                      corner
+	 *
+	 *    c = corner
+	 *    f = fuse corner
+	 *
+	 */
+	for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
+		fnum = cdata[i].fuse_corner;
+		fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
+		quot_offset = fuses[fnum].quotient_offset;
+		fuse = &drv->fuse_corners[fnum];
+		if (fnum)
+			prev_fuse = &drv->fuse_corners[fnum - 1];
+		else
+			prev_fuse = NULL;
+
+		corner->fuse_corner = fuse;
+		corner->freq = cdata[i].freq;
+		corner->uV = fuse->uV;
+
+		if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
+			scaling = cpr_calculate_scaling(quot_offset, drv,
+							fdata, corner);
+			if (scaling < 0)
+				return scaling;
+
+			apply_scaling = true;
+		} else if (corner->freq == fuse->max_freq) {
+			/* This is a fuse corner; don't scale anything */
+			apply_scaling = false;
+		}
+
+		if (apply_scaling) {
+			freq_diff = fuse->max_freq - corner->freq;
+			freq_diff_mhz = freq_diff / 1000000;
+			corner->quot_adjust = scaling * freq_diff_mhz / 1000;
+
+			corner->uV = cpr_interpolate(corner, step_volt, fdata);
+		}
+
+		corner->max_uV = fuse->max_uV;
+		corner->min_uV = fuse->min_uV;
+		corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
+		corner->last_uV = corner->uV;
+
+		/* Reduce the ceiling voltage if needed */
+		if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
+			corner->max_uV = corner->uV;
+		else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
+			corner->max_uV = max(corner->min_uV, fuse->uV);
+
+		dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
+			corner->min_uV, corner->uV, corner->max_uV,
+			fuse->quot - corner->quot_adjust);
+	}
+
+	return 0;
+}
+
+static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
+{
+	const struct cpr_desc *desc = drv->desc;
+	struct cpr_fuse *fuses;
+	int i;
+
+	fuses = devm_kzalloc(drv->dev,
+			     sizeof(struct cpr_fuse) * desc->num_fuse_corners,
+			     GFP_KERNEL);
+	if (!fuses)
+		return ERR_PTR(-ENOMEM);
+
+	for (i = 0; i < desc->num_fuse_corners; i++) {
+		char tbuf[32];
+
+		snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
+		fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
+		if (!fuses[i].ring_osc)
+			return ERR_PTR(-ENOMEM);
+
+		snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
+		fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
+						     GFP_KERNEL);
+		if (!fuses[i].init_voltage)
+			return ERR_PTR(-ENOMEM);
+
+		snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
+		fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
+		if (!fuses[i].quotient)
+			return ERR_PTR(-ENOMEM);
+
+		snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
+		fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
+							GFP_KERNEL);
+		if (!fuses[i].quotient_offset)
+			return ERR_PTR(-ENOMEM);
+	}
+
+	return fuses;
+}
+
+static int cpr_set_loop_allowed(struct cpr_drv *drv)
+{
+	drv->loop_disabled = false;
+
+	return 0;
+}
+
+static int cpr_init_parameters(struct cpr_drv *drv)
+{
+	struct device_node *of_node = drv->dev->of_node;
+	int ret;
+	struct clk *clk;
+
+	clk = clk_get(drv->dev, "ref");
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	drv->ref_clk_khz = clk_get_rate(clk) / 1000;
+	clk_put(clk);
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-timer-delay-us",
+				   &drv->timer_delay_us);
+	if (ret)
+		return ret;
+	ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-up",
+				   &drv->timer_cons_up);
+	if (ret)
+		return ret;
+	drv->timer_cons_up &= RBIF_TIMER_ADJ_CONS_UP_MASK;
+	ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-down",
+				   &drv->timer_cons_down);
+	if (ret)
+		return ret;
+	drv->timer_cons_down &= RBIF_TIMER_ADJ_CONS_DOWN_MASK;
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-up-threshold",
+				   &drv->up_threshold);
+	drv->up_threshold &= RBCPR_CTL_UP_THRESHOLD_MASK;
+	if (ret)
+		return ret;
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-down-threshold",
+				   &drv->down_threshold);
+	drv->down_threshold &= RBCPR_CTL_DN_THRESHOLD_MASK;
+	if (ret)
+		return ret;
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-idle-clocks",
+				   &drv->idle_clocks);
+	drv->idle_clocks &= RBCPR_STEP_QUOT_IDLE_CLK_MASK;
+	if (ret)
+		return ret;
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-gcnt-us", &drv->gcnt_us);
+	if (ret)
+		return ret;
+	ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-up-limit",
+				   &drv->vdd_apc_step_up_limit);
+	if (ret)
+		return ret;
+	ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-down-limit",
+				   &drv->vdd_apc_step_down_limit);
+	if (ret)
+		return ret;
+
+	ret = of_property_read_u32(of_node, "qcom,cpr-clamp-timer-interval",
+				   &drv->clamp_timer_interval);
+	if (ret && ret != -EINVAL)
+		return ret;
+
+	drv->clamp_timer_interval = min_t(unsigned int,
+					  drv->clamp_timer_interval,
+					  RBIF_TIMER_ADJ_CLAMP_INT_MASK);
+
+	dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
+		drv->up_threshold, drv->down_threshold);
+
+	return 0;
+}
+
+static int cpr_find_initial_corner(struct cpr_drv *drv)
+{
+	unsigned long rate;
+	const struct corner *end;
+	struct corner *iter;
+	int i = 0;
+
+	if (IS_ERR_OR_NULL(drv->cpu_clk)) {
+		dev_err(drv->dev, "cpu clk is not set\n");
+		return -EINVAL;
+	}
+
+	end = &drv->corners[drv->num_corners - 1];
+	rate = clk_get_rate(drv->cpu_clk);
+
+	for (iter = drv->corners; iter <= end; iter++) {
+		if (iter->freq > rate)
+			break;
+		i++;
+		if (iter->freq == rate) {
+			drv->corner = iter;
+			drv->performance_state = i;
+			break;
+		}
+		if (iter->freq < rate) {
+			drv->corner = iter;
+			drv->performance_state = i;
+		}
+	}
+
+	if (!drv->corner) {
+		dev_err(drv->dev, "boot up corner not found\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(drv->dev, "boot up perf state: %d\n", i);
+
+	return 0;
+}
+
+static const struct cpr_desc qcs404_cpr_desc = {
+	.num_fuse_corners = 3,
+	.min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
+	.step_quot = (int []){ 25, 25, 25, },
+	.cpr_fuses = {
+		.init_voltage_step = 8000,
+		.init_voltage_width = 6,
+		.fuse_corner_data = (struct fuse_corner_data[]){
+			/* fuse corner 0 */
+			{
+				.ref_uV = 1224000,
+				.max_uV = 1224000,
+				.min_uV = 1048000,
+				.max_volt_scale = 0,
+				.max_quot_scale = 0,
+				.quot_offset = 0,
+				.quot_scale = 1,
+				.quot_adjust = 0,
+				.quot_offset_scale = 5,
+				.quot_offset_adjust = 0,
+			},
+			/* fuse corner 1 */
+			{
+				.ref_uV = 1288000,
+				.max_uV = 1288000,
+				.min_uV = 1048000,
+				.max_volt_scale = 2000,
+				.max_quot_scale = 1400,
+				.quot_offset = 0,
+				.quot_scale = 1,
+				.quot_adjust = -20,
+				.quot_offset_scale = 5,
+				.quot_offset_adjust = 0,
+			},
+			/* fuse corner 2 */
+			{
+				.ref_uV = 1352000,
+				.max_uV = 1384000,
+				.min_uV = 1088000,
+				.max_volt_scale = 2000,
+				.max_quot_scale = 1400,
+				.quot_offset = 0,
+				.quot_scale = 1,
+				.quot_adjust = 0,
+				.quot_offset_scale = 5,
+				.quot_offset_adjust = 0,
+			},
+		},
+	},
+};
+
+static const struct acc_desc qcs404_acc_desc = {
+	.settings = (struct reg_sequence[]){
+		{ 0xb120, 0x1041040 },
+		{ 0xb124, 0x41 },
+		{ 0xb120, 0x0 },
+		{ 0xb124, 0x0 },
+		{ 0xb120, 0x0 },
+		{ 0xb124, 0x0 },
+	},
+	.config = (struct reg_sequence[]){
+		{ 0xb138, 0xff },
+		{ 0xb130, 0x5555 },
+	},
+	.num_regs_per_fuse = 2,
+};
+
+static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
+	.cpr_desc = &qcs404_cpr_desc,
+	.acc_desc = &qcs404_acc_desc,
+};
+
+static unsigned int cpr_get_performance(struct generic_pm_domain *genpd,
+					struct dev_pm_opp *opp)
+{
+	return dev_pm_opp_get_level(opp);
+}
+
+static int cpr_power_off(struct generic_pm_domain *domain)
+{
+	struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+
+	return cpr_disable(drv);
+}
+
+static int cpr_power_on(struct generic_pm_domain *domain)
+{
+	struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+
+	return cpr_enable(drv);
+}
+
+static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
+			     struct device *dev)
+{
+	struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
+	const struct acc_desc *acc_desc = drv->acc_desc;
+	size_t len;
+	int ret;
+
+	dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
+
+	if (!drv->cpu_clk) {
+		drv->cpu_clk = devm_clk_get(dev, NULL);
+		if (IS_ERR_OR_NULL(drv->cpu_clk)) {
+			dev_err(drv->dev, "could not get cpu clk\n");
+			return -EINVAL;
+		}
+
+		dev_dbg(drv->dev, "using cpu clk from: %s\n", dev_name(dev));
+
+		/* Everything related to (virtual) corners has to be initialized
+		 * here, when attaching to the power domain, since it depends on
+		 * the power domain's OPP table, which isn't available earlier.
+		 */
+		drv->num_corners = dev_pm_opp_get_opp_count(&drv->pd.dev);
+		if (drv->num_corners < 0)
+			return drv->num_corners;
+		if (drv->num_corners < 2) {
+			dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
+			return -EINVAL;
+		}
+
+		dev_dbg(drv->dev, "number of OPPs: %d\n", drv->num_corners);
+
+		len = sizeof(*drv->corners) * drv->num_corners;
+		drv->corners = devm_kzalloc(dev, len, GFP_KERNEL);
+		if (!drv->corners)
+			return -ENOMEM;
+
+		ret = cpr_corner_init(drv);
+		if (ret)
+			return ret;
+
+		ret = cpr_set_loop_allowed(drv);
+		if (ret)
+			return ret;
+
+		ret = cpr_init_parameters(drv);
+		if (ret)
+			return ret;
+
+		/* Configure CPR HW but keep it disabled */
+		ret = cpr_config(drv);
+		if (ret)
+			return ret;
+
+		ret = cpr_find_initial_corner(drv);
+		if (ret)
+			return ret;
+
+		if (acc_desc->config)
+			regmap_multi_reg_write(drv->tcsr, acc_desc->config,
+					       acc_desc->num_regs_per_fuse);
+
+		/* Enable ACC if required */
+		if (acc_desc->enable_mask)
+			regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
+					   acc_desc->enable_mask,
+					   acc_desc->enable_mask);
+	}
+
+	return 0;
+}
+
+static int cpr_debug_info_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+
+	return 0;
+}
+
+static ssize_t cpr_debug_info_read(struct file *file, char __user *buff,
+				   size_t count, loff_t *ppos)
+{
+	u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
+	u32 step_dn, step_up, error, error_lt0, busy;
+	struct cpr_drv *drv = file->private_data;
+	struct fuse_corner *fuse_corner;
+	struct corner *corner;
+	ssize_t len, ret = 0;
+	char *debugfs_buf;
+
+	debugfs_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!debugfs_buf)
+		return -ENOMEM;
+
+	mutex_lock(&drv->lock);
+
+	corner = drv->corner;
+	fuse_corner = corner->fuse_corner;
+
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "corner, current_volt = %d uV\n",
+		       corner->last_uV);
+	ret += len;
+
+	ro_sel = fuse_corner->ring_osc_idx;
+	gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "rbcpr_gcnt_target (%u) = 0x%02X\n", ro_sel, gcnt);
+	ret += len;
+
+	ctl = cpr_read(drv, REG_RBCPR_CTL);
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "rbcpr_ctl = 0x%02X\n", ctl);
+	ret += len;
+
+	irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "rbcpr_irq_status = 0x%02X\n", irq_status);
+	ret += len;
+
+	reg = cpr_read(drv, REG_RBCPR_RESULT_0);
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "rbcpr_result_0 = 0x%02X\n", reg);
+	ret += len;
+
+	step_dn = reg & 0x01;
+	step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       "  [step_dn = %u", step_dn);
+	ret += len;
+
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       ", step_up = %u", step_up);
+	ret += len;
+
+	error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
+				& RBCPR_RESULT0_ERROR_STEPS_MASK;
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       ", error_steps = %u", error_steps);
+	ret += len;
+
+	error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       ", error = %u", error);
+	ret += len;
+
+	error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       ", error_lt_0 = %u", error_lt0);
+	ret += len;
+
+	busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
+	len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
+		       ", busy = %u]\n", busy);
+	ret += len;
+	mutex_unlock(&drv->lock);
+
+	ret = simple_read_from_buffer(buff, count, ppos, debugfs_buf, ret);
+	kfree(debugfs_buf);
+	return ret;
+}
+
+static const struct file_operations cpr_debug_info_fops = {
+	.open = cpr_debug_info_open,
+	.read = cpr_debug_info_read,
+};
+
+static void cpr_debugfs_init(struct cpr_drv *drv)
+{
+	drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
+
+	debugfs_create_file("debug_info", 0444, drv->debugfs,
+			    drv, &cpr_debug_info_fops);
+}
+
+static int cpr_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	struct cpr_drv *drv;
+	size_t len;
+	int irq, ret;
+	const struct cpr_acc_desc *data;
+	struct device_node *np;
+	u32 cpr_rev = FUSE_REVISION_UNKNOWN;
+
+	data = of_device_get_match_data(dev);
+	if (!data || !data->cpr_desc || !data->acc_desc)
+		return -EINVAL;
+
+	drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+	if (!drv)
+		return -ENOMEM;
+	drv->dev = dev;
+	drv->desc = data->cpr_desc;
+	drv->acc_desc = data->acc_desc;
+
+	len = sizeof(*drv->fuse_corners) * drv->desc->num_fuse_corners;
+	drv->fuse_corners = devm_kzalloc(dev, len, GFP_KERNEL);
+	if (!drv->fuse_corners)
+		return -ENOMEM;
+
+	np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
+	if (!np)
+		return -ENODEV;
+
+	drv->tcsr = syscon_node_to_regmap(np);
+	of_node_put(np);
+	if (IS_ERR(drv->tcsr))
+		return PTR_ERR(drv->tcsr);
+
+	mutex_init(&drv->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	drv->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(drv->base))
+		return PTR_ERR(drv->base);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -EINVAL;
+
+	drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
+	if (IS_ERR(drv->vdd_apc))
+		return PTR_ERR(drv->vdd_apc);
+
+	/* Initialize fuse corners, since it simply depends
+	 * on data in efuses.
+	 * Everything related to (virtual) corners has to be
+	 * initialized after attaching to the power domain,
+	 * since is depends on the OPP table.
+	 */
+	ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
+	if (ret)
+		return ret;
+
+	drv->cpr_fuses = cpr_get_fuses(drv);
+	if (IS_ERR(drv->cpr_fuses))
+		return PTR_ERR(drv->cpr_fuses);
+
+	ret = cpr_populate_ring_osc_idx(drv);
+	if (ret)
+		return ret;
+
+	ret = cpr_fuse_corner_init(drv);
+	if (ret)
+		return ret;
+
+	ret = devm_request_threaded_irq(dev, irq, NULL,
+					cpr_irq_handler,
+					IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+					"cpr", drv);
+	if (ret)
+		return ret;
+
+	drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
+					  GFP_KERNEL);
+	if (!drv->pd.name)
+		return -EINVAL;
+
+	drv->pd.power_off = cpr_power_off;
+	drv->pd.power_on = cpr_power_on;
+	drv->pd.set_performance_state = cpr_set_performance;
+	drv->pd.opp_to_performance_state = cpr_get_performance;
+	drv->pd.attach_dev = cpr_pd_attach_dev;
+
+	ret = pm_genpd_init(&drv->pd, NULL, true);
+	if (ret)
+		return ret;
+
+	ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, drv);
+	cpr_debugfs_init(drv);
+
+	return 0;
+}
+
+static int cpr_remove(struct platform_device *pdev)
+{
+	struct cpr_drv *drv = platform_get_drvdata(pdev);
+
+	if (cpr_is_allowed(drv)) {
+		cpr_ctl_disable(drv);
+		cpr_irq_set(drv, 0);
+	}
+
+	of_genpd_del_provider(pdev->dev.of_node);
+	pm_genpd_remove(&drv->pd);
+
+	debugfs_remove_recursive(drv->debugfs);
+
+	return 0;
+}
+
+static const struct of_device_id cpr_match_table[] = {
+	{ .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, cpr_match_table);
+
+static struct platform_driver cpr_driver = {
+	.probe		= cpr_probe,
+	.remove		= cpr_remove,
+	.driver		= {
+		.name	= "qcom-cpr",
+		.of_match_table = cpr_match_table,
+		.pm = &cpr_pm_ops,
+	},
+};
+module_platform_driver(cpr_driver);
+
+MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-cpr");
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 12/14] arm64: dts: qcom: qcs404: Add CPR and populate OPP table
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (10 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 11/14] " Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 13/14] arm64: defconfig: enable CONFIG_QCOM_CPR Niklas Cassel
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: Andy Gross
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, Rob Herring,
	Mark Rutland, devicetree, linux-kernel

Add CPR and populate OPP table.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
Changes since V1:
-Removed opp-hz from CPR OPP table.

 arch/arm64/boot/dts/qcom/qcs404.dtsi | 142 +++++++++++++++++++++++++--
 1 file changed, 134 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ff9198740431..5519422b762d 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -38,7 +38,8 @@
 			#cooling-cells = <2>;
 			clocks = <&apcs_glb>;
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&pms405_s3>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
 		};
 
 		CPU1: cpu@101 {
@@ -51,7 +52,8 @@
 			#cooling-cells = <2>;
 			clocks = <&apcs_glb>;
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&pms405_s3>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
 		};
 
 		CPU2: cpu@102 {
@@ -64,7 +66,8 @@
 			#cooling-cells = <2>;
 			clocks = <&apcs_glb>;
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&pms405_s3>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
 		};
 
 		CPU3: cpu@103 {
@@ -77,7 +80,8 @@
 			#cooling-cells = <2>;
 			clocks = <&apcs_glb>;
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&pms405_s3>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
 		};
 
 		L2_0: l2-cache {
@@ -101,20 +105,37 @@
 	};
 
 	cpu_opp_table: cpu-opp-table {
-		compatible = "operating-points-v2";
+		compatible = "operating-points-v2-kryo-cpu";
 		opp-shared;
 
 		opp-1094400000 {
 			opp-hz = /bits/ 64 <1094400000>;
-			opp-microvolt = <1224000 1224000 1224000>;
+			required-opps = <&cpr_opp1>;
 		};
 		opp-1248000000 {
 			opp-hz = /bits/ 64 <1248000000>;
-			opp-microvolt = <1288000 1288000 1288000>;
+			required-opps = <&cpr_opp2>;
 		};
 		opp-1401600000 {
 			opp-hz = /bits/ 64 <1401600000>;
-			opp-microvolt = <1384000 1384000 1384000>;
+			required-opps = <&cpr_opp3>;
+		};
+	};
+
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			qcom,opp-fuse-level = <3>;
 		};
 	};
 
@@ -294,6 +315,62 @@
 			tsens_caldata: caldata@d0 {
 				reg = <0x1f8 0x14>;
 			};
+			cpr_efuse_speedbin: speedbin@13c {
+				reg = <0x13c 0x4>;
+				bits = <2 3>;
+			};
+			cpr_efuse_quot_offset1: qoffset1@231 {
+				reg = <0x231 0x4>;
+				bits = <4 7>;
+			};
+			cpr_efuse_quot_offset2: qoffset2@232 {
+				reg = <0x232 0x4>;
+				bits = <3 7>;
+			};
+			cpr_efuse_quot_offset3: qoffset3@233 {
+				reg = <0x233 0x4>;
+				bits = <2 7>;
+			};
+			cpr_efuse_init_voltage1: ivoltage1@229 {
+				reg = <0x229 0x4>;
+				bits = <4 6>;
+			};
+			cpr_efuse_init_voltage2: ivoltage2@22a {
+				reg = <0x22a 0x4>;
+				bits = <2 6>;
+			};
+			cpr_efuse_init_voltage3: ivoltage3@22b {
+				reg = <0x22b 0x4>;
+				bits = <0 6>;
+			};
+			cpr_efuse_quot1: quot1@22b {
+				reg = <0x22b 0x4>;
+				bits = <6 12>;
+			};
+			cpr_efuse_quot2: quot2@22d {
+				reg = <0x22d 0x4>;
+				bits = <2 12>;
+			};
+			cpr_efuse_quot3: quot3@230 {
+				reg = <0x230 0x4>;
+				bits = <0 12>;
+			};
+			cpr_efuse_ring1: ring1@228 {
+				reg = <0x228 0x4>;
+				bits = <0 3>;
+			};
+			cpr_efuse_ring2: ring2@228 {
+				reg = <0x228 0x4>;
+				bits = <4 3>;
+			};
+			cpr_efuse_ring3: ring3@229 {
+				reg = <0x229 0x4>;
+				bits = <0 3>;
+			};
+			cpr_efuse_revision: revision@218 {
+				reg = <0x218 0x4>;
+				bits = <3 3>;
+			};
 		};
 
 		rng: rng@e3000 {
@@ -901,6 +978,55 @@
 			clock-names = "xo";
 		};
 
+		cprpd: cpr@b018000 {
+			compatible = "qcom,qcs404-cpr", "qcom,cpr";
+			reg = <0x0b018000 0x1000>;
+			interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&xo_board>;
+			clock-names = "ref";
+			vdd-apc-supply = <&pms405_s3>;
+			#power-domain-cells = <0>;
+			operating-points-v2 = <&cpr_opp_table>;
+			acc-syscon = <&tcsr>;
+
+			nvmem-cells = <&cpr_efuse_quot_offset1>,
+				<&cpr_efuse_quot_offset2>,
+				<&cpr_efuse_quot_offset3>,
+				<&cpr_efuse_init_voltage1>,
+				<&cpr_efuse_init_voltage2>,
+				<&cpr_efuse_init_voltage3>,
+				<&cpr_efuse_quot1>,
+				<&cpr_efuse_quot2>,
+				<&cpr_efuse_quot3>,
+				<&cpr_efuse_ring1>,
+				<&cpr_efuse_ring2>,
+				<&cpr_efuse_ring3>,
+				<&cpr_efuse_revision>;
+			nvmem-cell-names = "cpr_quotient_offset1",
+				"cpr_quotient_offset2",
+				"cpr_quotient_offset3",
+				"cpr_init_voltage1",
+				"cpr_init_voltage2",
+				"cpr_init_voltage3",
+				"cpr_quotient1",
+				"cpr_quotient2",
+				"cpr_quotient3",
+				"cpr_ring_osc1",
+				"cpr_ring_osc2",
+				"cpr_ring_osc3",
+				"cpr_fuse_revision";
+
+			qcom,cpr-timer-delay-us = <5000>;
+			qcom,cpr-timer-cons-up = <0>;
+			qcom,cpr-timer-cons-down = <2>;
+			qcom,cpr-up-threshold = <1>;
+			qcom,cpr-down-threshold = <3>;
+			qcom,cpr-idle-clocks = <15>;
+			qcom,cpr-gcnt-us = <1>;
+			qcom,vdd-apc-step-up-limit = <1>;
+			qcom,vdd-apc-step-down-limit = <1>;
+		};
+
 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 13/14] arm64: defconfig: enable CONFIG_QCOM_CPR
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (11 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 12/14] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-25 10:41 ` [PATCH v2 14/14] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM Niklas Cassel
  2019-07-26  8:08 ` [PATCH v2 00/14] Add support for QCOM Core Power Reduction Viresh Kumar
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: linux-kernel
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, Catalin Marinas,
	Will Deacon, linux-arm-kernel

Enable CONFIG_QCOM_CPR.

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 04b7fb26a942..3e7618818250 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -420,6 +420,7 @@ CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_MAX77620=y
 CONFIG_POWER_AVS=y
 CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_QCOM_CPR=y
 CONFIG_POWER_RESET_MSM=y
 CONFIG_POWER_RESET_XGENE=y
 CONFIG_POWER_RESET_SYSCON=y
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v2 14/14] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (12 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 13/14] arm64: defconfig: enable CONFIG_QCOM_CPR Niklas Cassel
@ 2019-07-25 10:41 ` Niklas Cassel
  2019-07-26  8:08 ` [PATCH v2 00/14] Add support for QCOM Core Power Reduction Viresh Kumar
  14 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-07-25 10:41 UTC (permalink / raw)
  To: linux-kernel
  Cc: linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, Niklas Cassel, Catalin Marinas,
	Will Deacon, linux-arm-kernel

Enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM.

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 3e7618818250..9b0cc49f5fe8 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -84,6 +84,7 @@ CONFIG_ACPI_CPPC_CPUFREQ=m
 CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
 CONFIG_ARM_SCPI_CPUFREQ=y
 CONFIG_ARM_IMX_CPUFREQ_DT=m
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
 CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
 CONFIG_ARM_TEGRA186_CPUFREQ=y
 CONFIG_ARM_SCPI_PROTOCOL=y
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact()
  2019-07-25 10:41 ` [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Niklas Cassel
@ 2019-07-26  8:03   ` Viresh Kumar
  0 siblings, 0 replies; 31+ messages in thread
From: Viresh Kumar @ 2019-07-26  8:03 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Viresh Kumar, Nishanth Menon, Stephen Boyd, Rafael J. Wysocki,
	linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	linux-pm, linux-kernel

On 25-07-19, 12:41, Niklas Cassel wrote:
> When using performance states, there is usually not any opp-hz property
> specified, so the dev_pm_opp_find_freq_exact() function cannot be used.

Removed above two lines while applying.

> Since the performance states in the OPP table are unique, implement a
> dev_pm_opp_find_level_exact() in order to be able to fetch a specific OPP.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> ---
>  drivers/opp/core.c     | 48 ++++++++++++++++++++++++++++++++++++++++++
>  include/linux/pm_opp.h |  8 +++++++
>  2 files changed, 56 insertions(+)

-- 
viresh

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2019-07-25 10:41 ` [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Niklas Cassel
@ 2019-07-26  8:04   ` Viresh Kumar
  0 siblings, 0 replies; 31+ messages in thread
From: Viresh Kumar @ 2019-07-26  8:04 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Viresh Kumar, Nishanth Menon, Stephen Boyd, Andy Gross, Ilia Lin,
	linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Sricharan R, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

$subject of this and few more binding patches updated to:

"dt-bindings: opp: XXX"

On 25-07-19, 12:41, Niklas Cassel wrote:
> From: Sricharan R <sricharan@codeaurora.org>
> 
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the read data,
> rest of the driver is same for both the cases. So pull the common things
> out for reuse.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> [niklas.cassel@linaro.org: split dt-binding into a separate patch and
> do not rename the compatible string.]
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> Changes since V1:
> -Picked up tags.

-- 
viresh

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 00/14] Add support for QCOM Core Power Reduction
  2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
                   ` (13 preceding siblings ...)
  2019-07-25 10:41 ` [PATCH v2 14/14] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM Niklas Cassel
@ 2019-07-26  8:08 ` Viresh Kumar
  14 siblings, 0 replies; 31+ messages in thread
From: Viresh Kumar @ 2019-07-26  8:08 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: linux-pm, linux-arm-msm, jorge.ramirez-ortiz, sboyd, vireshk,
	bjorn.andersson, ulf.hansson, devicetree, linux-kernel,
	linux-arm-kernel

On 25-07-19, 12:41, Niklas Cassel wrote:
> This series adds support for Core Power Reduction (CPR), a form of
> Adaptive Voltage Scaling (AVS), found on certain Qualcomm SoCs.
> 
> This series is based on top of the qcs404 cpufreq patch series that
> hasn't landed yet:
> https://patchwork.kernel.org/project/linux-arm-msm/list/?series=137809
> 
> CPR is a technology that reduces core power on a CPU or on other device.
> It reads voltage settings from efuses (that have been written in
> production), it uses these voltage settings as initial values, for each
> OPP.
> 
> After moving to a certain OPP, CPR monitors dynamic factors such as
> temperature, etc. and adjusts the voltage for that frequency accordingly
> to save power and meet silicon characteristic requirements.
> 
> This driver has been developed together with Jorge Ramirez-Ortiz, and
> is based on an RFC by Stephen Boyd[1], which in turn is based on work
> by others on codeaurora.org[2].
> 
> [1] https://lkml.org/lkml/2015/9/18/833
> [2] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/cpr-regulator.c?h=msm-3.10
> 
> Changes since V1:
> Added a new patch implementing dev_pm_opp_find_level_exact() in order to
> make the CPR OPP table in device tree cleaner.
> For more detailed changes, check the "Changes since V1" as comments in
> the individual patches, where applicable.

Applied patches [1-9/14] to cpufreq and OPP trees and done some
reordering as well to keep all binding patches together.

Rob's Ack is missing on two of the binding patches and I will add them
later once he provides it.

Everything should be available here for you to base rest of the stuff.

git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git cpufreq/arm/linux-next

-- 
viresh

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-07-25 10:41 ` [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Niklas Cassel
@ 2019-08-16 21:21   ` Rob Herring
  2019-08-19 10:09   ` [PATCH v3 " Niklas Cassel
  1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2019-08-16 21:21 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Andy Gross, Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd,
	linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Mark Rutland, linux-pm, devicetree, linux-kernel

On Thu, 25 Jul 2019 12:41:34 +0200, Niklas Cassel wrote:
> Some Qualcomm SoCs have support for Core Power Reduction (CPR).
> On these platforms, we need to attach to the power domain provider
> providing the performance states, so that the leaky device (the CPU)
> can configure the performance states (which represent different
> CPU clock frequencies).
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> ---
>  .../bindings/opp/qcom-nvmem-cpufreq.txt       | 111 ++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction)
  2019-07-25 10:41 ` [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Niklas Cassel
@ 2019-08-17  6:14   ` Stephen Boyd
  2019-08-22 10:20     ` Niklas Cassel
  0 siblings, 1 reply; 31+ messages in thread
From: Stephen Boyd @ 2019-08-17  6:14 UTC (permalink / raw)
  To: Jorge Ramirez-Ortiz, Niklas Cassel
  Cc: linux-arm-msm, vireshk, bjorn.andersson, ulf.hansson,
	Rob Herring, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Quoting Niklas Cassel (2019-07-25 03:41:38)
> +       cpr@b018000 {
> +               compatible = "qcom,qcs404-cpr", "qcom,cpr";
> +               reg = <0x0b018000 0x1000>;
> +               interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> +               clocks = <&xo_board>;
> +               clock-names = "ref";
> +               vdd-apc-supply = <&pms405_s3>;
> +               #power-domain-cells = <0>;
> +               operating-points-v2 = <&cpr_opp_table>;
> +               acc-syscon = <&tcsr>;
> +
> +               nvmem-cells = <&cpr_efuse_quot_offset1>,
> +                       <&cpr_efuse_quot_offset2>,
> +                       <&cpr_efuse_quot_offset3>,
> +                       <&cpr_efuse_init_voltage1>,
> +                       <&cpr_efuse_init_voltage2>,
> +                       <&cpr_efuse_init_voltage3>,
> +                       <&cpr_efuse_quot1>,
> +                       <&cpr_efuse_quot2>,
> +                       <&cpr_efuse_quot3>,
> +                       <&cpr_efuse_ring1>,
> +                       <&cpr_efuse_ring2>,
> +                       <&cpr_efuse_ring3>,
> +                       <&cpr_efuse_revision>;
> +               nvmem-cell-names = "cpr_quotient_offset1",
> +                       "cpr_quotient_offset2",
> +                       "cpr_quotient_offset3",
> +                       "cpr_init_voltage1",
> +                       "cpr_init_voltage2",
> +                       "cpr_init_voltage3",
> +                       "cpr_quotient1",
> +                       "cpr_quotient2",
> +                       "cpr_quotient3",
> +                       "cpr_ring_osc1",
> +                       "cpr_ring_osc2",
> +                       "cpr_ring_osc3",
> +                       "cpr_fuse_revision";
> +
> +               qcom,cpr-timer-delay-us = <5000>;
> +               qcom,cpr-timer-cons-up = <0>;
> +               qcom,cpr-timer-cons-down = <2>;
> +               qcom,cpr-up-threshold = <1>;
> +               qcom,cpr-down-threshold = <3>;
> +               qcom,cpr-idle-clocks = <15>;
> +               qcom,cpr-gcnt-us = <1>;
> +               qcom,vdd-apc-step-up-limit = <1>;
> +               qcom,vdd-apc-step-down-limit = <1>;

Are any of these qcom,* properties going to change for a particular SoC?
They look like SoC config data that should just go into the driver and
change based on the SoC compatible string.


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 11/14] power: avs: Add support for CPR (Core Power Reduction)
  2019-07-25 10:41 ` [PATCH v2 11/14] " Niklas Cassel
@ 2019-08-18  1:04   ` Stephen Boyd
  0 siblings, 0 replies; 31+ messages in thread
From: Stephen Boyd @ 2019-08-18  1:04 UTC (permalink / raw)
  To: Andy Gross, Jorge Ramirez-Ortiz, Kevin Hilman, Niklas Cassel,
	Nishanth Menon
  Cc: linux-arm-msm, vireshk, bjorn.andersson, ulf.hansson,
	linux-kernel, linux-pm

Quoting Niklas Cassel (2019-07-25 03:41:39)
> diff --git a/drivers/power/avs/Kconfig b/drivers/power/avs/Kconfig
> index b5a217b828dc..4d4d742b3c6f 100644
> --- a/drivers/power/avs/Kconfig
> +++ b/drivers/power/avs/Kconfig
> @@ -12,6 +12,21 @@ menuconfig POWER_AVS
>  
>           Say Y here to enable Adaptive Voltage Scaling class support.
>  
> +config QCOM_CPR
> +       tristate "QCOM Core Power Reduction (CPR) support"
> +       depends on POWER_AVS
> +       select PM_OPP
> +       help
> +         Say Y here to enable support for the CPR hardware found on Qualcomm
> +         SoCs like MSM8916.

Maybe mention qcs404 too, because it looks like 8916 isn't actually here
:)

> +
> +         This driver populates CPU OPPs tables and makes adjustments to the
> +         tables based on feedback from the CPR hardware. If you want to do
> +         CPUfrequency scaling say Y here.
> +
> +         To compile this driver as a module, choose M here: the module will
> +         be called qcom-cpr
> +
>  config ROCKCHIP_IODOMAIN
>          tristate "Rockchip IO domain support"
>          depends on POWER_AVS && ARCH_ROCKCHIP && OF
> diff --git a/drivers/power/avs/Makefile b/drivers/power/avs/Makefile
> index a1b8cd453f19..8cd17e6660ee 100644
> --- a/drivers/power/avs/Makefile
> +++ b/drivers/power/avs/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  obj-$(CONFIG_POWER_AVS_OMAP)           += smartreflex.o
>  obj-$(CONFIG_ROCKCHIP_IODOMAIN)                += rockchip-io-domain.o
> +obj-$(CONFIG_QCOM_CPR)                 += qcom-cpr.o

Try to make this alphabetical on config name?

> diff --git a/drivers/power/avs/qcom-cpr.c b/drivers/power/avs/qcom-cpr.c
> new file mode 100644
> index 000000000000..d6bce2832589
> --- /dev/null
> +++ b/drivers/power/avs/qcom-cpr.c
> @@ -0,0 +1,1885 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2019, Linaro Limited
> + */
> +
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/debugfs.h>
> +#include <linux/string.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/bitops.h>
> +#include <linux/slab.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_opp.h>
> +#include <linux/interrupt.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/clk.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/bitops.h>
> +
> +/* Register Offsets for RB-CPR and Bit Definitions */
> +
> +/* RBCPR Version Register */
> +#define REG_RBCPR_VERSION              0
> +#define RBCPR_VER_2                    0x02
> +#define FLAGS_IGNORE_1ST_IRQ_STATUS    BIT(0)
> +
> +/* RBCPR Gate Count and Target Registers */
> +#define REG_RBCPR_GCNT_TARGET(n)       (0x60 + 4 * (n))
> +
> +#define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
> +#define RBCPR_GCNT_TARGET_TARGET_MASK  GENMASK(11, 0)
> +#define RBCPR_GCNT_TARGET_GCNT_SHIFT   12
> +#define RBCPR_GCNT_TARGET_GCNT_MASK    GENMASK(9, 0)
> +
> +/* RBCPR Timer Control */
> +#define REG_RBCPR_TIMER_INTERVAL       0x44
> +#define REG_RBIF_TIMER_ADJUST          0x4c
> +
> +#define RBIF_TIMER_ADJ_CONS_UP_MASK    GENMASK(3, 0)
> +#define RBIF_TIMER_ADJ_CONS_UP_SHIFT   0
> +#define RBIF_TIMER_ADJ_CONS_DOWN_MASK  GENMASK(3, 0)
> +#define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
> +#define RBIF_TIMER_ADJ_CLAMP_INT_MASK  GENMASK(7, 0)
> +#define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
> +
> +/* RBCPR Config Register */
> +#define REG_RBIF_LIMIT                 0x48
> +#define RBIF_LIMIT_CEILING_MASK                GENMASK(5, 0)
> +#define RBIF_LIMIT_CEILING_SHIFT       6
> +#define RBIF_LIMIT_FLOOR_BITS          6
> +#define RBIF_LIMIT_FLOOR_MASK          GENMASK(5, 0)
> +
> +#define RBIF_LIMIT_CEILING_DEFAULT     RBIF_LIMIT_CEILING_MASK
> +#define RBIF_LIMIT_FLOOR_DEFAULT       0
> +
> +#define REG_RBIF_SW_VLEVEL             0x94
> +#define RBIF_SW_VLEVEL_DEFAULT         0x20
> +
> +#define REG_RBCPR_STEP_QUOT            0x80
> +#define RBCPR_STEP_QUOT_STEPQUOT_MASK  GENMASK(7, 0)
> +#define RBCPR_STEP_QUOT_IDLE_CLK_MASK  GENMASK(3, 0)
> +#define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
> +
> +/* RBCPR Control Register */
> +#define REG_RBCPR_CTL                  0x90
> +
> +#define RBCPR_CTL_LOOP_EN                      BIT(0)
> +#define RBCPR_CTL_TIMER_EN                     BIT(3)
> +#define RBCPR_CTL_SW_AUTO_CONT_ACK_EN          BIT(5)
> +#define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN      BIT(6)
> +#define RBCPR_CTL_COUNT_MODE                   BIT(10)
> +#define RBCPR_CTL_UP_THRESHOLD_MASK    GENMASK(3, 0)
> +#define RBCPR_CTL_UP_THRESHOLD_SHIFT   24
> +#define RBCPR_CTL_DN_THRESHOLD_MASK    GENMASK(3, 0)
> +#define RBCPR_CTL_DN_THRESHOLD_SHIFT   28
> +
> +/* RBCPR Ack/Nack Response */
> +#define REG_RBIF_CONT_ACK_CMD          0x98
> +#define REG_RBIF_CONT_NACK_CMD         0x9c
> +
> +/* RBCPR Result status Register */
> +#define REG_RBCPR_RESULT_0             0xa0
> +
> +#define RBCPR_RESULT0_BUSY_SHIFT       19
> +#define RBCPR_RESULT0_BUSY_MASK                BIT(RBCPR_RESULT0_BUSY_SHIFT)
> +#define RBCPR_RESULT0_ERROR_LT0_SHIFT  18
> +#define RBCPR_RESULT0_ERROR_SHIFT      6
> +#define RBCPR_RESULT0_ERROR_MASK       GENMASK(11, 0)
> +#define RBCPR_RESULT0_ERROR_STEPS_SHIFT        2
> +#define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
> +#define RBCPR_RESULT0_STEP_UP_SHIFT    1
> +
> +/* RBCPR Interrupt Control Register */
> +#define REG_RBIF_IRQ_EN(n)             (0x100 + 4 * (n))
> +#define REG_RBIF_IRQ_CLEAR             0x110
> +#define REG_RBIF_IRQ_STATUS            0x114
> +
> +#define CPR_INT_DONE           BIT(0)
> +#define CPR_INT_MIN            BIT(1)
> +#define CPR_INT_DOWN           BIT(2)
> +#define CPR_INT_MID            BIT(3)
> +#define CPR_INT_UP             BIT(4)
> +#define CPR_INT_MAX            BIT(5)
> +#define CPR_INT_CLAMP          BIT(6)
> +#define CPR_INT_ALL    (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
> +                       CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
> +#define CPR_INT_DEFAULT        (CPR_INT_UP | CPR_INT_DOWN)
> +
> +#define CPR_NUM_RING_OSC       8
> +
> +/* CPR eFuse parameters */
> +#define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
> +
> +#define CPR_FUSE_MIN_QUOT_DIFF         50
> +
> +#define FUSE_REVISION_UNKNOWN          (-1)
> +
> +enum voltage_change_dir {
> +       NO_CHANGE,
> +       DOWN,
> +       UP,
> +};
> +
> +struct cpr_fuse {
> +       char *ring_osc;
> +       char *init_voltage;
> +       char *quotient;
> +       char *quotient_offset;
> +};
> +
> +struct fuse_corner_data {
> +       int ref_uV;
> +       int max_uV;
> +       int min_uV;
> +       int max_volt_scale;
> +       int max_quot_scale;
> +       /* fuse quot */
> +       int quot_offset;
> +       int quot_scale;
> +       int quot_adjust;
> +       /* fuse quot_offset */
> +       int quot_offset_scale;
> +       int quot_offset_adjust;
> +};
> +
> +struct cpr_fuses {
> +       int init_voltage_step;
> +       int init_voltage_width;
> +       struct fuse_corner_data *fuse_corner_data;
> +};
> +
> +struct pvs_bin {

Why does this struct exist?

> +       int *uV;
> +};
> +
> +struct pvs_fuses {
> +       char **pvs_fuse;
> +       struct pvs_bin *pvs_bins;

This can be int **pvs_bins?

> +};
> +
> +struct corner_data {
> +       unsigned int fuse_corner;
> +       unsigned long freq;
> +};
> +
> +struct cpr_desc {
> +       unsigned int num_fuse_corners;
> +       int min_diff_quot;
> +       int *step_quot;
> +       struct cpr_fuses cpr_fuses;
> +       struct pvs_fuses *pvs_fuses;
> +       bool reduce_to_fuse_uV;
> +       bool reduce_to_corner_uV;
> +};
> +
> +struct acc_desc {
> +       unsigned int    enable_reg;
> +       u32             enable_mask;
> +
> +       struct reg_sequence     *config;
> +       struct reg_sequence     *settings;
> +       int                     num_regs_per_fuse;
> +};
> +
> +struct cpr_acc_desc {
> +       const struct cpr_desc *cpr_desc;
> +       const struct acc_desc *acc_desc;
> +};
> +
> +struct fuse_corner {
> +       int min_uV;
> +       int max_uV;
> +       int uV;
> +       int quot;
> +       int step_quot;
> +       const struct reg_sequence *accs;
> +       int num_accs;
> +       unsigned long max_freq;
> +       u32 ring_osc_idx;

Can this be a u8?

> +};
> +
> +struct corner {
> +       int min_uV;
> +       int max_uV;
> +       int uV;
> +       int last_uV;
> +       int quot_adjust;
> +       u32 save_ctl;
> +       u32 save_irq;
> +       unsigned long freq;
> +       struct fuse_corner *fuse_corner;
> +};
> +
> +struct cpr_drv {
> +       unsigned int            num_corners;
> +
> +       unsigned int            ref_clk_khz;
> +       unsigned int            timer_delay_us;
> +       unsigned int            timer_cons_up;
> +       unsigned int            timer_cons_down;
> +       unsigned int            up_threshold;
> +       unsigned int            down_threshold;
> +       unsigned int            idle_clocks;
> +       unsigned int            gcnt_us;
> +       unsigned int            vdd_apc_step_up_limit;
> +       unsigned int            vdd_apc_step_down_limit;
> +       unsigned int            clamp_timer_interval;
> +       unsigned int            performance_state;
> +
> +       struct generic_pm_domain pd;
> +       struct device           *dev;
> +       struct mutex            lock;
> +       void __iomem            *base;
> +       struct corner           *corner;
> +       struct regulator        *vdd_apc;
> +       struct clk              *cpu_clk;
> +       struct regmap           *tcsr;
> +       bool                    loop_disabled;
> +       bool                    suspended;
> +       u32                     gcnt;
> +       unsigned long           flags;
> +
> +       struct fuse_corner      *fuse_corners;
> +       struct corner           *corners;
> +
> +       const struct cpr_desc *desc;
> +       const struct acc_desc *acc_desc;
> +       const struct cpr_fuse *cpr_fuses;
> +
> +       struct dentry *debugfs;
> +};
> +
> +static bool cpr_is_allowed(struct cpr_drv *drv)
> +{
> +       if (drv->loop_disabled)
> +               return false;
> +       else
> +               return true;

Simplify to return !drv->loop_disabled

> +}
> +
> +static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
> +{
> +       writel_relaxed(value, drv->base + offset);
> +}
> +
[...]
> +
> +static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
> +{
> +       u32 gcnt, ctl, irq, ro_sel, step_quot;
> +       struct fuse_corner *fuse = corner->fuse_corner;
> +       int i;
> +
> +       ro_sel = fuse->ring_osc_idx;
> +       gcnt = drv->gcnt;
> +       gcnt |= fuse->quot - corner->quot_adjust;
> +
> +       /* Program the step quotient and idle clocks */
> +       step_quot = drv->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
> +       step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
> +       cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
> +
> +       /* Clear the target quotient value and gate count of all ROs */
> +       for (i = 0; i < CPR_NUM_RING_OSC; i++)
> +               cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
> +
> +       cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
> +       ctl = corner->save_ctl;
> +       cpr_write(drv, REG_RBCPR_CTL, ctl);
> +       irq = corner->save_irq;
> +       cpr_irq_set(drv, irq);
> +       dev_dbg(drv->dev, "gcnt = 0x%08x, ctl = 0x%08x, irq = 0x%08x\n", gcnt,

Use %#08x to get the 0x part?

> +               ctl, irq);
> +}
> +
> +static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
> +                       struct fuse_corner *end)
> +{
> +       if (f < end) {
> +               for (f += 1; f <= end; f++)
> +                       regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
> +       } else {
> +               for (f -= 1; f >= end; f--)
> +                       regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
> +       }
> +}
> +
> +static int cpr_pre_voltage(struct cpr_drv *drv,
> +                          struct fuse_corner *fuse_corner,
> +                          enum voltage_change_dir dir)
> +{
> +       int ret = 0;
> +       struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
> +
> +       if (drv->tcsr && dir == DOWN)
> +               cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
> +
> +       return ret;
> +}
> +
> +static int cpr_post_voltage(struct cpr_drv *drv,
> +                           struct fuse_corner *fuse_corner,
> +                           enum voltage_change_dir dir)
> +{
> +       int ret = 0;

ret never changes in the above two functions. Remove it?

> +       struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
> +
> +       if (drv->tcsr && dir == UP)
> +               cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
> +
> +       return ret;
> +}
> +
> +static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
> +                            int new_uV, enum voltage_change_dir dir)
> +{
> +       int ret = 0;

Drop initial assignment to 0 because it's overwritten immediately below.

> +       struct fuse_corner *fuse_corner = corner->fuse_corner;
> +
> +       ret = cpr_pre_voltage(drv, fuse_corner, dir);
> +       if (ret)
> +               return ret;
> +
> +       ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
> +       if (ret) {
> +               dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
> +                                   new_uV);
> +               return ret;
> +       }
> +
> +       ret = cpr_post_voltage(drv, fuse_corner, dir);
> +       if (ret)
> +               return ret;
> +
> +       return 0;
> +}
> +
[...]
> +
> +static irqreturn_t cpr_irq_handler(int irq, void *dev)
> +{
> +       struct cpr_drv *drv = dev;
> +       u32 val;
> +
> +       mutex_lock(&drv->lock);
> +
> +       val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
> +       if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
> +               val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
> +
> +       dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
> +
> +       if (!cpr_ctl_is_enabled(drv)) {
> +               dev_dbg(drv->dev, "CPR is disabled\n");

Shouldn't this return IRQ_NONE because it's spurious?

> +               goto unlock;
> +       } else if (cpr_ctl_is_busy(drv) && !drv->clamp_timer_interval) {
> +               dev_dbg(drv->dev, "CPR measurement is not ready\n");
> +               goto unlock;
> +       } else if (!cpr_is_allowed(drv)) {
> +               val = cpr_read(drv, REG_RBCPR_CTL);
> +               dev_err_ratelimited(drv->dev,
> +                                   "Interrupt broken? RBCPR_CTL = %#02x\n",
> +                                   val);

Same case, return IRQ_NONE?

> +               goto unlock;

Maybe the goto can be dropped and you can use an else here to fall into
the 'normal' processing modes. Everything would have to be indented
again, but it will probably look alright.

> +       }
> +
> +       /* Following sequence of handling is as per each IRQ's priority */
> +       if (val & CPR_INT_UP) {
> +               cpr_scale(drv, UP);
> +       } else if (val & CPR_INT_DOWN) {
> +               cpr_scale(drv, DOWN);
> +       } else if (val & CPR_INT_MIN) {
> +               cpr_irq_clr_nack(drv);
> +       } else if (val & CPR_INT_MAX) {
> +               cpr_irq_clr_nack(drv);
> +       } else if (val & CPR_INT_MID) {
> +               /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
> +               dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
> +       } else {
> +               dev_dbg(drv->dev, "IRQ occurred for unknown flag (%#08x)\n",
> +                       val);
> +       }
> +
> +       /* Save register values for the corner */
> +       cpr_corner_save(drv, drv->corner);
> +
> +unlock:
> +       mutex_unlock(&drv->lock);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +static int cpr_enable(struct cpr_drv *drv)
> +{
> +       int ret;
> +
> +       ret = regulator_enable(drv->vdd_apc);
> +       if (ret)
> +               return ret;
> +
> +       mutex_lock(&drv->lock);
> +
> +       if (cpr_is_allowed(drv) && drv->corner) {
> +               cpr_irq_clr(drv);
> +               cpr_corner_restore(drv, drv->corner);
> +               cpr_ctl_enable(drv, drv->corner);
> +       }
> +       mutex_unlock(&drv->lock);
> +
> +       return 0;
> +}
> +
> +static int cpr_disable(struct cpr_drv *drv)
> +{
> +       int ret;
> +
> +       ret = regulator_disable(drv->vdd_apc);
> +       if (ret)
> +               return ret;
> +
> +       mutex_lock(&drv->lock);
> +
> +       if (cpr_is_allowed(drv))
> +               cpr_ctl_disable(drv);
> +       mutex_unlock(&drv->lock);

Seems weird to disable cpr in reverse order. Is that OK? Or should the
cpr monitoring be disabled first and then regulator is disabled? When is
the CPU's regulator disabled in relation to when it is hotplugged or
idle? I haven't followed the power domain stuff too closely.

> +
> +       return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int cpr_suspend(struct device *dev)
> +{
> +       struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
> +
> +       if (cpr_is_allowed(drv)) {

Sometimes cpr_is_allowed() is tested inside the mutex and other times
not. Please be consistent.

> +               mutex_lock(&drv->lock);
> +               cpr_ctl_disable(drv);
> +               cpr_irq_clr(drv);
> +               drv->suspended = true;
> +               mutex_unlock(&drv->lock);
> +       }
> +
> +       return 0;
> +}
> +
> +static int cpr_resume(struct device *dev)
> +{
> +       struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
> +
> +       if (cpr_is_allowed(drv)) {
> +               mutex_lock(&drv->lock);
> +               drv->suspended = false;
> +               cpr_irq_clr(drv);
> +               cpr_ctl_enable(drv, drv->corner);
> +               mutex_unlock(&drv->lock);
> +       }
> +
> +       return 0;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(cpr_pm_ops, cpr_suspend, cpr_resume);
> +
> +static int cpr_config(struct cpr_drv *drv)
> +{
> +       int i;
> +       u32 val, gcnt;
> +       struct corner *corner;
> +
> +       /* Disable interrupt and CPR */
> +       cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
> +       cpr_write(drv, REG_RBCPR_CTL, 0);
> +
> +       /* Program the default HW Ceiling, Floor and vlevel */

Why capitalize ceiling and floor?

> +       val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
> +               << RBIF_LIMIT_CEILING_SHIFT;
> +       val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
> +       cpr_write(drv, REG_RBIF_LIMIT, val);
> +       cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
> +
> +       /* Clear the target quotient value and gate count of all ROs */

RO == ring oscillator? Maybe just write ring oscillator.

> +       for (i = 0; i < CPR_NUM_RING_OSC; i++)
> +               cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
> +
> +       /* Init and save gcnt */
> +       gcnt = (drv->ref_clk_khz * drv->gcnt_us) / 1000;
> +       gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
> +       gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
> +       drv->gcnt = gcnt;
> +
> +       /* Program the delay count for the timer */
> +       val = (drv->ref_clk_khz * drv->timer_delay_us) / 1000;
> +       cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
> +       dev_dbg(drv->dev, "Timer count: 0x%0x (for %d us)\n", val,
> +               drv->timer_delay_us);
> +
[...]
> +
> +static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
> +{
> +       struct nvmem_cell *cell;
> +       ssize_t len;
> +       char *ret;
> +       int i;
> +
> +       if (!data) {

Looks like debug stuff, drop it?

> +               dev_err(dev, "invalid storage to read cell %s\n", cname);
> +               return -EINVAL;
> +       }
> +
> +       /* Optional cells will use their initialition values */

initialization?

> +       if (!cname)

Same?

> +               return 0;
> +
> +       *data = 0;
> +
> +       cell = nvmem_cell_get(dev, cname);
> +       if (IS_ERR(cell)) {
> +               if (PTR_ERR(cell) != -EPROBE_DEFER)
> +                       dev_info(dev, "undefined cell %s\n", cname);

dev_err()?

> +               return PTR_ERR(cell);
> +       }
> +
> +       ret = nvmem_cell_read(cell, &len);
> +       nvmem_cell_put(cell);
> +       if (IS_ERR(ret)) {
> +               dev_err(dev, "can't read cell %s\n", cname);
> +               return PTR_ERR(ret);
> +       }
> +
> +       for (i = 0; i < len; i++)
> +               *data |= ret[i] << (8 * i);

Amazing we don't have some sort of char array to u32 function.

> +
> +       kfree(ret);
> +       dev_dbg(dev, "efuse read(%s) = %x, bytes %ld\n", cname, *data, len);
> +
> +       return 0;
> +}
> +
[...]
> +
> +static int cpr_calculate_scaling(const char *quot_offset,
> +                                struct cpr_drv *drv,
> +                                const struct fuse_corner_data *fdata,
> +                                const struct corner *corner)
> +{
> +       u32 quot_diff = 0;
> +       unsigned long freq_diff;
> +       int scaling;
> +       const struct fuse_corner *fuse, *prev_fuse;
> +       int ret;
> +
> +       fuse = corner->fuse_corner;
> +       prev_fuse = fuse - 1;
> +
> +       if (quot_offset) {
> +               ret = cpr_read_efuse(drv->dev, quot_offset, &quot_diff);
> +               if (ret)
> +                       return ret;
> +
> +               quot_diff *= fdata->quot_offset_scale;
> +               quot_diff += fdata->quot_offset_adjust;
> +       } else {
> +               quot_diff = fuse->quot - prev_fuse->quot;
> +       }
> +
> +       freq_diff = fuse->max_freq - prev_fuse->max_freq;
> +       freq_diff /= 1000000; /* Convert to MHz */
> +       scaling = 1000 * quot_diff / freq_diff;
> +       return min(scaling, fdata->max_quot_scale);
> +}
> +
> +static int cpr_interpolate(const struct corner *corner, int step_volt,
> +                          const struct fuse_corner_data *fdata)
> +{
> +       unsigned long f_high, f_low, f_diff;
> +       int uV_high, uV_low, uV;
> +       u64 temp, temp_limit;
> +       const struct fuse_corner *fuse, *prev_fuse;
> +
> +       fuse = corner->fuse_corner;
> +       prev_fuse = fuse - 1;
> +
> +       f_high = fuse->max_freq;
> +       f_low = prev_fuse->max_freq;
> +       uV_high = fuse->uV;
> +       uV_low = prev_fuse->uV;
> +       f_diff = fuse->max_freq - corner->freq;
> +
> +       /*
> +        * Don't interpolate in the wrong direction. This could happen
> +        * if the adjusted fuse voltage overlaps with the previous fuse's
> +        * adjusted voltage.
> +        */
> +       if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
> +               return corner->uV;
> +
> +       temp = f_diff * (uV_high - uV_low);
> +       do_div(temp, f_high - f_low);
> +
> +       /*
> +        * max_volt_scale has units of uV/MHz while freq values
> +        * have units of Hz.  Divide by 1000000 to convert to.
> +        */
> +       temp_limit = f_diff * fdata->max_volt_scale;
> +       do_div(temp_limit, 1000000);
> +
> +       uV = uV_high - min(temp, temp_limit);
> +       return roundup(uV, step_volt);
> +}
> +
> +static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
> +{
> +       struct device_node *np;
> +       unsigned int fuse_corner = 0;
> +
> +       np = dev_pm_opp_get_of_node(opp);
> +       if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner)) {
> +               pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
> +                      __func__);
> +               return 0;
> +       }
> +
> +       of_node_put(np);

Do you need to of_node_put() on error above?

> +
> +       return fuse_corner;
> +}
> +
> +unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref)
> +{
> +       u64 rate = 0;
> +       struct device *cpu_dev;
> +       struct device_node *ref_np;
> +       struct device_node *desc_np;
> +       struct device_node *child_np = NULL;
> +       struct device_node *child_req_np = NULL;
> +
> +       cpu_dev = get_cpu_device(0);
> +       if (!cpu_dev)
> +               return 0;
> +
> +       desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> +       if (!desc_np)
> +               return 0;
> +
> +       ref_np = dev_pm_opp_get_of_node(ref);
> +       if (!ref_np)
> +               goto out_ref;
> +
> +       do {
> +               of_node_put(child_req_np);
> +               child_np = of_get_next_available_child(desc_np, child_np);
> +               child_req_np = of_parse_phandle(child_np, "required-opps", 0);
> +       } while (child_np && child_req_np != ref_np);
> +
> +       if (child_np && child_req_np == ref_np)
> +               of_property_read_u64(child_np, "opp-hz", &rate);
> +
> +       of_node_put(child_req_np);
> +       of_node_put(child_np);
> +       of_node_put(ref_np);
> +out_ref:
> +       of_node_put(desc_np);
> +
> +       return (unsigned long) rate;
> +}
> +
> +static int cpr_corner_init(struct cpr_drv *drv)
> +{
> +       const struct cpr_desc *desc = drv->desc;
> +       const struct cpr_fuse *fuses = drv->cpr_fuses;
> +       int i, level, count, scaling = 0;
> +       unsigned int fnum, fc;
> +       const char *quot_offset;
> +       struct fuse_corner *fuse, *prev_fuse;
> +       struct corner *corner, *end;
> +       struct corner_data *cdata;
> +       const struct fuse_corner_data *fdata;
> +       bool apply_scaling;
> +       unsigned long freq_diff, freq_diff_mhz;
> +       unsigned long freq;
> +       int step_volt = regulator_get_linear_step(drv->vdd_apc);
> +       struct dev_pm_opp *opp;
> +       struct device *pd_dev;
> +
> +       if (!step_volt)
> +               return -EINVAL;
> +
> +       corner = drv->corners;
> +       end = &corner[drv->num_corners - 1];
> +
> +       pd_dev = &drv->pd.dev;
> +       cdata = devm_kzalloc(drv->dev,
> +                            sizeof(struct corner_data) * drv->num_corners,
> +                            GFP_KERNEL);
> +       if (!cdata)
> +               return -ENOMEM;
> +
> +       /*
> +        * Store maximum frequency for each fuse corner based on the frequency
> +        * plan
> +        */
> +       count = dev_pm_opp_get_opp_count(pd_dev);
> +       for (level = 1; level <= count; level++) {
> +               opp = dev_pm_opp_find_level_exact(pd_dev, level);
> +               if (IS_ERR(opp))
> +                       return -EINVAL;
> +               fc = cpr_get_fuse_corner(opp);
> +               if (!fc) {
> +                       dev_pm_opp_put(opp);
> +                       return -EINVAL;
> +               }
> +               fnum = fc - 1;
> +               freq = cpr_get_opp_hz_for_req(opp);
> +               if (!freq) {
> +                       dev_pm_opp_put(opp);
> +                       return -EINVAL;
> +               }
> +               cdata[level - 1].fuse_corner = fnum;
> +               cdata[level - 1].freq = freq;
> +
> +               fuse = &drv->fuse_corners[fnum];
> +               dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
> +                       freq, dev_pm_opp_get_level(opp) - 1, fnum);
> +               if (freq > fuse->max_freq)
> +                       fuse->max_freq = freq;
> +               dev_pm_opp_put(opp);
> +       }
> +
> +       /*
> +        * Get the quotient adjustment scaling factor, according to:
> +        *
> +        * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
> +        *              / (freq(corner_N) - freq(corner_N-1)), max_factor)
> +        *
> +        * QUOT(corner_N):      quotient read from fuse for fuse corner N
> +        * QUOT(corner_N-1):    quotient read from fuse for fuse corner (N - 1)
> +        * freq(corner_N):      max frequency in MHz supported by fuse corner N
> +        * freq(corner_N-1):    max frequency in MHz supported by fuse corner
> +        *                       (N - 1)
> +        *
> +        * Then walk through the corners mapped to each fuse corner
> +        * and calculate the quotient adjustment for each one using the
> +        * following formula:
> +        *
> +        * quot_adjust = (freq_max - freq_corner) * scaling / 1000
> +        *
> +        * freq_max: max frequency in MHz supported by the fuse corner
> +        * freq_corner: frequency in MHz corresponding to the corner
> +        * scaling: calculated from above equation
> +        *
> +        *
> +        *     +                           +
> +        *     |                         v |
> +        *   q |           f c           o |           f c
> +        *   u |         c               l |         c
> +        *   o |       f                 t |       f
> +        *   t |     c                   a |     c
> +        *     | c f                     g | c f
> +        *     |                         e |
> +        *     +---------------            +----------------
> +        *       0 1 2 3 4 5 6               0 1 2 3 4 5 6
> +        *          corner                      corner
> +        *
> +        *    c = corner
> +        *    f = fuse corner
> +        *
> +        */
> +       for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
> +               fnum = cdata[i].fuse_corner;
> +               fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
> +               quot_offset = fuses[fnum].quotient_offset;
> +               fuse = &drv->fuse_corners[fnum];
> +               if (fnum)
> +                       prev_fuse = &drv->fuse_corners[fnum - 1];
> +               else
> +                       prev_fuse = NULL;
> +
> +               corner->fuse_corner = fuse;
> +               corner->freq = cdata[i].freq;
> +               corner->uV = fuse->uV;
> +
> +               if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
> +                       scaling = cpr_calculate_scaling(quot_offset, drv,
> +                                                       fdata, corner);
> +                       if (scaling < 0)
> +                               return scaling;
> +
> +                       apply_scaling = true;
> +               } else if (corner->freq == fuse->max_freq) {
> +                       /* This is a fuse corner; don't scale anything */
> +                       apply_scaling = false;
> +               }
> +
> +               if (apply_scaling) {
> +                       freq_diff = fuse->max_freq - corner->freq;
> +                       freq_diff_mhz = freq_diff / 1000000;
> +                       corner->quot_adjust = scaling * freq_diff_mhz / 1000;
> +
> +                       corner->uV = cpr_interpolate(corner, step_volt, fdata);
> +               }
> +
> +               corner->max_uV = fuse->max_uV;
> +               corner->min_uV = fuse->min_uV;
> +               corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
> +               corner->last_uV = corner->uV;
> +
> +               /* Reduce the ceiling voltage if needed */
> +               if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
> +                       corner->max_uV = corner->uV;
> +               else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
> +                       corner->max_uV = max(corner->min_uV, fuse->uV);
> +
> +               dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
> +                       corner->min_uV, corner->uV, corner->max_uV,
> +                       fuse->quot - corner->quot_adjust);
> +       }
> +
> +       return 0;
> +}
> +
> +static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
> +{
> +       const struct cpr_desc *desc = drv->desc;
> +       struct cpr_fuse *fuses;
> +       int i;
> +
> +       fuses = devm_kzalloc(drv->dev,
> +                            sizeof(struct cpr_fuse) * desc->num_fuse_corners,
> +                            GFP_KERNEL);
> +       if (!fuses)
> +               return ERR_PTR(-ENOMEM);
> +
> +       for (i = 0; i < desc->num_fuse_corners; i++) {
> +               char tbuf[32];
> +
> +               snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
> +               fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
> +               if (!fuses[i].ring_osc)
> +                       return ERR_PTR(-ENOMEM);
> +
> +               snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
> +               fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
> +                                                    GFP_KERNEL);
> +               if (!fuses[i].init_voltage)
> +                       return ERR_PTR(-ENOMEM);
> +
> +               snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
> +               fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
> +               if (!fuses[i].quotient)
> +                       return ERR_PTR(-ENOMEM);
> +
> +               snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
> +               fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
> +                                                       GFP_KERNEL);
> +               if (!fuses[i].quotient_offset)
> +                       return ERR_PTR(-ENOMEM);
> +       }
> +
> +       return fuses;
> +}
> +
> +static int cpr_set_loop_allowed(struct cpr_drv *drv)
> +{
> +       drv->loop_disabled = false;
> +
> +       return 0;

Drop the return code?

> +}
> +
> +static int cpr_init_parameters(struct cpr_drv *drv)
> +{
> +       struct device_node *of_node = drv->dev->of_node;
> +       int ret;
> +       struct clk *clk;
> +
> +       clk = clk_get(drv->dev, "ref");
> +       if (IS_ERR(clk))
> +               return PTR_ERR(clk);
> +
> +       drv->ref_clk_khz = clk_get_rate(clk) / 1000;
> +       clk_put(clk);
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-timer-delay-us",
> +                                  &drv->timer_delay_us);
> +       if (ret)
> +               return ret;
> +       ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-up",
> +                                  &drv->timer_cons_up);
> +       if (ret)
> +               return ret;
> +       drv->timer_cons_up &= RBIF_TIMER_ADJ_CONS_UP_MASK;
> +       ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-down",
> +                                  &drv->timer_cons_down);
> +       if (ret)
> +               return ret;
> +       drv->timer_cons_down &= RBIF_TIMER_ADJ_CONS_DOWN_MASK;
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-up-threshold",
> +                                  &drv->up_threshold);
> +       drv->up_threshold &= RBCPR_CTL_UP_THRESHOLD_MASK;
> +       if (ret)
> +               return ret;
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-down-threshold",
> +                                  &drv->down_threshold);
> +       drv->down_threshold &= RBCPR_CTL_DN_THRESHOLD_MASK;
> +       if (ret)
> +               return ret;
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-idle-clocks",
> +                                  &drv->idle_clocks);
> +       drv->idle_clocks &= RBCPR_STEP_QUOT_IDLE_CLK_MASK;
> +       if (ret)
> +               return ret;
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-gcnt-us", &drv->gcnt_us);
> +       if (ret)
> +               return ret;
> +       ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-up-limit",
> +                                  &drv->vdd_apc_step_up_limit);
> +       if (ret)
> +               return ret;
> +       ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-down-limit",
> +                                  &drv->vdd_apc_step_down_limit);
> +       if (ret)
> +               return ret;
> +
> +       ret = of_property_read_u32(of_node, "qcom,cpr-clamp-timer-interval",
> +                                  &drv->clamp_timer_interval);
> +       if (ret && ret != -EINVAL)
> +               return ret;
> +
> +       drv->clamp_timer_interval = min_t(unsigned int,
> +                                         drv->clamp_timer_interval,
> +                                         RBIF_TIMER_ADJ_CLAMP_INT_MASK);
> +
> +       dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
> +               drv->up_threshold, drv->down_threshold);
> +
> +       return 0;
> +}
> +
> +static int cpr_find_initial_corner(struct cpr_drv *drv)
> +{
> +       unsigned long rate;
> +       const struct corner *end;
> +       struct corner *iter;
> +       int i = 0;
> +
> +       if (IS_ERR_OR_NULL(drv->cpu_clk)) {

Will this ever happen?

> +               dev_err(drv->dev, "cpu clk is not set\n");
> +               return -EINVAL;
> +       }
> +
> +       end = &drv->corners[drv->num_corners - 1];
> +       rate = clk_get_rate(drv->cpu_clk);
> +
> +       for (iter = drv->corners; iter <= end; iter++) {
> +               if (iter->freq > rate)
> +                       break;
> +               i++;
> +               if (iter->freq == rate) {
> +                       drv->corner = iter;
> +                       drv->performance_state = i;
> +                       break;
> +               }
> +               if (iter->freq < rate) {
> +                       drv->corner = iter;
> +                       drv->performance_state = i;
> +               }
> +       }
> +
> +       if (!drv->corner) {
> +               dev_err(drv->dev, "boot up corner not found\n");
> +               return -EINVAL;
> +       }
> +
> +       dev_dbg(drv->dev, "boot up perf state: %d\n", i);
> +
> +       return 0;
> +}
[...]
> +
> +static unsigned int cpr_get_performance(struct generic_pm_domain *genpd,
> +                                       struct dev_pm_opp *opp)
> +{
> +       return dev_pm_opp_get_level(opp);
> +}
> +
> +static int cpr_power_off(struct generic_pm_domain *domain)
> +{
> +       struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
> +
> +       return cpr_disable(drv);
> +}
> +
> +static int cpr_power_on(struct generic_pm_domain *domain)
> +{
> +       struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
> +
> +       return cpr_enable(drv);
> +}
> +
> +static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
> +                            struct device *dev)
> +{
> +       struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
> +       const struct acc_desc *acc_desc = drv->acc_desc;
> +       size_t len;
> +       int ret;
> +
> +       dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
> +
> +       if (!drv->cpu_clk) {

Maybe this could be if (drv->cpu_clk) return 0, and then deindent
everything else.

> +               drv->cpu_clk = devm_clk_get(dev, NULL);
> +               if (IS_ERR_OR_NULL(drv->cpu_clk)) {

NULL is a valid clk. Probably just want to check for IS_ERR() and also
not do anything with the return value besides PTR_ERR() on it?
Eventually EPROBE_DEFER will arrive.

> +                       dev_err(drv->dev, "could not get cpu clk\n");
> +                       return -EINVAL;
> +               }
> +
> +               dev_dbg(drv->dev, "using cpu clk from: %s\n", dev_name(dev));
> +
> +               /* Everything related to (virtual) corners has to be initialized
> +                * here, when attaching to the power domain, since it depends on
> +                * the power domain's OPP table, which isn't available earlier.
> +                */
> +               drv->num_corners = dev_pm_opp_get_opp_count(&drv->pd.dev);
> +               if (drv->num_corners < 0)
> +                       return drv->num_corners;
> +               if (drv->num_corners < 2) {
> +                       dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
> +                       return -EINVAL;
> +               }
> +
> +               dev_dbg(drv->dev, "number of OPPs: %d\n", drv->num_corners);
> +
> +               len = sizeof(*drv->corners) * drv->num_corners;
> +               drv->corners = devm_kzalloc(dev, len, GFP_KERNEL);
> +               if (!drv->corners)
> +                       return -ENOMEM;
> +
> +               ret = cpr_corner_init(drv);
> +               if (ret)
> +                       return ret;
> +
> +               ret = cpr_set_loop_allowed(drv);
> +               if (ret)
> +                       return ret;
> +
> +               ret = cpr_init_parameters(drv);
> +               if (ret)
> +                       return ret;
> +
> +               /* Configure CPR HW but keep it disabled */
> +               ret = cpr_config(drv);
> +               if (ret)
> +                       return ret;
> +
> +               ret = cpr_find_initial_corner(drv);
> +               if (ret)
> +                       return ret;
> +
> +               if (acc_desc->config)
> +                       regmap_multi_reg_write(drv->tcsr, acc_desc->config,
> +                                              acc_desc->num_regs_per_fuse);
> +
> +               /* Enable ACC if required */
> +               if (acc_desc->enable_mask)
> +                       regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
> +                                          acc_desc->enable_mask,
> +                                          acc_desc->enable_mask);
> +       }
> +
> +       return 0;
> +}
> +
> +static int cpr_debug_info_open(struct inode *inode, struct file *file)
> +{
> +       file->private_data = inode->i_private;
> +
> +       return 0;
> +}
> +
> +static ssize_t cpr_debug_info_read(struct file *file, char __user *buff,
> +                                  size_t count, loff_t *ppos)
> +{
> +       u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
> +       u32 step_dn, step_up, error, error_lt0, busy;
> +       struct cpr_drv *drv = file->private_data;
> +       struct fuse_corner *fuse_corner;
> +       struct corner *corner;
> +       ssize_t len, ret = 0;
> +       char *debugfs_buf;
> +
> +       debugfs_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
> +       if (!debugfs_buf)
> +               return -ENOMEM;
> +
> +       mutex_lock(&drv->lock);
> +
> +       corner = drv->corner;
> +       fuse_corner = corner->fuse_corner;
> +
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "corner, current_volt = %d uV\n",
> +                      corner->last_uV);
> +       ret += len;
> +
> +       ro_sel = fuse_corner->ring_osc_idx;
> +       gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "rbcpr_gcnt_target (%u) = 0x%02X\n", ro_sel, gcnt);
> +       ret += len;
> +
> +       ctl = cpr_read(drv, REG_RBCPR_CTL);
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "rbcpr_ctl = 0x%02X\n", ctl);
> +       ret += len;
> +
> +       irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "rbcpr_irq_status = 0x%02X\n", irq_status);
> +       ret += len;
> +
> +       reg = cpr_read(drv, REG_RBCPR_RESULT_0);
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "rbcpr_result_0 = 0x%02X\n", reg);
> +       ret += len;
> +
> +       step_dn = reg & 0x01;
> +       step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      "  [step_dn = %u", step_dn);
> +       ret += len;
> +
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      ", step_up = %u", step_up);
> +       ret += len;
> +
> +       error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
> +                               & RBCPR_RESULT0_ERROR_STEPS_MASK;
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,

> +                      ", error_steps = %u", error_steps);
> +       ret += len;
> +
> +       error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      ", error = %u", error);
> +       ret += len;
> +
> +       error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      ", error_lt_0 = %u", error_lt0);
> +       ret += len;
> +
> +       busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
> +       len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret,
> +                      ", busy = %u]\n", busy);
> +       ret += len;
> +       mutex_unlock(&drv->lock);

What is the mutex for? Doesn't seem like a good idea for the debugfs API
to be able to DDOS the threaded irq.

> +
> +       ret = simple_read_from_buffer(buff, count, ppos, debugfs_buf, ret);

Can this use a seq_file instead of simple_read_from_buffer()?

> +       kfree(debugfs_buf);
> +       return ret;
> +}
> +
> +static const struct file_operations cpr_debug_info_fops = {
> +       .open = cpr_debug_info_open,
> +       .read = cpr_debug_info_read,
> +};
> +
> +static void cpr_debugfs_init(struct cpr_drv *drv)
> +{
> +       drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
> +
> +       debugfs_create_file("debug_info", 0444, drv->debugfs,
> +                           drv, &cpr_debug_info_fops);
> +}
> +
> +static int cpr_probe(struct platform_device *pdev)
> +{
> +       struct resource *res;
> +       struct device *dev = &pdev->dev;
> +       struct cpr_drv *drv;
> +       size_t len;
> +       int irq, ret;
> +       const struct cpr_acc_desc *data;
> +       struct device_node *np;
> +       u32 cpr_rev = FUSE_REVISION_UNKNOWN;
> +
> +       data = of_device_get_match_data(dev);
> +       if (!data || !data->cpr_desc || !data->acc_desc)
> +               return -EINVAL;
> +
> +       drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> +       if (!drv)
> +               return -ENOMEM;
> +       drv->dev = dev;
> +       drv->desc = data->cpr_desc;
> +       drv->acc_desc = data->acc_desc;
> +
> +       len = sizeof(*drv->fuse_corners) * drv->desc->num_fuse_corners;
> +       drv->fuse_corners = devm_kzalloc(dev, len, GFP_KERNEL);

Use devm_kcalloc() to allocate arrays

> +       if (!drv->fuse_corners)
> +               return -ENOMEM;
> +
> +       np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
> +       if (!np)
> +               return -ENODEV;
> +
> +       drv->tcsr = syscon_node_to_regmap(np);
> +       of_node_put(np);
> +       if (IS_ERR(drv->tcsr))
> +               return PTR_ERR(drv->tcsr);
> +
> +       mutex_init(&drv->lock);
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       drv->base = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(drv->base))
> +               return PTR_ERR(drv->base);
> +
> +       irq = platform_get_irq(pdev, 0);
> +       if (irq < 0)
> +               return -EINVAL;
> +
> +       drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
> +       if (IS_ERR(drv->vdd_apc))
> +               return PTR_ERR(drv->vdd_apc);
> +
> +       /* Initialize fuse corners, since it simply depends

Please fix multi line comment style to have a single /* at the
beginning.

> +        * on data in efuses.
> +        * Everything related to (virtual) corners has to be
> +        * initialized after attaching to the power domain,
> +        * since is depends on the OPP table.
> +        */
> +       ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
> +       if (ret)
> +               return ret;
> +
> +       drv->cpr_fuses = cpr_get_fuses(drv);
> +       if (IS_ERR(drv->cpr_fuses))
> +               return PTR_ERR(drv->cpr_fuses);
> +
> +       ret = cpr_populate_ring_osc_idx(drv);
> +       if (ret)
> +               return ret;
> +
> +       ret = cpr_fuse_corner_init(drv);
> +       if (ret)
> +               return ret;
> +
> +       ret = devm_request_threaded_irq(dev, irq, NULL,
> +                                       cpr_irq_handler,
> +                                       IRQF_ONESHOT | IRQF_TRIGGER_RISING,
> +                                       "cpr", drv);
> +       if (ret)
> +               return ret;
> +
> +       drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
> +                                         GFP_KERNEL);
> +       if (!drv->pd.name)
> +               return -EINVAL;
> +
> +       drv->pd.power_off = cpr_power_off;
> +       drv->pd.power_on = cpr_power_on;
> +       drv->pd.set_performance_state = cpr_set_performance;
> +       drv->pd.opp_to_performance_state = cpr_get_performance;
> +       drv->pd.attach_dev = cpr_pd_attach_dev;
> +
> +       ret = pm_genpd_init(&drv->pd, NULL, true);
> +       if (ret)
> +               return ret;
> +
> +       ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
> +       if (ret)
> +               return ret;
> +
> +       platform_set_drvdata(pdev, drv);
> +       cpr_debugfs_init(drv);
> +
> +       return 0;
> +}
> +
> +static int cpr_remove(struct platform_device *pdev)
> +{
> +       struct cpr_drv *drv = platform_get_drvdata(pdev);
> +
> +       if (cpr_is_allowed(drv)) {
> +               cpr_ctl_disable(drv);
> +               cpr_irq_set(drv, 0);
> +       }
> +
> +       of_genpd_del_provider(pdev->dev.of_node);
> +       pm_genpd_remove(&drv->pd);
> +
> +       debugfs_remove_recursive(drv->debugfs);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id cpr_match_table[] = {
> +       { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
> +       { }
> +};
> +MODULE_DEVICE_TABLE(of, cpr_match_table);
> +
> +static struct platform_driver cpr_driver = {
> +       .probe          = cpr_probe,
> +       .remove         = cpr_remove,
> +       .driver         = {
> +               .name   = "qcom-cpr",
> +               .of_match_table = cpr_match_table,
> +               .pm = &cpr_pm_ops,
> +       },
> +};
> +module_platform_driver(cpr_driver);
> +
> +MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:qcom-cpr");

Is the alias needed?


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 03/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs
  2019-07-25 10:41 ` [PATCH v2 03/14] cpufreq: qcom: " Niklas Cassel
@ 2019-08-18  1:06   ` Stephen Boyd
  0 siblings, 0 replies; 31+ messages in thread
From: Stephen Boyd @ 2019-08-18  1:06 UTC (permalink / raw)
  To: Rafael J. Wysocki, Andy Gross, Ilia Lin, Niklas Cassel, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, vireshk, bjorn.andersson,
	ulf.hansson, Sricharan R, Niklas Cassel, linux-kernel, linux-pm

Quoting Niklas Cassel (2019-07-25 03:41:31)
> From: Sricharan R <sricharan@codeaurora.org>
> 
> The kryo cpufreq driver reads the nvmem cell and uses that data to
> populate the opps. There are other qcom cpufreq socs like krait which
> does similar thing. Except for the interpretation of the read data,
> rest of the driver is same for both the cases. So pull the common things
> out for reuse.
> 
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> [niklas.cassel@linaro.org: split dt-binding into a separate patch and
> do not rename the compatible string. Update MAINTAINERS file.]
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Reviewed-by: Ilia Lin <ilia.lin@kernel.org>
> ---

FWIW

Reviewed-by: Stephen Boyd <sboyd@kernel.org>


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-07-25 10:41 ` [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Niklas Cassel
  2019-08-16 21:21   ` Rob Herring
@ 2019-08-19 10:09   ` " Niklas Cassel
  2019-08-19 17:59     ` Stephen Boyd
  2019-08-30 10:29     ` [PATCH v4 06/14] dt-bindings: opp: " Niklas Cassel
  1 sibling, 2 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-08-19 10:09 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since V2:
-Picked up Rob's Reviewed-by on V2.
-As Rob pointed out in V1, it should be
"In 'cpu' nodes" and not "In 'cpus' nodes".
-In Example 2: include the qcom,opp-fuse-level property rather than "...",
since Rob pointed out in the review of V1 of "dt-bindings: opp: Add
 qcom-opp bindings with properties needed for CPR", that this property was
missing in this patch.

 .../bindings/opp/qcom-nvmem-cpufreq.txt       | 113 +++++++++++++++++-
 1 file changed, 112 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c5ea8b90e35d..1e6261570f3e 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -14,7 +14,7 @@ operating-points-v2 table when it is parsed by the OPP framework.
 
 Required properties:
 --------------------
-In 'cpus' nodes:
+In 'cpu' nodes:
 - operating-points-v2: Phandle to the operating-points-v2 table to use.
 
 In 'operating-points-v2' table:
@@ -23,6 +23,15 @@ In 'operating-points-v2' table:
 
 Optional properties:
 --------------------
+In 'cpu' nodes:
+- power-domains: A phandle pointing to the PM domain specifier which provides
+		the performance states available for active state management.
+		Please refer to the power-domains bindings
+		Documentation/devicetree/bindings/power/power_domain.txt
+		and also examples below.
+- power-domain-names: Should be
+	- 'cpr' for qcs404.
+
 In 'operating-points-v2' table:
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
@@ -682,3 +691,105 @@ soc {
 		};
 	};
 };
+
+Example 2:
+---------
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cprpd>;
+			power-domain-names = "cpr";
+		};
+	};
+
+	cpu_opp_table: cpu-opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		opp-1094400000 {
+			opp-hz = /bits/ 64 <1094400000>;
+			required-opps = <&cpr_opp1>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			required-opps = <&cpr_opp2>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			required-opps = <&cpr_opp3>;
+		};
+	};
+
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			qcom,opp-fuse-level = <3>;
+		};
+	};
+
+....
+
+soc {
+....
+	cprpd: cpr@b018000 {
+		compatible = "qcom,qcs404-cpr", "qcom,cpr";
+		reg = <0x0b018000 0x1000>;
+		....
+		vdd-apc-supply = <&pms405_s3>;
+		#power-domain-cells = <0>;
+		operating-points-v2 = <&cpr_opp_table>;
+		....
+	};
+};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v3 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  2019-07-25 10:41 ` [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Niklas Cassel
@ 2019-08-19 10:12   ` " Niklas Cassel
  2019-08-19 17:58     ` Stephen Boyd
  2019-08-23 12:34     ` Rob Herring
  0 siblings, 2 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-08-19 10:12 UTC (permalink / raw)
  To: Andy Gross, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Add qcom-opp bindings with properties needed for Core Power Reduction
(CPR).

CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and
msm8996. CPR was first introduced in msm8974.

Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
---
Changes since V2:
qcom,opp-fuse-level is really a required property and not an optional
property, so properly define it as such.

 .../devicetree/bindings/opp/qcom-opp.txt      | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt

diff --git a/Documentation/devicetree/bindings/opp/qcom-opp.txt b/Documentation/devicetree/bindings/opp/qcom-opp.txt
new file mode 100644
index 000000000000..32eb0793c7e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/qcom-opp.txt
@@ -0,0 +1,19 @@
+Qualcomm OPP bindings to describe OPP nodes
+
+The bindings are based on top of the operating-points-v2 bindings
+described in Documentation/devicetree/bindings/opp/opp.txt
+Additional properties are described below.
+
+* OPP Table Node
+
+Required properties:
+- compatible: Allow OPPs to express their compatibility. It should be:
+  "operating-points-v2-qcom-level"
+
+* OPP Node
+
+Required properties:
+- qcom,opp-fuse-level: A positive value representing the fuse corner/level
+  associated with this OPP node. Sometimes several corners/levels shares
+  a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
+  min uV, and max uV.
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v3 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  2019-08-19 10:12   ` [PATCH v3 " Niklas Cassel
@ 2019-08-19 17:58     ` Stephen Boyd
  2019-08-23 12:34     ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Stephen Boyd @ 2019-08-19 17:58 UTC (permalink / raw)
  To: Andy Gross, Niklas Cassel, Nishanth Menon, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Quoting Niklas Cassel (2019-08-19 03:12:38)
> Add qcom-opp bindings with properties needed for Core Power Reduction
> (CPR).
> 
> CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and
> msm8996. CPR was first introduced in msm8974.
> 
> Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>


^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v3 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-08-19 10:09   ` [PATCH v3 " Niklas Cassel
@ 2019-08-19 17:59     ` Stephen Boyd
  2019-08-22 10:27       ` Niklas Cassel
  2019-08-30 10:29     ` [PATCH v4 06/14] dt-bindings: opp: " Niklas Cassel
  1 sibling, 1 reply; 31+ messages in thread
From: Stephen Boyd @ 2019-08-19 17:59 UTC (permalink / raw)
  To: Andy Gross, Ilia Lin, Niklas Cassel, Nishanth Menon, Viresh Kumar
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

Quoting Niklas Cassel (2019-08-19 03:09:57)
> +
> +soc {
> +....
> +       cprpd: cpr@b018000 {

Maybe node name should be 'avs' for the industry standard adaptive
voltage scaling acronym?


> +               compatible = "qcom,qcs404-cpr", "qcom,cpr";
> +               reg = <0x0b018000 0x1000>;
> +               ....
> +               vdd-apc-supply = <&pms405_s3>;
> +               #power-domain-cells = <0>;

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction)
  2019-08-17  6:14   ` Stephen Boyd
@ 2019-08-22 10:20     ` Niklas Cassel
  0 siblings, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-08-22 10:20 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Jorge Ramirez-Ortiz, linux-arm-msm, vireshk, bjorn.andersson,
	ulf.hansson, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

On Fri, Aug 16, 2019 at 11:14:13PM -0700, Stephen Boyd wrote:
> Quoting Niklas Cassel (2019-07-25 03:41:38)
> > +       cpr@b018000 {
> > +               compatible = "qcom,qcs404-cpr", "qcom,cpr";
> > +               reg = <0x0b018000 0x1000>;
> > +               interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> > +               clocks = <&xo_board>;
> > +               clock-names = "ref";
> > +               vdd-apc-supply = <&pms405_s3>;
> > +               #power-domain-cells = <0>;
> > +               operating-points-v2 = <&cpr_opp_table>;
> > +               acc-syscon = <&tcsr>;
> > +
> > +               nvmem-cells = <&cpr_efuse_quot_offset1>,
> > +                       <&cpr_efuse_quot_offset2>,
> > +                       <&cpr_efuse_quot_offset3>,
> > +                       <&cpr_efuse_init_voltage1>,
> > +                       <&cpr_efuse_init_voltage2>,
> > +                       <&cpr_efuse_init_voltage3>,
> > +                       <&cpr_efuse_quot1>,
> > +                       <&cpr_efuse_quot2>,
> > +                       <&cpr_efuse_quot3>,
> > +                       <&cpr_efuse_ring1>,
> > +                       <&cpr_efuse_ring2>,
> > +                       <&cpr_efuse_ring3>,
> > +                       <&cpr_efuse_revision>;
> > +               nvmem-cell-names = "cpr_quotient_offset1",
> > +                       "cpr_quotient_offset2",
> > +                       "cpr_quotient_offset3",
> > +                       "cpr_init_voltage1",
> > +                       "cpr_init_voltage2",
> > +                       "cpr_init_voltage3",
> > +                       "cpr_quotient1",
> > +                       "cpr_quotient2",
> > +                       "cpr_quotient3",
> > +                       "cpr_ring_osc1",
> > +                       "cpr_ring_osc2",
> > +                       "cpr_ring_osc3",
> > +                       "cpr_fuse_revision";
> > +
> > +               qcom,cpr-timer-delay-us = <5000>;
> > +               qcom,cpr-timer-cons-up = <0>;
> > +               qcom,cpr-timer-cons-down = <2>;
> > +               qcom,cpr-up-threshold = <1>;
> > +               qcom,cpr-down-threshold = <3>;
> > +               qcom,cpr-idle-clocks = <15>;
> > +               qcom,cpr-gcnt-us = <1>;
> > +               qcom,vdd-apc-step-up-limit = <1>;
> > +               qcom,vdd-apc-step-down-limit = <1>;
> 
> Are any of these qcom,* properties going to change for a particular SoC?
> They look like SoC config data that should just go into the driver and
> change based on the SoC compatible string.
> 

Hello Stephen,
thanks a lot for your reviews.

I agree with you, will drop these properties from the dt-binding
and the driver once I respin the series.

I'm hoping to get the cpufreq part of the patch series merged this
merge window, so that the patch pile will decrease.


Kind regards,
Niklas

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v3 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-08-19 17:59     ` Stephen Boyd
@ 2019-08-22 10:27       ` Niklas Cassel
  2019-08-28 17:52         ` Stephen Boyd
  0 siblings, 1 reply; 31+ messages in thread
From: Niklas Cassel @ 2019-08-22 10:27 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, Ilia Lin, Nishanth Menon, Viresh Kumar,
	linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Rob Herring, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

On Mon, Aug 19, 2019 at 10:59:36AM -0700, Stephen Boyd wrote:
> Quoting Niklas Cassel (2019-08-19 03:09:57)
> > +
> > +soc {
> > +....
> > +       cprpd: cpr@b018000 {
> 
> Maybe node name should be 'avs' for the industry standard adaptive
> voltage scaling acronym?

I see where this is coming from, but "git grep avs" gives a single result.

Also, since the label is cprpd, it doesn't make sense to simply rename the
node name, and I don't think that avspd would be a good name, since it is
less correct.

So if you don't insist, I would prefer to leave it as it is.

> 
> 
> > +               compatible = "qcom,qcs404-cpr", "qcom,cpr";
> > +               reg = <0x0b018000 0x1000>;
> > +               ....
> > +               vdd-apc-supply = <&pms405_s3>;
> > +               #power-domain-cells = <0>;

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v3 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR
  2019-08-19 10:12   ` [PATCH v3 " Niklas Cassel
  2019-08-19 17:58     ` Stephen Boyd
@ 2019-08-23 12:34     ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2019-08-23 12:34 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Andy Gross, Viresh Kumar, Nishanth Menon, Stephen Boyd,
	linux-arm-msm, Jorge Ramirez-Ortiz, Bjorn Andersson, Ulf Hansson,
	Mark Rutland, open list:THERMAL, devicetree, linux-kernel

On Mon, Aug 19, 2019 at 5:12 AM Niklas Cassel <niklas.cassel@linaro.org> wrote:
>
> Add qcom-opp bindings with properties needed for Core Power Reduction
> (CPR).
>
> CPR is included in a great variety of Qualcomm SoCs, e.g. msm8916 and
> msm8996. CPR was first introduced in msm8974.
>
> Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> ---
> Changes since V2:
> qcom,opp-fuse-level is really a required property and not an optional
> property, so properly define it as such.
>
>  .../devicetree/bindings/opp/qcom-opp.txt      | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH v3 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain
  2019-08-22 10:27       ` Niklas Cassel
@ 2019-08-28 17:52         ` Stephen Boyd
  0 siblings, 0 replies; 31+ messages in thread
From: Stephen Boyd @ 2019-08-28 17:52 UTC (permalink / raw)
  To: Niklas Cassel
  Cc: Andy Gross, Ilia Lin, Nishanth Menon, Viresh Kumar,
	linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Rob Herring, Rob Herring, Mark Rutland, linux-pm, devicetree,
	linux-kernel

Quoting Niklas Cassel (2019-08-22 03:27:23)
> On Mon, Aug 19, 2019 at 10:59:36AM -0700, Stephen Boyd wrote:
> > Quoting Niklas Cassel (2019-08-19 03:09:57)
> > > +
> > > +soc {
> > > +....
> > > +       cprpd: cpr@b018000 {
> > 
> > Maybe node name should be 'avs' for the industry standard adaptive
> > voltage scaling acronym?
> 
> I see where this is coming from, but "git grep avs" gives a single result.
> 
> Also, since the label is cprpd, it doesn't make sense to simply rename the
> node name, and I don't think that avspd would be a good name, since it is
> less correct.
> 
> So if you don't insist, I would prefer to leave it as it is.
> 

How about 'power-controller'? 


^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH v4 06/14] dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain
  2019-08-19 10:09   ` [PATCH v3 " Niklas Cassel
  2019-08-19 17:59     ` Stephen Boyd
@ 2019-08-30 10:29     ` " Niklas Cassel
  1 sibling, 0 replies; 31+ messages in thread
From: Niklas Cassel @ 2019-08-30 10:29 UTC (permalink / raw)
  To: Ilia Lin, Andy Gross, Viresh Kumar, Nishanth Menon, Stephen Boyd
  Cc: linux-arm-msm, jorge.ramirez-ortiz, bjorn.andersson, ulf.hansson,
	Niklas Cassel, Rob Herring, Rob Herring, Mark Rutland, linux-pm,
	devicetree, linux-kernel

Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since V3:
-In Example 2: rename the node name from cpr to power-controller,
and rename the label from cprpd to cpr.

 .../bindings/opp/qcom-nvmem-cpufreq.txt       | 113 +++++++++++++++++-
 1 file changed, 112 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
index c5ea8b90e35d..4751029b9b74 100644
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
@@ -14,7 +14,7 @@ operating-points-v2 table when it is parsed by the OPP framework.
 
 Required properties:
 --------------------
-In 'cpus' nodes:
+In 'cpu' nodes:
 - operating-points-v2: Phandle to the operating-points-v2 table to use.
 
 In 'operating-points-v2' table:
@@ -23,6 +23,15 @@ In 'operating-points-v2' table:
 
 Optional properties:
 --------------------
+In 'cpu' nodes:
+- power-domains: A phandle pointing to the PM domain specifier which provides
+		the performance states available for active state management.
+		Please refer to the power-domains bindings
+		Documentation/devicetree/bindings/power/power_domain.txt
+		and also examples below.
+- power-domain-names: Should be
+	- 'cpr' for qcs404.
+
 In 'operating-points-v2' table:
 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
 		efuse registers that has information about the
@@ -682,3 +691,105 @@ soc {
 		};
 	};
 };
+
+Example 2:
+---------
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			....
+			clocks = <&apcs_glb>;
+			operating-points-v2 = <&cpu_opp_table>;
+			power-domains = <&cpr>;
+			power-domain-names = "cpr";
+		};
+	};
+
+	cpu_opp_table: cpu-opp-table {
+		compatible = "operating-points-v2-kryo-cpu";
+		opp-shared;
+
+		opp-1094400000 {
+			opp-hz = /bits/ 64 <1094400000>;
+			required-opps = <&cpr_opp1>;
+		};
+		opp-1248000000 {
+			opp-hz = /bits/ 64 <1248000000>;
+			required-opps = <&cpr_opp2>;
+		};
+		opp-1401600000 {
+			opp-hz = /bits/ 64 <1401600000>;
+			required-opps = <&cpr_opp3>;
+		};
+	};
+
+	cpr_opp_table: cpr-opp-table {
+		compatible = "operating-points-v2-qcom-level";
+
+		cpr_opp1: opp1 {
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+		};
+		cpr_opp2: opp2 {
+			opp-level = <2>;
+			qcom,opp-fuse-level = <2>;
+		};
+		cpr_opp3: opp3 {
+			opp-level = <3>;
+			qcom,opp-fuse-level = <3>;
+		};
+	};
+
+....
+
+soc {
+....
+	cpr: power-controller@b018000 {
+		compatible = "qcom,qcs404-cpr", "qcom,cpr";
+		reg = <0x0b018000 0x1000>;
+		....
+		vdd-apc-supply = <&pms405_s3>;
+		#power-domain-cells = <0>;
+		operating-points-v2 = <&cpr_opp_table>;
+		....
+	};
+};
-- 
2.21.0


^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, back to index

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-25 10:41 [PATCH v2 00/14] Add support for QCOM Core Power Reduction Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Niklas Cassel
2019-07-26  8:03   ` Viresh Kumar
2019-07-25 10:41 ` [PATCH v2 02/14] dt-bindings: cpufreq: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Niklas Cassel
2019-07-26  8:04   ` Viresh Kumar
2019-07-25 10:41 ` [PATCH v2 03/14] cpufreq: qcom: " Niklas Cassel
2019-08-18  1:06   ` Stephen Boyd
2019-07-25 10:41 ` [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 05/14] cpufreq: qcom: Refactor the driver to make it easier to extend Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 06/14] dt-bindings: cpufreq: qcom-nvmem: Support pstates provided by a power domain Niklas Cassel
2019-08-16 21:21   ` Rob Herring
2019-08-19 10:09   ` [PATCH v3 " Niklas Cassel
2019-08-19 17:59     ` Stephen Boyd
2019-08-22 10:27       ` Niklas Cassel
2019-08-28 17:52         ` Stephen Boyd
2019-08-30 10:29     ` [PATCH v4 06/14] dt-bindings: opp: " Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 07/14] cpufreq: qcom: Add support for qcs404 on nvmem driver Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 08/14] cpufreq: Add qcs404 to cpufreq-dt-platdev blacklist Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 09/14] dt-bindings: opp: Add qcom-opp bindings with properties needed for CPR Niklas Cassel
2019-08-19 10:12   ` [PATCH v3 " Niklas Cassel
2019-08-19 17:58     ` Stephen Boyd
2019-08-23 12:34     ` Rob Herring
2019-07-25 10:41 ` [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Niklas Cassel
2019-08-17  6:14   ` Stephen Boyd
2019-08-22 10:20     ` Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 11/14] " Niklas Cassel
2019-08-18  1:04   ` Stephen Boyd
2019-07-25 10:41 ` [PATCH v2 12/14] arm64: dts: qcom: qcs404: Add CPR and populate OPP table Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 13/14] arm64: defconfig: enable CONFIG_QCOM_CPR Niklas Cassel
2019-07-25 10:41 ` [PATCH v2 14/14] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM Niklas Cassel
2019-07-26  8:08 ` [PATCH v2 00/14] Add support for QCOM Core Power Reduction Viresh Kumar

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