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[84.219.138.247]) by smtp.gmail.com with ESMTPSA id k8sm3758979lja.24.2019.08.22.03.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2019 03:20:04 -0700 (PDT) Date: Thu, 22 Aug 2019 12:20:02 +0200 From: Niklas Cassel To: Stephen Boyd Cc: Jorge Ramirez-Ortiz , linux-arm-msm@vger.kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Message-ID: <20190822102002.GA8494@centauri> References: <20190725104144.22924-1-niklas.cassel@linaro.org> <20190725104144.22924-11-niklas.cassel@linaro.org> <5d579b36.1c69fb81.85eba.ff51@mx.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5d579b36.1c69fb81.85eba.ff51@mx.google.com> User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Archived-At: List-Archive: List-Post: On Fri, Aug 16, 2019 at 11:14:13PM -0700, Stephen Boyd wrote: > Quoting Niklas Cassel (2019-07-25 03:41:38) > > + cpr@b018000 { > > + compatible = "qcom,qcs404-cpr", "qcom,cpr"; > > + reg = <0x0b018000 0x1000>; > > + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; > > + clocks = <&xo_board>; > > + clock-names = "ref"; > > + vdd-apc-supply = <&pms405_s3>; > > + #power-domain-cells = <0>; > > + operating-points-v2 = <&cpr_opp_table>; > > + acc-syscon = <&tcsr>; > > + > > + nvmem-cells = <&cpr_efuse_quot_offset1>, > > + <&cpr_efuse_quot_offset2>, > > + <&cpr_efuse_quot_offset3>, > > + <&cpr_efuse_init_voltage1>, > > + <&cpr_efuse_init_voltage2>, > > + <&cpr_efuse_init_voltage3>, > > + <&cpr_efuse_quot1>, > > + <&cpr_efuse_quot2>, > > + <&cpr_efuse_quot3>, > > + <&cpr_efuse_ring1>, > > + <&cpr_efuse_ring2>, > > + <&cpr_efuse_ring3>, > > + <&cpr_efuse_revision>; > > + nvmem-cell-names = "cpr_quotient_offset1", > > + "cpr_quotient_offset2", > > + "cpr_quotient_offset3", > > + "cpr_init_voltage1", > > + "cpr_init_voltage2", > > + "cpr_init_voltage3", > > + "cpr_quotient1", > > + "cpr_quotient2", > > + "cpr_quotient3", > > + "cpr_ring_osc1", > > + "cpr_ring_osc2", > > + "cpr_ring_osc3", > > + "cpr_fuse_revision"; > > + > > + qcom,cpr-timer-delay-us = <5000>; > > + qcom,cpr-timer-cons-up = <0>; > > + qcom,cpr-timer-cons-down = <2>; > > + qcom,cpr-up-threshold = <1>; > > + qcom,cpr-down-threshold = <3>; > > + qcom,cpr-idle-clocks = <15>; > > + qcom,cpr-gcnt-us = <1>; > > + qcom,vdd-apc-step-up-limit = <1>; > > + qcom,vdd-apc-step-down-limit = <1>; > > Are any of these qcom,* properties going to change for a particular SoC? > They look like SoC config data that should just go into the driver and > change based on the SoC compatible string. > Hello Stephen, thanks a lot for your reviews. I agree with you, will drop these properties from the dt-binding and the driver once I respin the series. I'm hoping to get the cpufreq part of the patch series merged this merge window, so that the patch pile will decrease. Kind regards, Niklas