From: Brian Masney <masneyb@onstation.org> To: agross@kernel.org, robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org, bjorn.andersson@linaro.org Cc: airlied@linux.ie, daniel@ffwll.ch, mark.rutland@arm.com, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, jcrouse@codeaurora.org Subject: [PATCH v7 2/7] dt-bindings: display: msm: gmu: add optional ocmem property Date: Fri, 23 Aug 2019 05:16:32 -0700 Message-ID: <20190823121637.5861-3-masneyb@onstation.org> (raw) In-Reply-To: <20190823121637.5861-1-masneyb@onstation.org> Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and must use the On Chip MEMory (OCMEM) in order to be functional. Add the optional ocmem property to the Adreno Graphics Management Unit bindings. Signed-off-by: Brian Masney <masneyb@onstation.org> --- Changes since v6: - link to gmu-sram in example - add ranges property to ocmem example to match bindings Changes since v5: - rename ocmem property to sram to match what TI currently has. Changes since v4: - None Changes since v3: - correct link to qcom,ocmem.yaml Changes since v2: - Add a3xx example with OCMEM Changes since v1: - None .../devicetree/bindings/display/msm/gmu.txt | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt index 90af5b0a56a9..bf9c7a2a495c 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.txt +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -31,6 +31,10 @@ Required properties: - iommus: phandle to the adreno iommu - operating-points-v2: phandle to the OPP operating points +Optional properties: +- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon + SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml. + Example: / { @@ -63,3 +67,50 @@ Example: operating-points-v2 = <&gmu_opp_table>; }; }; + +a3xx example with OCMEM support: + +/ { + ... + + gpu: adreno@fdb00000 { + compatible = "qcom,adreno-330.2", + "qcom,adreno"; + reg = <0xfdb00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem_iface"; + clocks = <&mmcc OXILI_GFX3D_CLK>, + <&mmcc OXILICX_AHB_CLK>, + <&mmcc OXILICX_AXI_CLK>; + sram = <&gmu_sram>; + power-domains = <&mmcc OXILICX_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 0>; + }; + + ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x180000>; + reg-names = "ctrl", + "mem"; + + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", + "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x100000>; + ranges = <0 0 0xfec00000 0x100000>; + }; + }; +}; -- 2.21.0
next prev parent reply index Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-23 12:16 [PATCH v7 0/7] qcom: add OCMEM support Brian Masney 2019-08-23 12:16 ` [PATCH v7 1/7] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings Brian Masney 2019-08-23 12:16 ` Brian Masney [this message] 2019-08-27 12:21 ` [PATCH v7 2/7] dt-bindings: display: msm: gmu: add optional ocmem property Rob Herring 2019-08-23 12:16 ` [PATCH v7 3/7] firmware: qcom: scm: add OCMEM lock/unlock interface Brian Masney 2019-08-23 12:16 ` [PATCH v7 4/7] firmware: qcom: scm: add support to restore secure config to qcm_scm-32 Brian Masney 2019-08-23 12:16 ` [PATCH v7 5/7] soc: qcom: add OCMEM driver Brian Masney 2019-08-23 12:16 ` [PATCH v7 6/7] drm/msm/gpu: add ocmem init/cleanup functions Brian Masney 2019-08-28 15:12 ` [Freedreno] " Jordan Crouse 2019-08-23 12:16 ` [PATCH v7 7/7] ARM: qcom_defconfig: add ocmem support Brian Masney 2019-09-01 21:40 ` [PATCH v7 0/7] qcom: add OCMEM support Brian Masney
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