From: Douglas Anderson <dianders@chromium.org>
To: Rob Herring <robh@kernel.org>, Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <sboyd@kernel.org>
Cc: Jeffrey Hugo <jhugo@codeaurora.org>,
Taniya Das <tdas@codeaurora.org>,
jeffrey.l.hugo@gmail.com, linux-arm-msm@vger.kernel.org,
harigovi@codeaurora.org, devicetree@vger.kernel.org,
mka@chromium.org, kalyan_t@codeaurora.org,
Mark Rutland <mark.rutland@arm.com>,
linux-clk@vger.kernel.org, hoegsberg@chromium.org,
Douglas Anderson <dianders@chromium.org>,
Stephen Boyd <swboyd@chromium.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 05/15] clk: qcom: Get rid of the test clock for dispcc-sc7180
Date: Mon, 3 Feb 2020 10:31:38 -0800
Message-ID: <20200203103049.v4.5.I28ac8f801456f1b950f7da10ed0f74a1344d4a35@changeid> (raw)
In-Reply-To: <20200203183149.73842-1-dianders@chromium.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v4: None
Changes in v3:
- Patch ("clk: qcom: Get rid of the test...dispcc-sc7180") split out for v3.
Changes in v2: None
drivers/clk/qcom/dispcc-sc7180.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index a820e1558677..397f5d9dafc8 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -76,38 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dp_phy_pll_link_clk" },
{ .fw_name = "dp_phy_pll_vco_div_clk" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_byteclk" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
@@ -115,7 +109,6 @@ static const struct parent_map disp_cc_parent_map_3[] = {
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
@@ -123,31 +116,26 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
{ .hw = &disp_cc_pll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
@@ -166,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
- .num_parents = 3,
+ .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -180,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 3,
+ .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -213,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -227,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -241,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = 3,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
@@ -256,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 3,
+ .num_parents = 2,
.ops = &clk_rcg2_ops,
},
};
@@ -279,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 5,
+ .num_parents = 4,
.ops = &clk_rcg2_shared_ops,
},
};
@@ -292,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
- .num_parents = 3,
+ .num_parents = 2,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
@@ -307,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 5,
+ .num_parents = 4,
.ops = &clk_rcg2_shared_ops,
},
};
@@ -321,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
- .num_parents = 2,
+ .num_parents = 1,
.ops = &clk_rcg2_shared_ops,
},
};
--
2.25.0.341.g760bfbb309-goog
next prev parent reply index
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-03 18:31 [PATCH v4 00/15] clk: qcom: Fix parenting for dispcc/gpucc/videocc Douglas Anderson
2020-02-03 18:31 ` [PATCH v4 01/15] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Douglas Anderson
2020-02-04 17:47 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 02/15] dt-bindings: clock: Fix qcom,dispcc bindings for sdm845/sc7180 Douglas Anderson
2020-02-04 17:47 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 03/15] arm64: dts: qcom: sdm845: Add the missing clocks on the dispcc Douglas Anderson
2020-02-03 18:31 ` [PATCH v4 04/15] clk: qcom: Get rid of fallback global names for dispcc-sc7180 Douglas Anderson
2020-02-04 17:47 ` Stephen Boyd
2020-02-03 18:31 ` Douglas Anderson [this message]
2020-02-04 17:47 ` [PATCH v4 05/15] clk: qcom: Get rid of the test clock " Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 06/15] clk: qcom: Use ARRAY_SIZE in dispcc-sc7180 for parent clocks Douglas Anderson
2020-02-04 17:48 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 07/15] dt-bindings: clock: Fix qcom,gpucc bindings for sdm845/sc7180/msm8998 Douglas Anderson
2020-02-04 17:48 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 08/15] arm64: dts: qcom: sdm845: Add missing clocks / fix names on the gpucc Douglas Anderson
2020-02-03 18:31 ` [PATCH v4 09/15] clk: qcom: Get rid of the test clock for gpucc-sc7180 Douglas Anderson
2020-02-04 17:48 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 10/15] clk: qcom: Use ARRAY_SIZE in gpucc-sc7180 for parent clocks Douglas Anderson
2020-02-04 17:48 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 11/15] dt-bindings: clock: Cleanup qcom,videocc bindings for sdm845/sc7180 Douglas Anderson
2020-02-04 17:48 ` Stephen Boyd
2020-02-04 20:49 ` Doug Anderson
2020-02-03 18:31 ` [PATCH v4 12/15] clk: qcom: Get rid of the test clock for videocc-sc7180 Douglas Anderson
2020-02-04 17:49 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 13/15] clk: qcom: Use ARRAY_SIZE in videocc-sc7180 for parent clocks Douglas Anderson
2020-02-04 17:49 ` Stephen Boyd
2020-02-03 18:31 ` [PATCH v4 14/15] arm64: dts: qcom: sdm845: Add the missing clock on the videocc Douglas Anderson
2020-02-03 18:31 ` [PATCH v4 15/15] arm64: dts: sc7180: Add clock controller nodes Douglas Anderson
2020-02-03 19:30 ` [PATCH v4 00/15] clk: qcom: Fix parenting for dispcc/gpucc/videocc Stephen Boyd
2020-02-03 19:41 ` Doug Anderson
2020-02-03 20:04 ` Bjorn Andersson
2020-02-03 20:48 ` Doug Anderson
2020-02-03 23:17 ` Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200203103049.v4.5.I28ac8f801456f1b950f7da10ed0f74a1344d4a35@changeid \
--to=dianders@chromium.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=harigovi@codeaurora.org \
--cc=hoegsberg@chromium.org \
--cc=jeffrey.l.hugo@gmail.com \
--cc=jhugo@codeaurora.org \
--cc=kalyan_t@codeaurora.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mka@chromium.org \
--cc=mturquette@baylibre.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=swboyd@chromium.org \
--cc=tdas@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Linux-ARM-MSM Archive on lore.kernel.org
Archives are clonable:
git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git
# If you have public-inbox 1.1+ installed, you may
# initialize and index your mirror using the following commands:
public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
linux-arm-msm@vger.kernel.org
public-inbox-index linux-arm-msm
Example config snippet for mirrors
Newsgroup available over NNTP:
nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git