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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h3sm9379345pfo.102.2020.02.03.15.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 15:35:19 -0800 (PST) Date: Mon, 3 Feb 2020 15:35:17 -0800 From: Bjorn Andersson To: Douglas Anderson Cc: Andrzej Hajda , Neil Armstrong , robdclark@chromium.org, linux-arm-msm@vger.kernel.org, seanpaul@chromium.org, Jeffrey Hugo , Daniel Vetter , Rob Clark , Jonas Karlman , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Jernej Skrabec , Laurent Pinchart Subject: Re: [PATCH v3 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Message-ID: <20200203233517.GE311651@builder> References: <20191218223530.253106-1-dianders@chromium.org> <20191218143416.v3.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191218143416.v3.5.Idbd0051d0de53f7e9d18a291ea33011c0854fcc6@changeid> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote: > At least one panel hooked up to the bridge (AUO B116XAK01) only > supports 1 lane of DP. Let's read this information and stop > hardcoding 4 DP lanes. > > Signed-off-by: Douglas Anderson > Tested-by: Rob Clark > Reviewed-by: Rob Clark Reviewed-by: Bjorn Andersson > --- > > Changes in v3: None > Changes in v2: None > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 32 +++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index d55d19759796..0fc9e97b2d98 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -313,8 +313,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge) > goto err_dsi_host; > } > > - /* TODO: setting to 4 lanes always for now */ > - pdata->dp_lanes = 4; > + /* TODO: setting to 4 MIPI lanes always for now */ > dsi->lanes = 4; > dsi->format = MIPI_DSI_FMT_RGB888; > dsi->mode_flags = MIPI_DSI_MODE_VIDEO; > @@ -511,12 +510,41 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata) > usleep_range(10000, 10500); /* 10ms delay recommended by spec */ > } > > +static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata) > +{ > + u8 data; > + int ret; > + > + ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); > + if (ret != 1) { > + DRM_DEV_ERROR(pdata->dev, > + "Can't read lane count (%d); assuming 4\n", ret); > + return 4; > + } > + > + return data & DP_LANE_COUNT_MASK; > +} > + > static void ti_sn_bridge_enable(struct drm_bridge *bridge) > { > struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge); > unsigned int val; > int ret; > > + /* > + * Run with the maximum number of lanes that the DP sink supports. > + * > + * Depending use cases, we might want to revisit this later because: > + * - It's plausible that someone may have run fewer lines to the > + * sink than the sink actually supports, assuming that the lines > + * will just be driven at a higher rate. > + * - The DP spec seems to indicate that it's more important to minimize > + * the number of lanes than the link rate. > + * > + * If we do revisit, it would be important to measure the power impact. > + */ > + pdata->dp_lanes = ti_sn_get_max_lanes(pdata); > + > /* DSI_A lane config */ > val = CHA_DSI_LANES(4 - pdata->dsi->lanes); > regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, > -- > 2.24.1.735.g03f4e72817-goog >