From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
robdclark@chromium.org, linux-arm-msm@vger.kernel.org,
seanpaul@chromium.org, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, Rob Clark <robdclark@gmail.com>,
Jonas Karlman <jonas@kwiboo.se>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can
Date: Mon, 3 Feb 2020 15:37:11 -0800 [thread overview]
Message-ID: <20200203233711.GF311651@builder> (raw)
In-Reply-To: <20191218143416.v3.6.Iaf8d698f4e5253d658ae283d2fd07268076a7c27@changeid>
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> The current bridge driver always forced us to use 24 bits per pixel
> over the DP link. This is a waste if you are hooked up to a panel
> that only supports 6 bits per color or fewer, since in that case you
> ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
s/ran/can/
>
> Let's support this.
>
> While at it, let's clean up the math in the function to avoid rounding
> errors (and round in the correct direction when we have to round).
> Numbers are sufficiently small (because mode->clock is in kHz) that we
> don't need to worry about integer overflow.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Rob Clark <robdclark@gmail.com>
> Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 27 ++++++++++++++++++---------
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 0fc9e97b2d98..d5990a0947b9 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -51,6 +51,7 @@
> #define SN_ENH_FRAME_REG 0x5A
> #define VSTREAM_ENABLE BIT(3)
> #define SN_DATA_FORMAT_REG 0x5B
> +#define BPP_18_RGB BIT(0)
> #define SN_HPD_DISABLE_REG 0x5C
> #define HPD_DISABLE BIT(0)
> #define SN_AUX_WDATA_REG(x) (0x64 + (x))
> @@ -436,6 +437,14 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
> regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> }
>
> +static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
> +{
> + if (pdata->connector.display_info.bpc <= 6)
> + return 18;
> + else
> + return 24;
> +}
> +
> /**
> * LUT index corresponds to register value and
> * LUT values corresponds to dp data rate supported
> @@ -447,21 +456,17 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
>
> static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
> {
> - unsigned int bit_rate_mhz, dp_rate_mhz;
> + unsigned int bit_rate_khz, dp_rate_mhz;
> unsigned int i;
> struct drm_display_mode *mode =
> &pdata->bridge.encoder->crtc->state->adjusted_mode;
>
> - /*
> - * Calculate minimum bit rate based on our pixel clock. At
> - * the moment this driver never sets the DP_18BPP_EN bit in
> - * register 0x5b so we hardcode 24bpp.
> - */
> - bit_rate_mhz = (mode->clock / 1000) * 24;
> + /* Calculate minimum bit rate based on our pixel clock. */
> + bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
>
> /* Calculate minimum DP data rate, taking 80% as per DP spec */
> - dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
> - DP_CLK_FUDGE_DEN;
> + dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
> + 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
>
> for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
> if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
> @@ -550,6 +555,10 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
> CHA_DSI_LANES_MASK, val);
>
> + /* Set the DP output format (18 bpp or 24 bpp) */
> + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
> + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
> +
> /* DP lane config */
> val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
> regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
> --
> 2.24.1.735.g03f4e72817-goog
>
next prev parent reply other threads:[~2020-02-03 23:37 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 22:35 [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson
2019-12-18 22:35 ` [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson
2020-02-03 23:31 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson
2020-02-03 23:32 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson
2020-02-03 23:33 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson
2020-02-03 23:34 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson
2020-02-03 23:35 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson
2020-02-03 23:37 ` Bjorn Andersson [this message]
2020-02-04 0:21 ` Doug Anderson
2020-02-12 23:04 ` Doug Anderson
2020-02-13 9:17 ` Neil Armstrong
[not found] ` <20200710011935.GA7056@gentoo.org>
2020-07-10 1:38 ` Doug Anderson
2020-07-10 2:14 ` Doug Anderson
2020-07-10 3:12 ` Steev Klimaszewski
2020-07-10 3:17 ` Steev Klimaszewski
2020-07-10 3:43 ` Steev Klimaszewski
2020-07-10 4:12 ` Doug Anderson
2020-07-10 6:15 ` Steev Klimaszewski
2020-07-10 14:16 ` Rob Clark
2020-07-10 14:47 ` Doug Anderson
2020-07-10 17:10 ` Steev Klimaszewski
2020-07-14 15:31 ` Doug Anderson
2020-09-02 14:37 ` Doug Anderson
2019-12-18 22:35 ` [PATCH v3 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson
2020-02-03 23:39 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson
2020-02-03 23:41 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson
2020-02-03 23:43 ` Bjorn Andersson
2020-01-06 22:47 ` [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Doug Anderson
2020-02-03 23:45 ` Bjorn Andersson
2020-02-13 9:51 ` Neil Armstrong
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