Linux-ARM-MSM Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH 0/5] Add initial support for SDM660/630 SoCs
@ 2020-02-12 17:09 Alexey Minnekhanov
  2020-02-12 17:09 ` [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi Alexey Minnekhanov
                   ` (4 more replies)
  0 siblings, 5 replies; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree, Alexey Minnekhanov

This patchset adds some minimal device tree
support for Qualcomm Snapdragon 660/630 SoCs.

Alexey Minnekhanov (5):
  dt-bindings: Add vendor prefix for Xiaomi
  dt-bindings: arm: Add kryo260 compatible
  dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs
  arm64: dts: qcom: Add SDM660 SoC support
  arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender)

 .../devicetree/bindings/arm/cpus.yaml         |   1 +
 .../devicetree/bindings/arm/qcom.yaml         |   2 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sdm660-xiaomi-lavender.dts  |  42 ++
 arch/arm64/boot/dts/qcom/sdm660.dtsi          | 373 ++++++++++++++++++
 6 files changed, 421 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660.dtsi

-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi
  2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
@ 2020-02-12 17:09 ` Alexey Minnekhanov
  2020-02-19 22:20   ` Rob Herring
  2020-02-12 17:09 ` [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible Alexey Minnekhanov
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree, Alexey Minnekhanov

Xiaomi Corporation is a Chinese electronics company.

Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6046f4555852..7cef5ee734d6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1054,6 +1054,8 @@ patternProperties:
     description: X-Powers
   "^xes,.*":
     description: Extreme Engineering Solutions (X-ES)
+  "^xiaomi,.*":
+    description: Xiaomi Technology Co., Ltd.
   "^xillybus,.*":
     description: Xillybus Ltd.
   "^xlnx,.*":
-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible
  2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
  2020-02-12 17:09 ` [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi Alexey Minnekhanov
@ 2020-02-12 17:09 ` Alexey Minnekhanov
  2020-02-19 22:21   ` Rob Herring
  2020-02-12 17:09 ` [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree, Alexey Minnekhanov

Kryo260 is found in SDM660, so add it in list of cpu compatibles

Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
 Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index c23c24ff7575..d994c066a8bd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -155,6 +155,7 @@ properties:
       - nvidia,tegra194-carmel
       - qcom,krait
       - qcom,kryo
+      - qcom,kryo260
       - qcom,kryo385
       - qcom,kryo485
       - qcom,scorpion
-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs
  2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
  2020-02-12 17:09 ` [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi Alexey Minnekhanov
  2020-02-12 17:09 ` [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible Alexey Minnekhanov
@ 2020-02-12 17:09 ` Alexey Minnekhanov
  2020-02-19 22:20   ` Rob Herring
  2020-02-12 17:09 ` [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
  2020-02-12 17:09 ` [PATCH 5/5] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender) Alexey Minnekhanov
  4 siblings, 1 reply; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree, Alexey Minnekhanov

Add a SoC strings for the Qualcomm SDM630 and SDM660 SoCs.
Also document the new xiaomi,lavender compatible used in
a device tree binding.

Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 529d924931f1..c5af92acd427 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -36,6 +36,8 @@ description: |
         msm8994
         msm8996
         sc7180
+        sdm630
+        sdm660
         sdm845
 
   The 'board' element must be one of the following strings:
@@ -125,6 +127,11 @@ properties:
               - samsung,a5u-eur
           - const: qcom,msm8916
 
+      - items:
+          - enum:
+              - xiaomi,lavender
+          - const: qcom,sdm660
+
       - items:
           - const: qcom,msm8996-mtp
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support
  2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
                   ` (2 preceding siblings ...)
  2020-02-12 17:09 ` [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
@ 2020-02-12 17:09 ` Alexey Minnekhanov
  2020-02-20  7:06   ` Bjorn Andersson
  2020-02-12 17:09 ` [PATCH 5/5] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender) Alexey Minnekhanov
  4 siblings, 1 reply; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree,
	Alexey Minnekhanov, Craig Tatlor

Initial device tree support for Qualcomm SDM660 SoC.

SDM660 is based off MSM8998 and uses some of its drivers.
SDM630/636 are based off SDM660 SoC and they are pin
and software compatible.

The device tree is based on the CAF 4.4 kernel tree.

Features:
 * CPU nodes
 * Timer nodes
 * Interrupt controller
 * Global Clock Controller
 * Top Level Mode Multiplexer (pin controller)
 * UART node

This is inspired by and based on the work of Craig Tatlor in
https://patchwork.kernel.org/patch/10563667/

Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
 arch/arm64/boot/dts/qcom/sdm660.dtsi | 373 +++++++++++++++++++++++++++
 1 file changed, 373 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
new file mode 100644
index 000000000000..1187f2f98bd0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, Craig Tatlor.
+ * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+			};
+			L1_I_100: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_100: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU1: cpu@101 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			L1_I_101: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_101: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU2: cpu@102 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x102>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			L1_I_102: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_102: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU3: cpu@103 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x103>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1024>;
+			next-level-cache = <&L2_1>;
+			L1_I_103: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_103: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU4: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <640>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+			};
+			L1_I_0: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_0: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU5: cpu@1 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <640>;
+			next-level-cache = <&L2_0>;
+			L1_I_1: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_1: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU6: cpu@2 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <640>;
+			next-level-cache = <&L2_0>;
+			L1_I_2: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_2: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		CPU7: cpu@3 {
+			device_type = "cpu";
+			compatible = "qcom,kryo260";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <640>;
+			next-level-cache = <&L2_0>;
+			L1_I_3: l1-icache {
+				compatible = "cache";
+			};
+			L1_D_3: l1-dcache {
+				compatible = "cache";
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0 0 0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	soc: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,gcc-sdm660";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			reg = <0x00100000 0x94000>;
+		};
+
+		tlmm: pinctrl@3100000 {
+			compatible = "qcom,sdm660-pinctrl";
+			reg = <0x03100000 0x400000>,
+			      <0x03500000 0x400000>,
+			      <0x03900000 0x400000>;
+			reg-names = "south", "center", "north";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 114>;
+			gpio-reserved-ranges = <8 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart_console_active: uart_console_active {
+				pinmux {
+					pins = "gpio4", "gpio5";
+					function = "blsp_uart2";
+				};
+
+				pinconf {
+					pins = "gpio4", "gpio5";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		spmi_bus: spmi@800f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0800f000 0x1000>,
+			      <0x08400000 0x1000000>,
+			      <0x09400000 0x1000000>,
+			      <0x0a400000 0x220000>,
+			      <0x0800a000 0x3000>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			cell-index = <0>;
+		};
+
+		blsp1_uart2: serial@c170000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x0c170000 0x1000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		timer@17920000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x17920000 0x1000>;
+
+			frame@17921000 {
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17921000 0x1000>,
+				      <0x17922000 0x1000>;
+			};
+
+			frame@17923000 {
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17923000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17924000 {
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17924000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17925000 {
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17925000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17926000 {
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17926000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17927000 {
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17927000 0x1000>;
+				status = "disabled";
+			};
+
+			frame@17928000 {
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x17928000 0x1000>;
+				status = "disabled";
+			};
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x17a00000 0x10000>,
+			      <0x17b00000 0x100000>;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 5/5] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender)
  2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
                   ` (3 preceding siblings ...)
  2020-02-12 17:09 ` [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
@ 2020-02-12 17:09 ` Alexey Minnekhanov
  4 siblings, 0 replies; 10+ messages in thread
From: Alexey Minnekhanov @ 2020-02-12 17:09 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson
  Cc: linux-arm-msm, Rob Herring, Mark Rutland, devicetree, Alexey Minnekhanov

This adds the initial device tree support for Xiaomi
Redmi Note 7 (lavender) phone. It is based on SDM660
SoC. Currently it can be booted into initrd with a
shell over UART and you can get kernel boot logs
from a pstore-ramoops.

Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
 arch/arm64/boot/dts/qcom/Makefile             |  1 +
 .../boot/dts/qcom/sdm660-xiaomi-lavender.dts  | 42 +++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 973c0f079659..a61b1089bd9a 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sdm660-xiaomi-lavender.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
new file mode 100644
index 000000000000..676efba0e16b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sdm660.dtsi"
+
+/ {
+	model = "Xiaomi Redmi Note 7";
+	compatible = "xiaomi,lavender", "qcom,sdm660";
+
+	aliases {
+		serial0 = &blsp1_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ramoops@a0000000 {
+			compatible = "ramoops";
+			reg = <0x0 0xa0000000 0x0 0x400000>;
+			console-size = <0x20000>;
+			record-size = <0x20000>;
+			ftrace-size = <0x0>;
+			pmsg-size = <0x20000>;
+		};
+	};
+};
+
+&blsp1_uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart_console_active>;
+};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs
  2020-02-12 17:09 ` [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
@ 2020-02-19 22:20   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-02-19 22:20 UTC (permalink / raw)
  To: Alexey Minnekhanov
  Cc: Andy Gross, Bjorn Andersson, linux-arm-msm, Mark Rutland, devicetree

On Wed, Feb 12, 2020 at 08:09:14PM +0300, Alexey Minnekhanov wrote:
> Add a SoC strings for the Qualcomm SDM630 and SDM660 SoCs.
> Also document the new xiaomi,lavender compatible used in
> a device tree binding.
> 
> Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 529d924931f1..c5af92acd427 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -36,6 +36,8 @@ description: |
>          msm8994
>          msm8996
>          sc7180
> +        sdm630
> +        sdm660
>          sdm845
>  
>    The 'board' element must be one of the following strings:
> @@ -125,6 +127,11 @@ properties:
>                - samsung,a5u-eur
>            - const: qcom,msm8916
>  
> +      - items:
> +          - enum:
> +              - xiaomi,lavender
> +          - const: qcom,sdm660

I think you want to keep this sorted by the compatible string and not be 
in the middle of msm89xx.

> +
>        - items:
>            - const: qcom,msm8996-mtp
>  
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi
  2020-02-12 17:09 ` [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi Alexey Minnekhanov
@ 2020-02-19 22:20   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-02-19 22:20 UTC (permalink / raw)
  To: Alexey Minnekhanov
  Cc: Andy Gross, Bjorn Andersson, linux-arm-msm, Mark Rutland,
	devicetree, Alexey Minnekhanov

On Wed, 12 Feb 2020 20:09:12 +0300, Alexey Minnekhanov wrote:
> Xiaomi Corporation is a Chinese electronics company.
> 
> Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Applied, thanks.

Rob

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible
  2020-02-12 17:09 ` [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible Alexey Minnekhanov
@ 2020-02-19 22:21   ` Rob Herring
  0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-02-19 22:21 UTC (permalink / raw)
  To: Alexey Minnekhanov
  Cc: Andy Gross, Bjorn Andersson, linux-arm-msm, Mark Rutland,
	devicetree, Alexey Minnekhanov

On Wed, 12 Feb 2020 20:09:13 +0300, Alexey Minnekhanov wrote:
> Kryo260 is found in SDM660, so add it in list of cpu compatibles
> 
> Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Applied, thanks.

Rob

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support
  2020-02-12 17:09 ` [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
@ 2020-02-20  7:06   ` Bjorn Andersson
  0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2020-02-20  7:06 UTC (permalink / raw)
  To: Alexey Minnekhanov
  Cc: Andy Gross, linux-arm-msm, Rob Herring, Mark Rutland, devicetree,
	Craig Tatlor

On Wed 12 Feb 09:09 PST 2020, Alexey Minnekhanov wrote:

> Initial device tree support for Qualcomm SDM660 SoC.
> 
> SDM660 is based off MSM8998 and uses some of its drivers.
> SDM630/636 are based off SDM660 SoC and they are pin
> and software compatible.
> 
> The device tree is based on the CAF 4.4 kernel tree.
> 
> Features:
>  * CPU nodes
>  * Timer nodes
>  * Interrupt controller
>  * Global Clock Controller
>  * Top Level Mode Multiplexer (pin controller)
>  * UART node
> 
> This is inspired by and based on the work of Craig Tatlor in
> https://patchwork.kernel.org/patch/10563667/
> 
> Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
> Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>

The content of the patch looks good, but with the S-o-b like this (which
looks correct) the author of the patch should be Craig - which
would/should be noted by a From: Craig at the beginning of the body.

Can you please update this patch accordingly and resend the two dts
patches?

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sdm660.dtsi | 373 +++++++++++++++++++++++++++
>  1 file changed, 373 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sdm660.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
> new file mode 100644
> index 000000000000..1187f2f98bd0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
> @@ -0,0 +1,373 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2018, Craig Tatlor.
> + * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-sdm660.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	chosen { };
> +
> +	clocks {
> +		xo_board: xo_board {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <19200000>;
> +			clock-output-names = "xo_board";
> +		};
> +
> +		sleep_clk: sleep_clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <32764>;
> +			clock-output-names = "sleep_clk";
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +			next-level-cache = <&L2_1>;
> +			L2_1: l2-cache {
> +				compatible = "cache";
> +				cache-level = <2>;
> +			};
> +			L1_I_100: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_100: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU1: cpu@101 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x101>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +			next-level-cache = <&L2_1>;
> +			L1_I_101: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_101: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU2: cpu@102 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x102>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +			next-level-cache = <&L2_1>;
> +			L1_I_102: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_102: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU3: cpu@103 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x103>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <1024>;
> +			next-level-cache = <&L2_1>;
> +			L1_I_103: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_103: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU4: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <640>;
> +			next-level-cache = <&L2_0>;
> +			L2_0: l2-cache {
> +				compatible = "cache";
> +				cache-level = <2>;
> +			};
> +			L1_I_0: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_0: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU5: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <640>;
> +			next-level-cache = <&L2_0>;
> +			L1_I_1: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_1: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU6: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x2>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <640>;
> +			next-level-cache = <&L2_0>;
> +			L1_I_2: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_2: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		CPU7: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "qcom,kryo260";
> +			reg = <0x0 0x3>;
> +			enable-method = "psci";
> +			capacity-dmips-mhz = <640>;
> +			next-level-cache = <&L2_0>;
> +			L1_I_3: l1-icache {
> +				compatible = "cache";
> +			};
> +			L1_D_3: l1-dcache {
> +				compatible = "cache";
> +			};
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&CPU4>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU5>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU6>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU7>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&CPU0>;
> +				};
> +
> +				core1 {
> +					cpu = <&CPU1>;
> +				};
> +
> +				core2 {
> +					cpu = <&CPU2>;
> +				};
> +
> +				core3 {
> +					cpu = <&CPU3>;
> +				};
> +			};
> +		};
> +	};
> +
> +	firmware {
> +		scm {
> +			compatible = "qcom,scm";
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		/* We expect the bootloader to fill in the reg */
> +		reg = <0 0 0 0>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	soc: soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
> +		compatible = "simple-bus";
> +
> +		gcc: clock-controller@100000 {
> +			compatible = "qcom,gcc-sdm660";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +			reg = <0x00100000 0x94000>;
> +		};
> +
> +		tlmm: pinctrl@3100000 {
> +			compatible = "qcom,sdm660-pinctrl";
> +			reg = <0x03100000 0x400000>,
> +			      <0x03500000 0x400000>,
> +			      <0x03900000 0x400000>;
> +			reg-names = "south", "center", "north";
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			gpio-ranges = <&tlmm 0 0 114>;
> +			gpio-reserved-ranges = <8 4>;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart_console_active: uart_console_active {
> +				pinmux {
> +					pins = "gpio4", "gpio5";
> +					function = "blsp_uart2";
> +				};
> +
> +				pinconf {
> +					pins = "gpio4", "gpio5";
> +					drive-strength = <2>;
> +					bias-disable;
> +				};
> +			};
> +		};
> +
> +		spmi_bus: spmi@800f000 {
> +			compatible = "qcom,spmi-pmic-arb";
> +			reg = <0x0800f000 0x1000>,
> +			      <0x08400000 0x1000000>,
> +			      <0x09400000 0x1000000>,
> +			      <0x0a400000 0x220000>,
> +			      <0x0800a000 0x3000>;
> +			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> +			interrupt-names = "periph_irq";
> +			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
> +			qcom,ee = <0>;
> +			qcom,channel = <0>;
> +			#address-cells = <2>;
> +			#size-cells = <0>;
> +			interrupt-controller;
> +			#interrupt-cells = <4>;
> +			cell-index = <0>;
> +		};
> +
> +		blsp1_uart2: serial@c170000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x0c170000 0x1000>;
> +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> +				 <&gcc GCC_BLSP1_AHB_CLK>;
> +			clock-names = "core", "iface";
> +			status = "disabled";
> +		};
> +
> +		timer@17920000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0x17920000 0x1000>;
> +
> +			frame@17921000 {
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17921000 0x1000>,
> +				      <0x17922000 0x1000>;
> +			};
> +
> +			frame@17923000 {
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17923000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17924000 {
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17924000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17925000 {
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17925000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17926000 {
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17926000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17927000 {
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17927000 0x1000>;
> +				status = "disabled";
> +			};
> +
> +			frame@17928000 {
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				reg = <0x17928000 0x1000>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		intc: interrupt-controller@17a00000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x17a00000 0x10000>,
> +			      <0x17b00000 0x100000>;
> +			#interrupt-cells = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			interrupt-controller;
> +			#redistributor-regions = <1>;
> +			redistributor-stride = <0x0 0x20000>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +};
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, back to index

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-12 17:09 [PATCH 0/5] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
2020-02-12 17:09 ` [PATCH 1/5] dt-bindings: Add vendor prefix for Xiaomi Alexey Minnekhanov
2020-02-19 22:20   ` Rob Herring
2020-02-12 17:09 ` [PATCH 2/5] dt-bindings: arm: Add kryo260 compatible Alexey Minnekhanov
2020-02-19 22:21   ` Rob Herring
2020-02-12 17:09 ` [PATCH 3/5] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
2020-02-19 22:20   ` Rob Herring
2020-02-12 17:09 ` [PATCH 4/5] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
2020-02-20  7:06   ` Bjorn Andersson
2020-02-12 17:09 ` [PATCH 5/5] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender) Alexey Minnekhanov

Linux-ARM-MSM Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
		linux-arm-msm@vger.kernel.org
	public-inbox-index linux-arm-msm

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git