From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC67FC3F2D1 for ; Tue, 3 Mar 2020 17:13:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92D1D20873 for ; Tue, 3 Mar 2020 17:13:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Du9Qu22z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729849AbgCCRL7 (ORCPT ); Tue, 3 Mar 2020 12:11:59 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:45746 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729859AbgCCRL6 (ORCPT ); Tue, 3 Mar 2020 12:11:58 -0500 Received: by mail-wr1-f65.google.com with SMTP id v2so5274347wrp.12 for ; Tue, 03 Mar 2020 09:11:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x14DHuiChMvzSWsadrwnTIhfZ4wDDTTqWq8bf9unaaI=; b=Du9Qu22ztUZjSTVSiL24pPM+euHVU9XNSZ1i3LWBzI0AUSm/Ao+kgcYmbbdt5pvhsP 6QC93teKVb/8161KXakzCUEOaIX2xn1MQivBG2gac2uWTIrf+taYOXXZ8FbSeLhFrMSH kMhpq4LM6M7QAG94hMiPypRM4D6JhfBSqJuP4BkKtGbuS18lYjuGbkB8lfsutFxN2oXm XR6AyM3z3migAlB1dadLIRI4pUI0qYk605ohUdyjVf+ZAHVmMnNksAXC1p+7ULdaPMQn wEh8nekBmI2nUIYS3KdAsKxyU+eT5VZuw5ZrYi7t0LUZMNcFKwtuewH2kmOpPdKlsUGF Fhnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x14DHuiChMvzSWsadrwnTIhfZ4wDDTTqWq8bf9unaaI=; b=Uz6x7WFMTOc8vB3H0C/2ezmm2pjKLpYAgOg/Cw0y4Wkcgcu3QFveKWju6A9idGuZBc Vlwh0QJ1ED61vqVPETg4UY3BmJnfvbP7Oy6blwzoN9qZiPm/yOs6nhdUIy1dFdvmsde+ o2sSsRRlzjcW8HI7sD8yQz2IsNtX+HvwTIOO3GijJ7GlMnuoY+vv+iR1AUygG2CDoEx+ Ea513J4zKtvG/l5zzlrXH2TSBPSQQcCJyFqpe3cYK/Iz1j8waz4evoUyxYjJFIPyPB+t 36DPedOXwcaVLoGNemKJJP1xvdSHKAoEo+swExjnUkQ+uyL7DAt1/5k4T+A1cdhZhwes DJNg== X-Gm-Message-State: ANhLgQ1bp8AU+YCmE2OjBNTOZAbytcWGkAgPsUwtTTha1hkjzg+RNnAM Dye+rFynLP3oift0TmIx89lxI1Jr4pI= X-Google-Smtp-Source: ADFU+vvAPi7jejs+NNjZQAyc2iu811clxwle31yQJY1UjLIPta/ye65qm3YuHtGd6NdgYrCY6eJuEQ== X-Received: by 2002:adf:9cca:: with SMTP id h10mr6767695wre.390.1583255516296; Tue, 03 Mar 2020 09:11:56 -0800 (PST) Received: from localhost.localdomain ([176.61.57.127]) by smtp.gmail.com with ESMTPSA id z13sm5425319wrw.88.2020.03.03.09.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2020 09:11:55 -0800 (PST) From: Bryan O'Donoghue To: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: linux-kernel@vger.kernel.org, Jorge Ramirez-Ortiz , Jorge Ramirez-Ortiz , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, Bryan O'Donoghue Subject: [PATCH v7 04/18] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings Date: Tue, 3 Mar 2020 17:11:45 +0000 Message-Id: <20200303171159.246992-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200303171159.246992-1-bryan.odonoghue@linaro.org> References: <20200303171159.246992-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jorge Ramirez-Ortiz Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY appears in a number of SoCs on various flavors of 20nm and 28nm nodes. This commit adds information related to the 28nm node only. Based on Sriharsha Allenki's original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Rob Herring Cc: Mark Rutland Cc: Bjorn Andersson Cc: Jorge Ramirez-Ortiz Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Bryan O'Donoghue --- .../devicetree/bindings/phy/qcom,usb-ss.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml new file mode 100644 index 000000000000..bd1388d62ce0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,usb-ss.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY + +properties: + compatible: + enum: + - qcom,usb-ss-28nm-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmcc clock + - description: PHY AHB clock + - description: SuperSpeed pipe clock + + clock-names: + items: + - const: ref + - const: ahb + - const: pipe + + vdd-supply: + description: phandle to the regulator VDD supply node. + + vdda1p8-supply: + description: phandle to the regulator 1.8V supply node. + + resets: + items: + - description: COM reset + - description: PHY reset line + + reset-names: + items: + - const: com + - const: phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda1p8-supply + +additionalProperties: false + +examples: + - | + #include + #include + usb3_phy: usb3-phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + }; +... -- 2.25.1