From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 524F7C433E2 for ; Thu, 28 May 2020 14:52:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2796A20888 for ; Thu, 28 May 2020 14:52:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590677565; bh=Ebx7jijUnpRPlvXA82f4pS2rM3VY7uO8uLut9YlHAhU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=n37WCXjLgdW3YTgDmklG+ivd9hUVw6Lyj2VmTnuL12okeXfs/pCniNO/pai4Pnr3G CJa4DtmSTMJbDexjGpr1I4eDBDrqgmhZ6aYsWFe4lZhIEEdMDBPxa40y8Ow4vGe0DH +X5wGZocAs9tk9GCIU6Lh4Vg3OzgJb4mffQWD1WA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403785AbgE1Owb (ORCPT ); Thu, 28 May 2020 10:52:31 -0400 Received: from mail-il1-f171.google.com ([209.85.166.171]:46189 "EHLO mail-il1-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391322AbgE1Owa (ORCPT ); Thu, 28 May 2020 10:52:30 -0400 Received: by mail-il1-f171.google.com with SMTP id h3so342667ilh.13; Thu, 28 May 2020 07:52:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=ovujcsIda1tQu8DKvfSwPVMWXijBMsT5Rkxd+Yb9Dnk=; b=IIvWxR8xlD7wyUoW56uJAmAm5mPr7u8Axd+OQfy15opTwxB2L6qnMYL4sKSGr8VRym CtSorwgKWKGWIcIB/nulXwyvHpc8Cwf2CgsOzXrv4IOFoWfjoaWOflmhZyFbvpjUFqtR S1X/ex8mOjGpoNHlnDXwzUW5e+nZKSEvYXPBFuIvtXfcRO4S+dtkYUJV5ruI7ESa/ALZ 9AsnRceAFcsRuLFaTY5pS0SNDPCtrIG1+LV1wn7U++NqsuoEHuUqMikWkm781dM8pfSP pGtbbvN+Avlcq8b+XIrhRAcVcSAbPusCv9Knwi37u/+kXurLCwEqHHbrrSCtnqRWm1GM 4tbQ== X-Gm-Message-State: AOAM533K/bW/tfgeX2UCe3JvRiRgdi0OmyoR3emniCnfGeh1TynKr+Iq cTS8pL/Sgz/SVttPkzs11Q== X-Google-Smtp-Source: ABdhPJwJaHWbYr6tMVxKGIV9kSLXoW5j2Prp5ZBTkEyhui05nVoF73ZZHNCf37YB32pRpWomLQkBEw== X-Received: by 2002:a92:b10c:: with SMTP id t12mr2979301ilh.158.1590677549086; Thu, 28 May 2020 07:52:29 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id v76sm3387048ill.73.2020.05.28.07.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2020 07:52:27 -0700 (PDT) Received: (nullmailer pid 44393 invoked by uid 1000); Thu, 28 May 2020 14:52:26 -0000 Date: Thu, 28 May 2020 08:52:26 -0600 From: Rob Herring To: Sai Prakash Ranjan Cc: linux-kernel@vger.kernel.org, Suzuki K Poulose , Leo Yan , Tingwei Zhang , Rob Herring , Mathieu Poirier , linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, Mike Leach , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Stephen Boyd Subject: Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up Message-ID: <20200528145226.GA44346@bogus> References: <7b69c9752713ce22f04688e83ec78f8aa67c63dc.1589558615.git.saiprakash.ranjan@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7b69c9752713ce22f04688e83ec78f8aa67c63dc.1589558615.git.saiprakash.ranjan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, 15 May 2020 21:52:33 +0530, Sai Prakash Ranjan wrote: > From: Tingwei Zhang > > Add "qcom,skip-power-up" property to identify systems which can > skip powering up of trace unit since they share the same power > domain as their CPU core. This is required to identify such > systems with hardware errata which stops the CPU watchdog counter > when the power up bit is set (TRCPDCR.PU). > > Signed-off-by: Tingwei Zhang > Co-developed-by: Sai Prakash Ranjan > Signed-off-by: Sai Prakash Ranjan > --- > Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ > 1 file changed, 7 insertions(+) > Reviewed-by: Rob Herring