From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 522B6C433E3 for ; Fri, 10 Jul 2020 17:33:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F9F72078D for ; Fri, 10 Jul 2020 17:33:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="TtG7vY+N" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727038AbgGJRdj (ORCPT ); Fri, 10 Jul 2020 13:33:39 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:25539 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727059AbgGJRdi (ORCPT ); Fri, 10 Jul 2020 13:33:38 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1594402417; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=nBIBjS8TfT8I4G2Q/UfKP196gmJswu2oE3cHLZLGdsE=; b=TtG7vY+NB/UkiS4gh0mFslFYPwIUh/X3beR1CB6uJwBs2uzLawyTkFOgMCedRCW1v6GqKxH5 xR+2psHruGnaeJFj9R80CxdNlvVksSgDQHFHU+f/TyUkmO8ansrRhKHvxaDCrE/fwWHapSJi uhnTMdY4jlQK12FGrhpPM2lD0r8= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n13.prod.us-west-2.postgun.com with SMTP id 5f08a6642991e765cdf01b16 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 10 Jul 2020 17:33:24 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C724BC43395; Fri, 10 Jul 2020 17:33:23 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse) by smtp.codeaurora.org (Postfix) with ESMTPSA id 01787C433C8; Fri, 10 Jul 2020 17:33:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 01787C433C8 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Fri, 10 Jul 2020 11:33:18 -0600 From: Jordan Crouse To: Jonathan Marek Cc: freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , kbuild test robot , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list Subject: Re: [PATCH] drm/msm/a6xx: add build_bw_table for A640/A650 Message-ID: <20200710173318.GE21059@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Jonathan Marek , freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , kbuild test robot , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20200701030958.24466-1-jonathan@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200701030958.24466-1-jonathan@marek.ca> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Jun 30, 2020 at 11:09:57PM -0400, Jonathan Marek wrote: > This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth > vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was > working, but this is required for A650 to work. > > Eventually the bw table should be filled by querying the interconnect > driver for each BW in the dts, but use these dummy tables for now. Reviewed-by: Jordan Crouse And yes, I agree that we need to move this into the generic API sooner rather than later, but this should be good enough to get a working GPU/GMU. > Signed-off-by: Jonathan Marek > --- > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 74 +++++++++++++++++++++++++++ > 1 file changed, 74 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index 9921e632f1ca..ccd44d0418f8 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -281,6 +281,76 @@ static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > msg->cnoc_cmds_data[1][0] = 0x60000001; > } > > +static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > +{ > + /* > + * Send a single "off" entry just to get things running > + * TODO: bus scaling > + */ > + msg->bw_level_num = 1; > + > + msg->ddr_cmds_num = 3; > + msg->ddr_wait_bitmask = 0x01; > + > + msg->ddr_cmds_addrs[0] = 0x50000; > + msg->ddr_cmds_addrs[1] = 0x5003c; > + msg->ddr_cmds_addrs[2] = 0x5000c; > + > + msg->ddr_cmds_data[0][0] = 0x40000000; > + msg->ddr_cmds_data[0][1] = 0x40000000; > + msg->ddr_cmds_data[0][2] = 0x40000000; > + > + /* > + * These are the CX (CNOC) votes - these are used by the GMU but the > + * votes are known and fixed for the target > + */ > + msg->cnoc_cmds_num = 3; > + msg->cnoc_wait_bitmask = 0x01; > + > + msg->cnoc_cmds_addrs[0] = 0x50034; > + msg->cnoc_cmds_addrs[1] = 0x5007c; > + msg->cnoc_cmds_addrs[2] = 0x5004c; > + > + msg->cnoc_cmds_data[0][0] = 0x40000000; > + msg->cnoc_cmds_data[0][1] = 0x00000000; > + msg->cnoc_cmds_data[0][2] = 0x40000000; > + > + msg->cnoc_cmds_data[1][0] = 0x60000001; > + msg->cnoc_cmds_data[1][1] = 0x20000001; > + msg->cnoc_cmds_data[1][2] = 0x60000001; > +} > + > +static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > +{ > + /* > + * Send a single "off" entry just to get things running > + * TODO: bus scaling > + */ > + msg->bw_level_num = 1; > + > + msg->ddr_cmds_num = 3; > + msg->ddr_wait_bitmask = 0x01; > + > + msg->ddr_cmds_addrs[0] = 0x50000; > + msg->ddr_cmds_addrs[1] = 0x50004; > + msg->ddr_cmds_addrs[2] = 0x5007c; > + > + msg->ddr_cmds_data[0][0] = 0x40000000; > + msg->ddr_cmds_data[0][1] = 0x40000000; > + msg->ddr_cmds_data[0][2] = 0x40000000; > + > + /* > + * These are the CX (CNOC) votes - these are used by the GMU but the > + * votes are known and fixed for the target > + */ > + msg->cnoc_cmds_num = 1; > + msg->cnoc_wait_bitmask = 0x01; > + > + msg->cnoc_cmds_addrs[0] = 0x500a4; > + msg->cnoc_cmds_data[0][0] = 0x40000000; > + msg->cnoc_cmds_data[1][0] = 0x60000001; > +} > + > static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > { > /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ > @@ -327,6 +397,10 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) > > if (adreno_is_a618(adreno_gpu)) > a618_build_bw_table(&msg); > + else if (adreno_is_a640(adreno_gpu)) > + a640_build_bw_table(&msg); > + else if (adreno_is_a650(adreno_gpu)) > + a650_build_bw_table(&msg); > else > a6xx_build_bw_table(&msg); > > -- > 2.26.1 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project