From: Matthias Kaehlcke <mka@chromium.org>
To: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Felipe Balbi <balbi@kernel.org>,
Stephen Boyd <swboyd@chromium.org>,
Doug Anderson <dianders@chromium.org>,
linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manu Gautam <mgautam@codeaurora.org>,
Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Subject: Re: [PATCH v10 1/2] usb: dwc3: qcom: Add interconnect support in dwc3 driver
Date: Thu, 23 Jul 2020 11:51:23 -0700 [thread overview]
Message-ID: <20200723185123.GY3191083@google.com> (raw)
In-Reply-To: <1595528857-25357-2-git-send-email-sanm@codeaurora.org>
Hi Sandeep,
On Thu, Jul 23, 2020 at 11:57:36PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB to
> DDR. The other is from APPS to USB.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 127 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 125 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index e1e78e9..712efb7 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -13,6 +13,7 @@
> #include <linux/module.h>
> #include <linux/kernel.h>
> #include <linux/extcon.h>
> +#include <linux/interconnect.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> @@ -43,6 +44,14 @@
> #define SDM845_QSCRATCH_SIZE 0x400
> #define SDM845_DWC3_CORE_SIZE 0xcd00
>
> +/* Interconnect path bandwidths in MBps */
> +#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
> +#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
> +#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
> +#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
> +#define APPS_USB_AVG_BW 0
> +#define APPS_USB_PEAK_BW MBps_to_icc(40)
> +
> struct dwc3_acpi_pdata {
> u32 qscratch_base_offset;
> u32 qscratch_base_size;
> @@ -76,6 +85,8 @@ struct dwc3_qcom {
> enum usb_dr_mode mode;
> bool is_suspended;
> bool pm_suspended;
> + struct icc_path *icc_path_ddr;
> + struct icc_path *icc_path_apps;
> };
>
> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
> @@ -190,6 +201,103 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
> return 0;
> }
>
> +static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
> +{
> + int ret;
> +
> + ret = icc_enable(qcom->icc_path_ddr);
> + if (ret)
> + return ret;
> +
> + ret = icc_enable(qcom->icc_path_apps);
> + if (ret)
> + return icc_disable(qcom->icc_path_ddr);
You are returning the result of icc_disable(), but it should be the
previous error. Just do
icc_disable(qcom->icc_path_ddr);
and use the below statement for returning (if not it should be 'return 0').
> +
> + return ret;
> +}
> +
> +static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
> +{
> + int ret;
> +
> + ret = icc_disable(qcom->icc_path_ddr);
> + if (ret)
> + return ret;
> +
> + ret = icc_disable(qcom->icc_path_apps);
> + if (ret)
> + goto err_reenable_memory_path;
Please make the error handling in _enable() and _disable() symmetrical, either
call icc_enable/disable() directly or use a goto in both functions (IMO the goto
is not needed in this case, it makes the code more complex rather than
simplifying it).
> +
> + return 0;
> +
> + /* Re-enable things in the event of an error */
> +err_reenable_memory_path:
> + dwc3_qcom_interconnect_enable(qcom);
Why this function which disables both paths and not just
icc_enable(qcom->icc_path_ddr), analogous to dwc3_qcom_interconnect_enable()?
> +
> + return ret;
> +}
> +
> +/**
> + * dwc3_qcom_interconnect_init() - Get interconnect path handles
> + * and set bandwidhth.
> + * @qcom: Pointer to the concerned usb core.
> + *
> + */
> +static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
> +{
> + struct device *dev = qcom->dev;
> + int ret;
> +
> + qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
> + if (IS_ERR(qcom->icc_path_ddr)) {
> + dev_err(dev, "failed to get usb-ddr path: %ld\n",
> + PTR_ERR(qcom->icc_path_ddr));
> + return PTR_ERR(qcom->icc_path_ddr);
> + }
> +
> + qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
> + if (IS_ERR(qcom->icc_path_apps)) {
> + dev_err(dev, "failed to get apps-usb path: %ld\n",
> + PTR_ERR(qcom->icc_path_apps));
> + return PTR_ERR(qcom->icc_path_apps);
> + }
> +
> + if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
> + usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
> + ret = icc_set_bw(qcom->icc_path_ddr,
> + USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
> + else
> + ret = icc_set_bw(qcom->icc_path_ddr,
> + USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
> +
> + if (ret) {
> + dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
> + return ret;
> + }
> +
> + ret = icc_set_bw(qcom->icc_path_apps,
> + APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
> +
nit: remove empty line, the call and the if block belong together.
> + if (ret) {
> + dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
> + return ret;
> + }
next prev parent reply other threads:[~2020-07-23 18:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-23 18:27 [PATCH v10 0/2] ADD interconnect support for Qualcomm DWC3 driver Sandeep Maheswaram
2020-07-23 18:27 ` [PATCH v10 1/2] usb: dwc3: qcom: Add interconnect support in dwc3 driver Sandeep Maheswaram
2020-07-23 18:51 ` Matthias Kaehlcke [this message]
2020-07-27 19:17 ` Matthias Kaehlcke
2020-07-27 19:18 ` Matthias Kaehlcke
2020-07-23 18:27 ` [PATCH v10 2/2] arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB node Sandeep Maheswaram
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