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From: Sibi Sankar <sibis@codeaurora.org>
To: robh+dt@kernel.org, georgi.djakov@linaro.org
Cc: bjorn.andersson@linaro.org, agross@kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, jonathan@marek.ca,
	linux-pm@vger.kernel.org, Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH 2/7] interconnect: qcom: Add OSM L3 support on SM8150
Date: Sat,  1 Aug 2020 18:00:44 +0530
Message-ID: <20200801123049.32398-3-sibis@codeaurora.org> (raw)
In-Reply-To: <20200801123049.32398-1-sibis@codeaurora.org>

Add Operation State Manager (OSM) L3 interconnect provider support on
SM8150 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 drivers/interconnect/qcom/osm-l3.c | 15 +++++++++++++++
 drivers/interconnect/qcom/sm8150.h |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 96fb9ff5ff2e8..00831c33e0fe5 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -16,6 +16,7 @@
 
 #include "sc7180.h"
 #include "sdm845.h"
+#include "sm8150.h"
 
 #define LUT_MAX_ENTRIES			40U
 #define LUT_SRC				GENMASK(31, 30)
@@ -96,6 +97,19 @@ static const struct qcom_icc_desc sc7180_icc_osm_l3 = {
 	.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
 };
 
+DEFINE_QNODE(sm8150_osm_apps_l3, SM8150_MASTER_OSM_L3_APPS, 32, SM8150_SLAVE_OSM_L3);
+DEFINE_QNODE(sm8150_osm_l3, SM8150_SLAVE_OSM_L3, 32);
+
+static struct qcom_icc_node *sm8150_osm_l3_nodes[] = {
+	[MASTER_OSM_L3_APPS] = &sm8150_osm_apps_l3,
+	[SLAVE_OSM_L3] = &sm8150_osm_l3,
+};
+
+static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
+	.nodes = sm8150_osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sm8150_osm_l3_nodes),
+};
+
 static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_osm_l3_icc_provider *qp;
@@ -258,6 +272,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
+	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h
index 3e01ac76ae1db..97996f64d799c 100644
--- a/drivers/interconnect/qcom/sm8150.h
+++ b/drivers/interconnect/qcom/sm8150.h
@@ -148,5 +148,7 @@
 #define SM8150_SLAVE_VSENSE_CTRL_CFG		137
 #define SM8150_SNOC_CNOC_MAS			138
 #define SM8150_SNOC_CNOC_SLV			139
+#define SM8150_MASTER_OSM_L3_APPS		140
+#define SM8150_SLAVE_OSM_L3			141
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


  parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-01 12:30 [PATCH 0/7] Add L3 provider support for SM8150/SM8250 Sibi Sankar
2020-08-01 12:30 ` [PATCH 1/7] dt-bindings: interconnect: Add OSM L3 DT binding on SM8150 Sibi Sankar
2020-08-01 12:30 ` Sibi Sankar [this message]
2020-08-01 12:30 ` [PATCH 3/7] interconnect: qcom: Lay the groundwork for adding EPSS support Sibi Sankar
2020-08-01 12:30 ` [PATCH 4/7] dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 Sibi Sankar
2020-08-01 12:30 ` [PATCH 5/7] interconnect: qcom: Add EPSS L3 support " Sibi Sankar
2020-08-01 12:30 ` [PATCH 6/7] arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider Sibi Sankar
2020-08-01 12:30 ` [PATCH 7/7] arm64: dts: qcom: sm8250: Add EPSS " Sibi Sankar

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