From: Sibi Sankar <sibis@codeaurora.org>
To: robh+dt@kernel.org, georgi.djakov@linaro.org
Cc: bjorn.andersson@linaro.org, agross@kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org, jonathan@marek.ca,
linux-pm@vger.kernel.org, Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH 5/7] interconnect: qcom: Add EPSS L3 support on SM8250
Date: Sat, 1 Aug 2020 18:00:47 +0530 [thread overview]
Message-ID: <20200801123049.32398-6-sibis@codeaurora.org> (raw)
In-Reply-To: <20200801123049.32398-1-sibis@codeaurora.org>
Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SM8250 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/interconnect/qcom/osm-l3.c | 23 +++++++++++++++++++++++
drivers/interconnect/qcom/sm8250.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 27c9ece52efda..cbf4ef04491df 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -17,6 +17,7 @@
#include "sc7180.h"
#include "sdm845.h"
#include "sm8150.h"
+#include "sm8250.h"
#define LUT_MAX_ENTRIES 40U
#define LUT_SRC GENMASK(31, 30)
@@ -29,6 +30,11 @@
#define OSM_REG_FREQ_LUT 0x110
#define OSM_REG_PERF_STATE 0x920
+/* EPSS Register offsets */
+#define EPSS_LUT_ROW_SIZE 4
+#define EPSS_REG_FREQ_LUT 0x100
+#define EPSS_REG_PERF_STATE 0x320
+
#define OSM_L3_MAX_LINKS 1
#define to_qcom_provider(_provider) \
@@ -123,6 +129,22 @@ static const struct qcom_icc_desc sm8150_icc_osm_l3 = {
.reg_perf_state = OSM_REG_PERF_STATE,
};
+DEFINE_QNODE(sm8250_epss_apps_l3, SM8250_MASTER_EPSS_L3_APPS, 32, SM8250_SLAVE_EPSS_L3);
+DEFINE_QNODE(sm8250_epss_l3, SM8250_SLAVE_EPSS_L3, 32);
+
+static struct qcom_icc_node *sm8250_epss_l3_nodes[] = {
+ [MASTER_EPSS_L3_APPS] = &sm8250_epss_apps_l3,
+ [SLAVE_EPSS_L3_SHARED] = &sm8250_epss_l3,
+};
+
+static const struct qcom_icc_desc sm8250_icc_epss_l3 = {
+ .nodes = sm8250_epss_l3_nodes,
+ .num_nodes = ARRAY_SIZE(sm8250_epss_l3_nodes),
+ .lut_row_size = EPSS_LUT_ROW_SIZE,
+ .reg_freq_lut = EPSS_REG_FREQ_LUT,
+ .reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
@@ -288,6 +310,7 @@ static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
+ { .compatible = "qcom,sm8250-epss-l3", .data = &sm8250_icc_epss_l3 },
{ }
};
MODULE_DEVICE_TABLE(of, osm_l3_of_match);
diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h
index 7eb6c709c30d1..b31fb431a20fc 100644
--- a/drivers/interconnect/qcom/sm8250.h
+++ b/drivers/interconnect/qcom/sm8250.h
@@ -158,5 +158,7 @@
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
#define SM8250_SNOC_CNOC_MAS 148
#define SM8250_SNOC_CNOC_SLV 149
+#define SM8250_MASTER_EPSS_L3_APPS 150
+#define SM8250_SLAVE_EPSS_L3 151
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-08-01 12:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-01 12:30 [PATCH 0/7] Add L3 provider support for SM8150/SM8250 Sibi Sankar
2020-08-01 12:30 ` [PATCH 1/7] dt-bindings: interconnect: Add OSM L3 DT binding on SM8150 Sibi Sankar
2020-08-17 21:16 ` Rob Herring
2020-08-01 12:30 ` [PATCH 2/7] interconnect: qcom: Add OSM L3 support " Sibi Sankar
2020-08-01 12:30 ` [PATCH 3/7] interconnect: qcom: Lay the groundwork for adding EPSS support Sibi Sankar
2020-08-01 12:30 ` [PATCH 4/7] dt-bindings: interconnect: Add EPSS L3 DT binding on SM8250 Sibi Sankar
2020-08-17 21:16 ` Rob Herring
2020-08-01 12:30 ` Sibi Sankar [this message]
2020-08-01 12:30 ` [PATCH 6/7] arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider Sibi Sankar
2020-09-09 8:05 ` Georgi Djakov
2020-08-01 12:30 ` [PATCH 7/7] arm64: dts: qcom: sm8250: Add EPSS " Sibi Sankar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200801123049.32398-6-sibis@codeaurora.org \
--to=sibis@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=georgi.djakov@linaro.org \
--cc=jonathan@marek.ca \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).