From: Rob Clark <robdclark@gmail.com>
To: dri-devel@lists.freedesktop.org,
iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Sibi Sankar <sibis@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
Stephen Boyd <swboyd@chromium.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Rob Clark <robdclark@chromium.org>,
Joerg Roedel <joro@8bytes.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thierry Reding <treding@nvidia.com>,
Krishna Reddy <vdumpa@nvidia.com>,
linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU
DRIVERS), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v16 13/20] iommu/arm-smmu: Add support for split pagetables
Date: Tue, 1 Sep 2020 09:46:30 -0700 [thread overview]
Message-ID: <20200901164707.2645413-14-robdclark@gmail.com> (raw)
In-Reply-To: <20200901164707.2645413-1-robdclark@gmail.com>
From: Jordan Crouse <jcrouse@codeaurora.org>
Enable TTBR1 for a context bank if IO_PGTABLE_QUIRK_ARM_TTBR1 is selected
by the io-pgtable configuration.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 19 +++++++++++++++----
drivers/iommu/arm/arm-smmu/arm-smmu.h | 25 +++++++++++++++++++------
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 37d8d49299b4..8e884e58f208 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -552,11 +552,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr;
cb->ttbr[1] = 0;
} else {
- cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
- cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID,
- cfg->asid);
+ cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
+ cfg->asid);
cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID,
cfg->asid);
+
+ if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1)
+ cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
+ else
+ cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr;
}
} else {
cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
@@ -822,7 +826,14 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
/* Update the domain's page sizes to reflect the page table format */
domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
- domain->geometry.aperture_end = (1UL << ias) - 1;
+
+ if (pgtbl_cfg.quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+ domain->geometry.aperture_start = ~0UL << ias;
+ domain->geometry.aperture_end = ~0UL;
+ } else {
+ domain->geometry.aperture_end = (1UL << ias) - 1;
+ }
+
domain->geometry.force_aperture = true;
/* Initialise the context bank with our page table cfg */
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 83294516ac08..f3e456893f28 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -169,10 +169,12 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_TCR 0x30
#define ARM_SMMU_TCR_EAE BIT(31)
#define ARM_SMMU_TCR_EPD1 BIT(23)
+#define ARM_SMMU_TCR_A1 BIT(22)
#define ARM_SMMU_TCR_TG0 GENMASK(15, 14)
#define ARM_SMMU_TCR_SH0 GENMASK(13, 12)
#define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10)
#define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8)
+#define ARM_SMMU_TCR_EPD0 BIT(7)
#define ARM_SMMU_TCR_T0SZ GENMASK(5, 0)
#define ARM_SMMU_VTCR_RES1 BIT(31)
@@ -350,12 +352,23 @@ struct arm_smmu_domain {
static inline u32 arm_smmu_lpae_tcr(struct io_pgtable_cfg *cfg)
{
- return ARM_SMMU_TCR_EPD1 |
- FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
- FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
- FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
- FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
- FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+ u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
+ FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
+ FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
+ FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
+ FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
+
+ /*
+ * When TTBR1 is selected shift the TCR fields by 16 bits and disable
+ * translation in TTBR0
+ */
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
+ tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
+ tcr |= ARM_SMMU_TCR_EPD0;
+ } else
+ tcr |= ARM_SMMU_TCR_EPD1;
+
+ return tcr;
}
static inline u32 arm_smmu_lpae_tcr2(struct io_pgtable_cfg *cfg)
--
2.26.2
next prev parent reply other threads:[~2020-09-01 16:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 16:46 [PATCH v16 00/20] iommu/arm-smmu + drm/msm: per-process GPU pgtables Rob Clark
2020-09-01 16:46 ` [PATCH v16 01/20] drm/msm: Remove dangling submitqueue references Rob Clark
2020-09-01 16:46 ` [PATCH v16 02/20] drm/msm: Add private interface for adreno-smmu Rob Clark
2020-09-01 16:46 ` [PATCH v16 03/20] drm/msm/gpu: Add dev_to_gpu() helper Rob Clark
2020-09-01 16:46 ` [PATCH v16 04/20] drm/msm: Set adreno_smmu as gpu's drvdata Rob Clark
2020-09-01 16:46 ` [PATCH v16 05/20] drm/msm: Add a context pointer to the submitqueue Rob Clark
2020-09-01 16:46 ` [PATCH v16 06/20] drm/msm: Drop context arg to gpu->submit() Rob Clark
2020-09-01 16:46 ` [PATCH v16 07/20] drm/msm: Set the global virtual address range from the IOMMU domain Rob Clark
2020-09-01 16:46 ` [PATCH v16 08/20] drm/msm: Add support to create a local pagetable Rob Clark
2020-09-01 16:46 ` [PATCH v16 09/20] drm/msm: Add support for private address space instances Rob Clark
2020-09-01 16:46 ` [PATCH v16 10/20] drm/msm/a6xx: Add support for per-instance pagetables Rob Clark
2020-09-01 16:46 ` [PATCH v16 11/20] drm/msm: Show process names in gem_describe Rob Clark
2020-09-01 16:46 ` [PATCH v16 12/20] iommu/arm-smmu: Pass io-pgtable config to implementation specific function Rob Clark
2020-09-01 16:46 ` Rob Clark [this message]
2020-09-01 16:46 ` [PATCH v16 14/20] iommu/arm-smmu: Prepare for the adreno-smmu implementation Rob Clark
2020-09-04 16:00 ` Bjorn Andersson
2020-09-05 18:32 ` Rob Clark
2020-09-01 16:46 ` [PATCH v16 15/20] iommu/arm-smmu: Constify some helpers Rob Clark
2020-09-01 16:46 ` [PATCH v16 16/20] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Rob Clark
2020-09-01 16:46 ` [PATCH v16 17/20] iommu/arm-smmu: Add a way for implementations to influence SCTLR Rob Clark
2020-09-01 16:46 ` [PATCH v16 18/20] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU Rob Clark
2020-09-01 16:46 ` [PATCH v16 19/20] arm: dts: qcom: sm845: Set the compatible string for the " Rob Clark
2020-09-04 16:06 ` Bjorn Andersson
2020-09-01 16:46 ` [PATCH v16 20/20] arm: dts: qcom: sc7180: " Rob Clark
2020-09-04 16:06 ` Bjorn Andersson
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