From: Jonathan Marek <jonathan@marek.ca>
To: linux-arm-msm@vger.kernel.org
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Taniya Das <tdas@codeaurora.org>,
linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK),
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 5/7] dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
Date: Thu, 3 Sep 2020 18:26:13 -0400 [thread overview]
Message-ID: <20200903222620.27448-6-jonathan@marek.ca> (raw)
In-Reply-To: <20200903222620.27448-1-jonathan@marek.ca>
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8250 SoCs.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../bindings/clock/qcom,dispcc.yaml | 4 +-
.../dt-bindings/clock/qcom,dispcc-sm8250.h | 66 +++++++++++++++++++
2 files changed, 69 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index 5b5c7fa6375e..0b905a4e9ada 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -11,12 +11,13 @@ maintainers:
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SDM845/SC7180/SM8150.
+ power domains on SDM845/SC7180/SM8150/SM8250.
See also:
dt-bindings/clock/qcom,dispcc-sdm845.h
dt-bindings/clock/qcom,dispcc-sc7180.h
dt-bindings/clock/qcom,dispcc-sm8150.h
+ dt-bindings/clock/qcom,dispcc-sm8250.h
properties:
compatible:
@@ -24,6 +25,7 @@ properties:
- qcom,sdm845-dispcc
- qcom,sc7180-dispcc
- qcom,sm8150-dispcc
+ - qcom,sm8250-dispcc
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
# The code had to use hardcoded mechanisms to find the input clocks.
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
new file mode 100644
index 000000000000..fdaca6ad5c85
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK 12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DP_LINK1_CLK 14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
+#define DISP_CC_MDSS_DP_LINK_CLK 18
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
+#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
+#define DISP_CC_MDSS_DP_PIXEL_CLK 26
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
+#define DISP_CC_MDSS_ESC0_CLK 28
+#define DISP_CC_MDSS_ESC0_CLK_SRC 29
+#define DISP_CC_MDSS_ESC1_CLK 30
+#define DISP_CC_MDSS_ESC1_CLK_SRC 31
+#define DISP_CC_MDSS_MDP_CLK 32
+#define DISP_CC_MDSS_MDP_CLK_SRC 33
+#define DISP_CC_MDSS_MDP_LUT_CLK 34
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35
+#define DISP_CC_MDSS_PCLK0_CLK 36
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 37
+#define DISP_CC_MDSS_PCLK1_CLK 38
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 39
+#define DISP_CC_MDSS_ROT_CLK 40
+#define DISP_CC_MDSS_ROT_CLK_SRC 41
+#define DISP_CC_MDSS_RSCC_AHB_CLK 42
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43
+#define DISP_CC_MDSS_VSYNC_CLK 44
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
+#define DISP_CC_PLL0 46
+#define DISP_CC_PLL1 47
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
--
2.26.1
next prev parent reply other threads:[~2020-09-03 22:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 22:26 [PATCH v2 0/7] SM8150 and SM8250 dispcc drivers Jonathan Marek
2020-09-03 22:26 ` [PATCH v2 1/7] dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as sc7180 Jonathan Marek
2020-09-03 22:26 ` [PATCH v2 2/7] arm64: dts: qcom: " Jonathan Marek
2020-09-03 22:26 ` [PATCH v2 3/7] dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc Jonathan Marek
2020-09-03 22:26 ` [PATCH v2 4/7] dt-bindings: clock: Introduce QCOM SM8150 display clock bindings Jonathan Marek
2020-09-03 22:26 ` Jonathan Marek [this message]
2020-09-03 22:26 ` [PATCH v2 6/7] clk: qcom: Add display clock controller driver for SM8150 Jonathan Marek
2020-09-03 22:26 ` [PATCH v2 7/7] clk: qcom: Add display clock controller driver for SM8250 Jonathan Marek
2020-09-07 14:25 ` [PATCH v2 0/7] SM8150 and SM8250 dispcc drivers Dmitry Baryshkov
[not found] ` <160012787871.4188128.16710718496771467444@swboyd.mtv.corp.google.com>
2020-09-14 23:58 ` Jonathan Marek
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