linux-arm-msm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
@ 2021-02-10 10:47 Vinod Koul
  2021-02-10 10:47 ` [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver Vinod Koul
  2021-02-10 11:30 ` [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Georgi Djakov
  0 siblings, 2 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-10 10:47 UTC (permalink / raw)
  To: Georgi Djakov
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	Rob Herring, Odelu Kukatla, linux-pm, devicetree, linux-kernel

The Qualcomm SM8350 platform has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 .../bindings/interconnect/qcom,rpmh.yaml      |  10 ++
 .../dt-bindings/interconnect/qcom,sm8350.h    | 169 ++++++++++++++++++
 2 files changed, 179 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/qcom,sm8350.h

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index 30c2a092d2d3..e47f2aa0c61b 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -67,6 +67,16 @@ properties:
       - qcom,sm8250-mmss-noc
       - qcom,sm8250-npu-noc
       - qcom,sm8250-system-noc
+      - qcom,sm8350-aggre1-noc
+      - qcom,sm8350-aggre2-noc
+      - qcom,sm8350-config-noc
+      - qcom,sm8350-dc-noc
+      - qcom,sm8350-gem-noc
+      - qcom,sm8350-lpass-ag-noc
+      - qcom,sm8350-mc-virt
+      - qcom,sm8350-mmss-noc
+      - qcom,sm8350-compute-noc
+      - qcom,sm8350-system-noc
 
   '#interconnect-cells':
     const: 1
diff --git a/include/dt-bindings/interconnect/qcom,sm8350.h b/include/dt-bindings/interconnect/qcom,sm8350.h
new file mode 100644
index 000000000000..8633c58b3b80
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sm8350.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Qualcomm SM8350 interconnect IDs
+ *
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
+
+#define SM8350_MASTER_GPU_TCU				0
+#define SM8350_MASTER_SYS_TCU				1
+#define SM8350_MASTER_APPSS_PROC			2
+#define SM8350_MASTER_LLCC				3
+#define SM8350_MASTER_CNOC_LPASS_AG_NOC			4
+#define SM8350_MASTER_CDSP_NOC_CFG			5
+#define SM8350_MASTER_QDSS_BAM				6
+#define SM8350_MASTER_QSPI_0				7
+#define SM8350_MASTER_QUP_0				8
+#define SM8350_MASTER_QUP_1				9
+#define SM8350_MASTER_QUP_2				10
+#define SM8350_MASTER_A1NOC_CFG				11
+#define SM8350_MASTER_A2NOC_CFG				12
+#define SM8350_MASTER_A1NOC_SNOC			13
+#define SM8350_MASTER_A2NOC_SNOC			14
+#define SM8350_MASTER_CAMNOC_HF				15
+#define SM8350_MASTER_CAMNOC_ICP			16
+#define SM8350_MASTER_CAMNOC_SF				17
+#define SM8350_MASTER_COMPUTE_NOC			18
+#define SM8350_MASTER_CNOC_DC_NOC			19
+#define SM8350_MASTER_GEM_NOC_CFG			20
+#define SM8350_MASTER_GEM_NOC_CNOC			21
+#define SM8350_MASTER_GEM_NOC_PCIE_SNOC			22
+#define SM8350_MASTER_GFX3D				23
+#define SM8350_MASTER_CNOC_MNOC_CFG			24
+#define SM8350_MASTER_MNOC_HF_MEM_NOC			25
+#define SM8350_MASTER_MNOC_SF_MEM_NOC			26
+#define SM8350_MASTER_ANOC_PCIE_GEM_NOC			27
+#define SM8350_MASTER_SNOC_CFG				28
+#define SM8350_MASTER_SNOC_GC_MEM_NOC			29
+#define SM8350_MASTER_SNOC_SF_MEM_NOC			30
+#define SM8350_MASTER_VIDEO_P0				31
+#define SM8350_MASTER_VIDEO_P1				32
+#define SM8350_MASTER_VIDEO_PROC			33
+#define SM8350_MASTER_QUP_CORE_0			34
+#define SM8350_MASTER_QUP_CORE_1			35
+#define SM8350_MASTER_QUP_CORE_2			36
+#define SM8350_MASTER_CRYPTO				37
+#define SM8350_MASTER_IPA				38
+#define SM8350_MASTER_MDP0				39
+#define SM8350_MASTER_MDP1				40
+#define SM8350_MASTER_CDSP_PROC				41
+#define SM8350_MASTER_PIMEM				42
+#define SM8350_MASTER_ROTATOR				43
+#define SM8350_MASTER_GIC				44
+#define SM8350_MASTER_PCIE_0				45
+#define SM8350_MASTER_PCIE_1				46
+#define SM8350_MASTER_QDSS_DAP				47
+#define SM8350_MASTER_QDSS_ETR				48
+#define SM8350_MASTER_SDCC_2				49
+#define SM8350_MASTER_SDCC_4				50
+#define SM8350_MASTER_UFS_CARD				51
+#define SM8350_MASTER_UFS_MEM				52
+#define SM8350_MASTER_USB3_0				53
+#define SM8350_MASTER_USB3_1				54
+#define SM8350_SLAVE_EBI1				512
+#define SM8350_SLAVE_AHB2PHY_SOUTH			513
+#define SM8350_SLAVE_AHB2PHY_NORTH			514
+#define SM8350_SLAVE_AOSS				515
+#define SM8350_SLAVE_APPSS				516
+#define SM8350_SLAVE_CAMERA_CFG				517
+#define SM8350_SLAVE_CLK_CTL				518
+#define SM8350_SLAVE_CDSP_CFG				519
+#define SM8350_SLAVE_RBCPR_CX_CFG			520
+#define SM8350_SLAVE_RBCPR_MMCX_CFG			521
+#define SM8350_SLAVE_RBCPR_MX_CFG			522
+#define SM8350_SLAVE_CRYPTO_0_CFG			523
+#define SM8350_SLAVE_CX_RDPM				524
+#define SM8350_SLAVE_DCC_CFG				525
+#define SM8350_SLAVE_DISPLAY_CFG			526
+#define SM8350_SLAVE_GFX3D_CFG				527
+#define SM8350_SLAVE_HWKM				528
+#define SM8350_SLAVE_IMEM_CFG				529
+#define SM8350_SLAVE_IPA_CFG				530
+#define SM8350_SLAVE_IPC_ROUTER_CFG			531
+#define SM8350_SLAVE_LLCC_CFG				532
+#define SM8350_SLAVE_LPASS				533
+#define SM8350_SLAVE_LPASS_CORE_CFG			534
+#define SM8350_SLAVE_LPASS_LPI_CFG			535
+#define SM8350_SLAVE_LPASS_MPU_CFG			536
+#define SM8350_SLAVE_LPASS_TOP_CFG			537
+#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG		538
+#define SM8350_SLAVE_MCDMA_MS_MPU_CFG			539
+#define SM8350_SLAVE_CNOC_MSS				540
+#define SM8350_SLAVE_MX_RDPM				541
+#define SM8350_SLAVE_PCIE_0_CFG				542
+#define SM8350_SLAVE_PCIE_1_CFG				543
+#define SM8350_SLAVE_PDM				544
+#define SM8350_SLAVE_PIMEM_CFG				545
+#define SM8350_SLAVE_PKA_WRAPPER_CFG			546
+#define SM8350_SLAVE_PMU_WRAPPER_CFG			547
+#define SM8350_SLAVE_QDSS_CFG				548
+#define SM8350_SLAVE_QSPI_0				549
+#define SM8350_SLAVE_QUP_0				550
+#define SM8350_SLAVE_QUP_1				551
+#define SM8350_SLAVE_QUP_2				552
+#define SM8350_SLAVE_SDCC_2				553
+#define SM8350_SLAVE_SDCC_4				554
+#define SM8350_SLAVE_SECURITY				555
+#define SM8350_SLAVE_SPSS_CFG				556
+#define SM8350_SLAVE_TCSR				557
+#define SM8350_SLAVE_TLMM				558
+#define SM8350_SLAVE_UFS_CARD_CFG			559
+#define SM8350_SLAVE_UFS_MEM_CFG			560
+#define SM8350_SLAVE_USB3_0				561
+#define SM8350_SLAVE_USB3_1				562
+#define SM8350_SLAVE_VENUS_CFG				563
+#define SM8350_SLAVE_VSENSE_CTRL_CFG			564
+#define SM8350_SLAVE_A1NOC_CFG				565
+#define SM8350_SLAVE_A1NOC_SNOC				566
+#define SM8350_SLAVE_A2NOC_CFG				567
+#define SM8350_SLAVE_A2NOC_SNOC				568
+#define SM8350_SLAVE_DDRSS_CFG				569
+#define SM8350_SLAVE_GEM_NOC_CNOC			570
+#define SM8350_SLAVE_GEM_NOC_CFG			571
+#define SM8350_SLAVE_SNOC_GEM_NOC_GC			572
+#define SM8350_SLAVE_SNOC_GEM_NOC_SF			573
+#define SM8350_SLAVE_LLCC				574
+#define SM8350_SLAVE_MNOC_HF_MEM_NOC			575
+#define SM8350_SLAVE_MNOC_SF_MEM_NOC			576
+#define SM8350_SLAVE_CNOC_MNOC_CFG			577
+#define SM8350_SLAVE_CDSP_MEM_NOC			578
+#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC			579
+#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC			580
+#define SM8350_SLAVE_SNOC_CFG				581
+#define SM8350_SLAVE_QUP_CORE_0				582
+#define SM8350_SLAVE_QUP_CORE_1				583
+#define SM8350_SLAVE_QUP_CORE_2				584
+#define SM8350_SLAVE_BOOT_IMEM				585
+#define SM8350_SLAVE_IMEM				586
+#define SM8350_SLAVE_PIMEM				587
+#define SM8350_SLAVE_SERVICE_NSP_NOC			588
+#define SM8350_SLAVE_SERVICE_A1NOC			589
+#define SM8350_SLAVE_SERVICE_A2NOC			590
+#define SM8350_SLAVE_SERVICE_CNOC			591
+#define SM8350_SLAVE_SERVICE_GEM_NOC_1			592
+#define SM8350_SLAVE_SERVICE_MNOC			593
+#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC		594
+#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC		595
+#define SM8350_SLAVE_SERVICE_GEM_NOC_2			596
+#define SM8350_SLAVE_SERVICE_SNOC			597
+#define SM8350_SLAVE_SERVICE_GEM_NOC			598
+#define SM8350_SLAVE_PCIE_0				599
+#define SM8350_SLAVE_PCIE_1				600
+#define SM8350_SLAVE_QDSS_STM				601
+#define SM8350_SLAVE_TCU				602
+#define SM8350_MASTER_LLCC_DISP				1000
+#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP		1001
+#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP		1002
+#define SM8350_MASTER_MDP0_DISP				1003
+#define SM8350_MASTER_MDP1_DISP				1004
+#define SM8350_MASTER_ROTATOR_DISP			1005
+#define SM8350_SLAVE_EBI1_DISP				1512
+#define SM8350_SLAVE_LLCC_DISP				1513
+#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP		1514
+#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP		1515
+
+#endif
-- 
2.26.2


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver
  2021-02-10 10:47 [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Vinod Koul
@ 2021-02-10 10:47 ` Vinod Koul
  2021-02-10 11:40   ` Georgi Djakov
  2021-02-10 11:30 ` [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Georgi Djakov
  1 sibling, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2021-02-10 10:47 UTC (permalink / raw)
  To: Georgi Djakov
  Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
	Rob Herring, Odelu Kukatla, linux-pm, devicetree, linux-kernel

Add driver for the Qualcomm interconnect buses found in SM8i350 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.

Generated from downstream interconnect driver written by David Dai

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/interconnect/qcom/Kconfig  |  10 +
 drivers/interconnect/qcom/Makefile |   2 +
 drivers/interconnect/qcom/sm8350.c | 635 +++++++++++++++++++++++++++++
 3 files changed, 647 insertions(+)
 create mode 100644 drivers/interconnect/qcom/sm8350.c

diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index a8f93ba265f8..2ad0aea8336a 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -85,5 +85,15 @@ config INTERCONNECT_QCOM_SM8250
 	  This is a driver for the Qualcomm Network-on-Chip on sm8250-based
 	  platforms.
 
+config INTERCONNECT_QCOM_SM8350
+	tristate "Qualcomm SM8350 interconnect driver"
+	depends on INTERCONNECT_QCOM
+	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
+	select INTERCONNECT_QCOM_RPMH
+	select INTERCONNECT_QCOM_BCM_VOTER
+	help
+	  This is a driver for the Qualcomm Network-on-Chip on SM8350-based
+	  platforms.
+
 config INTERCONNECT_QCOM_SMD_RPM
 	tristate
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index cf628f7990cd..4062c9e43a2a 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -10,6 +10,7 @@ qnoc-sc7180-objs			:= sc7180.o
 qnoc-sdm845-objs			:= sdm845.o
 qnoc-sm8150-objs			:= sm8150.o
 qnoc-sm8250-objs			:= sm8250.o
+qnoc-sm8350-objs			:= sm8350.o
 icc-smd-rpm-objs			:= smd-rpm.o
 
 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
@@ -22,4 +23,5 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
 obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
 obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
 obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
 obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c
new file mode 100644
index 000000000000..194a29e789e1
--- /dev/null
+++ b/drivers/interconnect/qcom/sm8350.c
@@ -0,0 +1,635 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, Linaro Limited
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC);
+DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
+DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC);
+DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
+DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
+DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1);
+DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
+DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG);
+DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC);
+DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC);
+DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
+DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC);
+DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1);
+DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC);
+DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC);
+DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC);
+DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
+DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
+DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC);
+DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
+DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
+DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
+DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
+DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP);
+DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
+DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
+DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP);
+DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC);
+DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4);
+DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC);
+DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC);
+DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4);
+DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4);
+DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4);
+DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4);
+DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8);
+DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4);
+DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4);
+DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4);
+DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4);
+DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4);
+DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4);
+DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4);
+DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8);
+DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4);
+DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4);
+DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4);
+DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC);
+DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4);
+DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4);
+DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4);
+DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4);
+DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4);
+DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4);
+DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4);
+DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4);
+DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4);
+DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4);
+DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4);
+DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4);
+DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4);
+DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4);
+DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4);
+DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4);
+DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4);
+DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4);
+DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4);
+DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4);
+DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4);
+DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4);
+DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4);
+DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
+DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4);
+DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4);
+DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4);
+DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4);
+DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4);
+DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8);
+DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8);
+DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8);
+DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4);
+DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8);
+DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8);
+DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4);
+DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8);
+DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4);
+DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4);
+DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
+DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
+DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16);
+DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16);
+DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8);
+DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
+DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
+DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4);
+DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4);
+DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4);
+DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4);
+DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4);
+DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4);
+DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4);
+DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4);
+DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC);
+DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC);
+DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4);
+DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC);
+DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4);
+DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC);
+DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC);
+DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4);
+DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP);
+DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4);
+DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP);
+DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP);
+
+DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
+DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
+DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
+DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
+DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
+DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
+DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
+DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
+DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
+DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
+DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
+DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
+DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
+DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
+DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
+DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
+DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
+DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
+DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
+DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
+DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
+DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
+DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
+DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
+DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
+DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
+DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
+DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
+DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
+DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
+DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
+DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
+
+static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *aggre1_noc_nodes[] = {
+	[SM8350_MASTER_QSPI_0] = &qhm_qspi,
+	[SM8350_MASTER_QUP_1] = &qhm_qup1,
+	[SM8350_MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
+	[SM8350_MASTER_SDCC_4] = &xm_sdc4,
+	[SM8350_MASTER_UFS_MEM] = &xm_ufs_mem,
+	[SM8350_MASTER_USB3_0] = &xm_usb3_0,
+	[SM8350_MASTER_USB3_1] = &xm_usb3_1,
+	[SM8350_SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+	[SM8350_SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
+};
+
+static struct qcom_icc_desc sm8350_aggre1_noc = {
+	.nodes = aggre1_noc_nodes,
+	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+	.bcms = aggre1_noc_bcms,
+	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+};
+
+static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
+	&bcm_ce0,
+	&bcm_sn5,
+	&bcm_sn6,
+	&bcm_sn14,
+};
+
+static struct qcom_icc_node *aggre2_noc_nodes[] = {
+	[SM8350_MASTER_QDSS_BAM] = &qhm_qdss_bam,
+	[SM8350_MASTER_QUP_0] = &qhm_qup0,
+	[SM8350_MASTER_QUP_2] = &qhm_qup2,
+	[SM8350_MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
+	[SM8350_MASTER_CRYPTO] = &qxm_crypto,
+	[SM8350_MASTER_IPA] = &qxm_ipa,
+	[SM8350_MASTER_PCIE_0] = &xm_pcie3_0,
+	[SM8350_MASTER_PCIE_1] = &xm_pcie3_1,
+	[SM8350_MASTER_QDSS_ETR] = &xm_qdss_etr,
+	[SM8350_MASTER_SDCC_2] = &xm_sdc2,
+	[SM8350_MASTER_UFS_CARD] = &xm_ufs_card,
+	[SM8350_SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
+	[SM8350_SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
+	[SM8350_SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
+};
+
+static struct qcom_icc_desc sm8350_aggre2_noc = {
+	.nodes = aggre2_noc_nodes,
+	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
+	.bcms = aggre2_noc_bcms,
+	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
+};
+
+static struct qcom_icc_bcm *config_noc_bcms[] = {
+	&bcm_cn0,
+	&bcm_cn1,
+	&bcm_cn2,
+	&bcm_sn3,
+	&bcm_sn4,
+};
+
+static struct qcom_icc_node *config_noc_nodes[] = {
+	[SM8350_MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+	[SM8350_MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+	[SM8350_MASTER_QDSS_DAP] = &xm_qdss_dap,
+	[SM8350_SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+	[SM8350_SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
+	[SM8350_SLAVE_AOSS] = &qhs_aoss,
+	[SM8350_SLAVE_APPSS] = &qhs_apss,
+	[SM8350_SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+	[SM8350_SLAVE_CLK_CTL] = &qhs_clk_ctl,
+	[SM8350_SLAVE_CDSP_CFG] = &qhs_compute_cfg,
+	[SM8350_SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
+	[SM8350_SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
+	[SM8350_SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
+	[SM8350_SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
+	[SM8350_SLAVE_CX_RDPM] = &qhs_cx_rdpm,
+	[SM8350_SLAVE_DCC_CFG] = &qhs_dcc_cfg,
+	[SM8350_SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+	[SM8350_SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+	[SM8350_SLAVE_HWKM] = &qhs_hwkm,
+	[SM8350_SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+	[SM8350_SLAVE_IPA_CFG] = &qhs_ipa,
+	[SM8350_SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+	[SM8350_SLAVE_LPASS] = &qhs_lpass_cfg,
+	[SM8350_SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+	[SM8350_SLAVE_MX_RDPM] = &qhs_mx_rdpm,
+	[SM8350_SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
+	[SM8350_SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
+	[SM8350_SLAVE_PDM] = &qhs_pdm,
+	[SM8350_SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
+	[SM8350_SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
+	[SM8350_SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
+	[SM8350_SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
+	[SM8350_SLAVE_QSPI_0] = &qhs_qspi,
+	[SM8350_SLAVE_QUP_0] = &qhs_qup0,
+	[SM8350_SLAVE_QUP_1] = &qhs_qup1,
+	[SM8350_SLAVE_QUP_2] = &qhs_qup2,
+	[SM8350_SLAVE_SDCC_2] = &qhs_sdc2,
+	[SM8350_SLAVE_SDCC_4] = &qhs_sdc4,
+	[SM8350_SLAVE_SECURITY] = &qhs_security,
+	[SM8350_SLAVE_SPSS_CFG] = &qhs_spss_cfg,
+	[SM8350_SLAVE_TCSR] = &qhs_tcsr,
+	[SM8350_SLAVE_TLMM] = &qhs_tlmm,
+	[SM8350_SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
+	[SM8350_SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+	[SM8350_SLAVE_USB3_0] = &qhs_usb3_0,
+	[SM8350_SLAVE_USB3_1] = &qhs_usb3_1,
+	[SM8350_SLAVE_VENUS_CFG] = &qhs_venus_cfg,
+	[SM8350_SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+	[SM8350_SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
+	[SM8350_SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
+	[SM8350_SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
+	[SM8350_SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
+	[SM8350_SLAVE_SNOC_CFG] = &qns_snoc_cfg,
+	[SM8350_SLAVE_BOOT_IMEM] = &qxs_boot_imem,
+	[SM8350_SLAVE_IMEM] = &qxs_imem,
+	[SM8350_SLAVE_PIMEM] = &qxs_pimem,
+	[SM8350_SLAVE_SERVICE_CNOC] = &srvc_cnoc,
+	[SM8350_SLAVE_PCIE_0] = &xs_pcie_0,
+	[SM8350_SLAVE_PCIE_1] = &xs_pcie_1,
+	[SM8350_SLAVE_QDSS_STM] = &xs_qdss_stm,
+	[SM8350_SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static struct qcom_icc_desc sm8350_config_noc = {
+	.nodes = config_noc_nodes,
+	.num_nodes = ARRAY_SIZE(config_noc_nodes),
+	.bcms = config_noc_bcms,
+	.num_bcms = ARRAY_SIZE(config_noc_bcms),
+};
+
+static struct qcom_icc_bcm *dc_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *dc_noc_nodes[] = {
+	[SM8350_MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
+	[SM8350_SLAVE_LLCC_CFG] = &qhs_llcc,
+	[SM8350_SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
+};
+
+static struct qcom_icc_desc sm8350_dc_noc = {
+	.nodes = dc_noc_nodes,
+	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
+	.bcms = dc_noc_bcms,
+	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
+};
+
+static struct qcom_icc_bcm *gem_noc_bcms[] = {
+	&bcm_sh0,
+	&bcm_sh2,
+	&bcm_sh3,
+	&bcm_sh4,
+	&bcm_sh0_disp,
+};
+
+static struct qcom_icc_node *gem_noc_nodes[] = {
+	[SM8350_MASTER_GPU_TCU] = &alm_gpu_tcu,
+	[SM8350_MASTER_SYS_TCU] = &alm_sys_tcu,
+	[SM8350_MASTER_APPSS_PROC] = &chm_apps,
+	[SM8350_MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
+	[SM8350_MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
+	[SM8350_MASTER_GFX3D] = &qnm_gpu,
+	[SM8350_MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+	[SM8350_MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+	[SM8350_MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+	[SM8350_MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
+	[SM8350_MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+	[SM8350_SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
+	[SM8350_SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
+	[SM8350_SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+	[SM8350_SLAVE_LLCC] = &qns_llcc,
+	[SM8350_SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+	[SM8350_SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
+	[SM8350_SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
+	[SM8350_SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
+	[SM8350_MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
+	[SM8350_MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
+	[SM8350_SLAVE_LLCC_DISP] = &qns_llcc_disp,
+};
+
+static struct qcom_icc_desc sm8350_gem_noc = {
+	.nodes = gem_noc_nodes,
+	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
+	.bcms = gem_noc_bcms,
+	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
+};
+
+static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
+	[SM8350_MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
+	[SM8350_SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
+	[SM8350_SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
+	[SM8350_SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
+	[SM8350_SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
+	[SM8350_SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
+	[SM8350_SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
+};
+
+static struct qcom_icc_desc sm8350_lpass_ag_noc = {
+	.nodes = lpass_ag_noc_nodes,
+	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+	.bcms = lpass_ag_noc_bcms,
+	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
+};
+
+static struct qcom_icc_bcm *mc_virt_bcms[] = {
+	&bcm_acv,
+	&bcm_mc0,
+	&bcm_acv_disp,
+	&bcm_mc0_disp,
+};
+
+static struct qcom_icc_node *mc_virt_nodes[] = {
+	[SM8350_MASTER_LLCC] = &llcc_mc,
+	[SM8350_SLAVE_EBI1] = &ebi,
+	[SM8350_MASTER_LLCC_DISP] = &llcc_mc_disp,
+	[SM8350_SLAVE_EBI1_DISP] = &ebi_disp,
+};
+
+static struct qcom_icc_desc sm8350_mc_virt = {
+	.nodes = mc_virt_nodes,
+	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
+	.bcms = mc_virt_bcms,
+	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm *mmss_noc_bcms[] = {
+	&bcm_mm0,
+	&bcm_mm1,
+	&bcm_mm4,
+	&bcm_mm5,
+	&bcm_mm0_disp,
+	&bcm_mm1_disp,
+	&bcm_mm4_disp,
+	&bcm_mm5_disp,
+};
+
+static struct qcom_icc_node *mmss_noc_nodes[] = {
+	[SM8350_MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+	[SM8350_MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
+	[SM8350_MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+	[SM8350_MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
+	[SM8350_MASTER_VIDEO_P0] = &qnm_video0,
+	[SM8350_MASTER_VIDEO_P1] = &qnm_video1,
+	[SM8350_MASTER_VIDEO_PROC] = &qnm_video_cvp,
+	[SM8350_MASTER_MDP0] = &qxm_mdp0,
+	[SM8350_MASTER_MDP1] = &qxm_mdp1,
+	[SM8350_MASTER_ROTATOR] = &qxm_rot,
+	[SM8350_SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+	[SM8350_SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+	[SM8350_SLAVE_SERVICE_MNOC] = &srvc_mnoc,
+	[SM8350_MASTER_MDP0_DISP] = &qxm_mdp0_disp,
+	[SM8350_MASTER_MDP1_DISP] = &qxm_mdp1_disp,
+	[SM8350_MASTER_ROTATOR_DISP] = &qxm_rot_disp,
+	[SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
+	[SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
+};
+
+static struct qcom_icc_desc sm8350_mmss_noc = {
+	.nodes = mmss_noc_nodes,
+	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+	.bcms = mmss_noc_bcms,
+	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm *nsp_noc_bcms[] = {
+	&bcm_co0,
+	&bcm_co3,
+};
+
+static struct qcom_icc_node *nsp_noc_nodes[] = {
+	[SM8350_MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
+	[SM8350_MASTER_CDSP_PROC] = &qxm_nsp,
+	[SM8350_SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+	[SM8350_SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
+};
+
+static struct qcom_icc_desc sm8350_compute_noc = {
+	.nodes = nsp_noc_nodes,
+	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
+	.bcms = nsp_noc_bcms,
+	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
+};
+
+static struct qcom_icc_bcm *system_noc_bcms[] = {
+	&bcm_sn0,
+	&bcm_sn2,
+	&bcm_sn7,
+	&bcm_sn8,
+};
+
+static struct qcom_icc_node *system_noc_nodes[] = {
+	[SM8350_MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
+	[SM8350_MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
+	[SM8350_MASTER_SNOC_CFG] = &qnm_snoc_cfg,
+	[SM8350_MASTER_PIMEM] = &qxm_pimem,
+	[SM8350_MASTER_GIC] = &xm_gic,
+	[SM8350_SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
+	[SM8350_SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+	[SM8350_SLAVE_SERVICE_SNOC] = &srvc_snoc,
+};
+
+static struct qcom_icc_desc sm8350_system_noc = {
+	.nodes = system_noc_nodes,
+	.num_nodes = ARRAY_SIZE(system_noc_nodes),
+	.bcms = system_noc_bcms,
+	.num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static int qnoc_probe(struct platform_device *pdev)
+{
+	const struct qcom_icc_desc *desc;
+	struct icc_onecell_data *data;
+	struct icc_provider *provider;
+	struct qcom_icc_node **qnodes;
+	struct qcom_icc_provider *qp;
+	struct icc_node *node;
+	size_t num_nodes, i;
+	int ret;
+
+	desc = of_device_get_match_data(&pdev->dev);
+	if (!desc)
+		return -EINVAL;
+
+	qnodes = desc->nodes;
+	num_nodes = desc->num_nodes;
+
+	qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
+	if (!qp)
+		return -ENOMEM;
+
+	data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	provider = &qp->provider;
+	provider->dev = &pdev->dev;
+	provider->set = qcom_icc_set;
+	provider->pre_aggregate = qcom_icc_pre_aggregate;
+	provider->aggregate = qcom_icc_aggregate;
+	provider->xlate = of_icc_xlate_onecell;
+	INIT_LIST_HEAD(&provider->nodes);
+	provider->data = data;
+
+	qp->dev = &pdev->dev;
+	qp->bcms = desc->bcms;
+	qp->num_bcms = desc->num_bcms;
+
+	qp->voter = of_bcm_voter_get(qp->dev, NULL);
+	if (IS_ERR(qp->voter))
+		return PTR_ERR(qp->voter);
+
+	ret = icc_provider_add(provider);
+	if (ret) {
+		dev_err(&pdev->dev, "error adding interconnect provider\n");
+		return ret;
+	}
+
+	for (i = 0; i < qp->num_bcms; i++)
+		qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
+
+	for (i = 0; i < num_nodes; i++) {
+		size_t j;
+
+		if (!qnodes[i])
+			continue;
+
+		node = icc_node_create(qnodes[i]->id);
+		if (IS_ERR(node)) {
+			ret = PTR_ERR(node);
+			goto err;
+		}
+
+		node->name = qnodes[i]->name;
+		node->data = qnodes[i];
+		icc_node_add(node, provider);
+
+		for (j = 0; j < qnodes[i]->num_links; j++)
+			icc_link_create(node, qnodes[i]->links[j]);
+
+		data->nodes[i] = node;
+	}
+	data->num_nodes = num_nodes;
+
+	platform_set_drvdata(pdev, qp);
+
+	return ret;
+
+err:
+	icc_nodes_remove(provider);
+	icc_provider_del(provider);
+	return ret;
+}
+
+static int qnoc_remove(struct platform_device *pdev)
+{
+	struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
+
+	icc_nodes_remove(&qp->provider);
+	return icc_provider_del(&qp->provider);
+}
+
+static const struct of_device_id qnoc_of_match[] = {
+	{ .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
+	{ .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
+	{ .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
+	{ .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
+	{ .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
+	{ .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
+	{ .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
+	{ .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
+	{ .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
+	{ .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+	.probe = qnoc_probe,
+	.remove = qnoc_remove,
+	.driver = {
+		.name = "qnoc-sm8350",
+		.of_match_table = qnoc_of_match,
+		.sync_state = icc_sync_state,
+	},
+};
+module_platform_driver(qnoc_driver);
+
+MODULE_DESCRIPTION("SM8350 NoC driver");
+MODULE_LICENSE("GPL v2");
-- 
2.26.2


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
  2021-02-10 10:47 [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Vinod Koul
  2021-02-10 10:47 ` [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver Vinod Koul
@ 2021-02-10 11:30 ` Georgi Djakov
  2021-02-10 12:07   ` Vinod Koul
  1 sibling, 1 reply; 6+ messages in thread
From: Georgi Djakov @ 2021-02-10 11:30 UTC (permalink / raw)
  To: Vinod Koul
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Rob Herring,
	Odelu Kukatla, linux-pm, devicetree, linux-kernel

Hi Vinod,

On 2/10/21 12:47, Vinod Koul wrote:
> The Qualcomm SM8350 platform has several bus fabrics that could be
> controlled and tuned dynamically according to the bandwidth demand.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>   .../bindings/interconnect/qcom,rpmh.yaml      |  10 ++
>   .../dt-bindings/interconnect/qcom,sm8350.h    | 169 ++++++++++++++++++
>   2 files changed, 179 insertions(+)
>   create mode 100644 include/dt-bindings/interconnect/qcom,sm8350.h
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> index 30c2a092d2d3..e47f2aa0c61b 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
> @@ -67,6 +67,16 @@ properties:
>         - qcom,sm8250-mmss-noc
>         - qcom,sm8250-npu-noc
>         - qcom,sm8250-system-noc
> +      - qcom,sm8350-aggre1-noc
> +      - qcom,sm8350-aggre2-noc
> +      - qcom,sm8350-config-noc
> +      - qcom,sm8350-dc-noc
> +      - qcom,sm8350-gem-noc
> +      - qcom,sm8350-lpass-ag-noc
> +      - qcom,sm8350-mc-virt
> +      - qcom,sm8350-mmss-noc
> +      - qcom,sm8350-compute-noc
> +      - qcom,sm8350-system-noc
>   
>     '#interconnect-cells':
>       const: 1
> diff --git a/include/dt-bindings/interconnect/qcom,sm8350.h b/include/dt-bindings/interconnect/qcom,sm8350.h
> new file mode 100644
> index 000000000000..8633c58b3b80
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,sm8350.h
> @@ -0,0 +1,169 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Qualcomm SM8350 interconnect IDs
> + *
> + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2021, Linaro Limited
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
> +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
> +
> +#define SM8350_MASTER_GPU_TCU				0
> +#define SM8350_MASTER_SYS_TCU				1
> +#define SM8350_MASTER_APPSS_PROC			2
> +#define SM8350_MASTER_LLCC				3
> +#define SM8350_MASTER_CNOC_LPASS_AG_NOC			4
> +#define SM8350_MASTER_CDSP_NOC_CFG			5
> +#define SM8350_MASTER_QDSS_BAM				6
> +#define SM8350_MASTER_QSPI_0				7
> +#define SM8350_MASTER_QUP_0				8
> +#define SM8350_MASTER_QUP_1				9
> +#define SM8350_MASTER_QUP_2				10
> +#define SM8350_MASTER_A1NOC_CFG				11
> +#define SM8350_MASTER_A2NOC_CFG				12
> +#define SM8350_MASTER_A1NOC_SNOC			13
> +#define SM8350_MASTER_A2NOC_SNOC			14
> +#define SM8350_MASTER_CAMNOC_HF				15
> +#define SM8350_MASTER_CAMNOC_ICP			16
> +#define SM8350_MASTER_CAMNOC_SF				17
> +#define SM8350_MASTER_COMPUTE_NOC			18
> +#define SM8350_MASTER_CNOC_DC_NOC			19
> +#define SM8350_MASTER_GEM_NOC_CFG			20
> +#define SM8350_MASTER_GEM_NOC_CNOC			21
> +#define SM8350_MASTER_GEM_NOC_PCIE_SNOC			22
> +#define SM8350_MASTER_GFX3D				23
> +#define SM8350_MASTER_CNOC_MNOC_CFG			24
> +#define SM8350_MASTER_MNOC_HF_MEM_NOC			25
> +#define SM8350_MASTER_MNOC_SF_MEM_NOC			26
> +#define SM8350_MASTER_ANOC_PCIE_GEM_NOC			27
> +#define SM8350_MASTER_SNOC_CFG				28
> +#define SM8350_MASTER_SNOC_GC_MEM_NOC			29
> +#define SM8350_MASTER_SNOC_SF_MEM_NOC			30
> +#define SM8350_MASTER_VIDEO_P0				31
> +#define SM8350_MASTER_VIDEO_P1				32
> +#define SM8350_MASTER_VIDEO_PROC			33
> +#define SM8350_MASTER_QUP_CORE_0			34
> +#define SM8350_MASTER_QUP_CORE_1			35
> +#define SM8350_MASTER_QUP_CORE_2			36
> +#define SM8350_MASTER_CRYPTO				37
> +#define SM8350_MASTER_IPA				38
> +#define SM8350_MASTER_MDP0				39
> +#define SM8350_MASTER_MDP1				40
> +#define SM8350_MASTER_CDSP_PROC				41
> +#define SM8350_MASTER_PIMEM				42
> +#define SM8350_MASTER_ROTATOR				43
> +#define SM8350_MASTER_GIC				44
> +#define SM8350_MASTER_PCIE_0				45
> +#define SM8350_MASTER_PCIE_1				46
> +#define SM8350_MASTER_QDSS_DAP				47
> +#define SM8350_MASTER_QDSS_ETR				48
> +#define SM8350_MASTER_SDCC_2				49
> +#define SM8350_MASTER_SDCC_4				50
> +#define SM8350_MASTER_UFS_CARD				51
> +#define SM8350_MASTER_UFS_MEM				52
> +#define SM8350_MASTER_USB3_0				53
> +#define SM8350_MASTER_USB3_1				54
> +#define SM8350_SLAVE_EBI1				512
> +#define SM8350_SLAVE_AHB2PHY_SOUTH			513
> +#define SM8350_SLAVE_AHB2PHY_NORTH			514
> +#define SM8350_SLAVE_AOSS				515
> +#define SM8350_SLAVE_APPSS				516
> +#define SM8350_SLAVE_CAMERA_CFG				517
> +#define SM8350_SLAVE_CLK_CTL				518
> +#define SM8350_SLAVE_CDSP_CFG				519
> +#define SM8350_SLAVE_RBCPR_CX_CFG			520
> +#define SM8350_SLAVE_RBCPR_MMCX_CFG			521
> +#define SM8350_SLAVE_RBCPR_MX_CFG			522
> +#define SM8350_SLAVE_CRYPTO_0_CFG			523
> +#define SM8350_SLAVE_CX_RDPM				524
> +#define SM8350_SLAVE_DCC_CFG				525
> +#define SM8350_SLAVE_DISPLAY_CFG			526
> +#define SM8350_SLAVE_GFX3D_CFG				527
> +#define SM8350_SLAVE_HWKM				528
> +#define SM8350_SLAVE_IMEM_CFG				529
> +#define SM8350_SLAVE_IPA_CFG				530
> +#define SM8350_SLAVE_IPC_ROUTER_CFG			531
> +#define SM8350_SLAVE_LLCC_CFG				532
> +#define SM8350_SLAVE_LPASS				533
> +#define SM8350_SLAVE_LPASS_CORE_CFG			534
> +#define SM8350_SLAVE_LPASS_LPI_CFG			535
> +#define SM8350_SLAVE_LPASS_MPU_CFG			536
> +#define SM8350_SLAVE_LPASS_TOP_CFG			537
> +#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG		538
> +#define SM8350_SLAVE_MCDMA_MS_MPU_CFG			539
> +#define SM8350_SLAVE_CNOC_MSS				540
> +#define SM8350_SLAVE_MX_RDPM				541
> +#define SM8350_SLAVE_PCIE_0_CFG				542
> +#define SM8350_SLAVE_PCIE_1_CFG				543
> +#define SM8350_SLAVE_PDM				544
> +#define SM8350_SLAVE_PIMEM_CFG				545
> +#define SM8350_SLAVE_PKA_WRAPPER_CFG			546
> +#define SM8350_SLAVE_PMU_WRAPPER_CFG			547
> +#define SM8350_SLAVE_QDSS_CFG				548
> +#define SM8350_SLAVE_QSPI_0				549
> +#define SM8350_SLAVE_QUP_0				550
> +#define SM8350_SLAVE_QUP_1				551
> +#define SM8350_SLAVE_QUP_2				552
> +#define SM8350_SLAVE_SDCC_2				553
> +#define SM8350_SLAVE_SDCC_4				554
> +#define SM8350_SLAVE_SECURITY				555
> +#define SM8350_SLAVE_SPSS_CFG				556
> +#define SM8350_SLAVE_TCSR				557
> +#define SM8350_SLAVE_TLMM				558
> +#define SM8350_SLAVE_UFS_CARD_CFG			559
> +#define SM8350_SLAVE_UFS_MEM_CFG			560
> +#define SM8350_SLAVE_USB3_0				561
> +#define SM8350_SLAVE_USB3_1				562
> +#define SM8350_SLAVE_VENUS_CFG				563
> +#define SM8350_SLAVE_VSENSE_CTRL_CFG			564
> +#define SM8350_SLAVE_A1NOC_CFG				565
> +#define SM8350_SLAVE_A1NOC_SNOC				566
> +#define SM8350_SLAVE_A2NOC_CFG				567
> +#define SM8350_SLAVE_A2NOC_SNOC				568
> +#define SM8350_SLAVE_DDRSS_CFG				569
> +#define SM8350_SLAVE_GEM_NOC_CNOC			570
> +#define SM8350_SLAVE_GEM_NOC_CFG			571
> +#define SM8350_SLAVE_SNOC_GEM_NOC_GC			572
> +#define SM8350_SLAVE_SNOC_GEM_NOC_SF			573
> +#define SM8350_SLAVE_LLCC				574
> +#define SM8350_SLAVE_MNOC_HF_MEM_NOC			575
> +#define SM8350_SLAVE_MNOC_SF_MEM_NOC			576
> +#define SM8350_SLAVE_CNOC_MNOC_CFG			577
> +#define SM8350_SLAVE_CDSP_MEM_NOC			578
> +#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC			579
> +#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC			580
> +#define SM8350_SLAVE_SNOC_CFG				581
> +#define SM8350_SLAVE_QUP_CORE_0				582
> +#define SM8350_SLAVE_QUP_CORE_1				583
> +#define SM8350_SLAVE_QUP_CORE_2				584
> +#define SM8350_SLAVE_BOOT_IMEM				585
> +#define SM8350_SLAVE_IMEM				586
> +#define SM8350_SLAVE_PIMEM				587
> +#define SM8350_SLAVE_SERVICE_NSP_NOC			588
> +#define SM8350_SLAVE_SERVICE_A1NOC			589
> +#define SM8350_SLAVE_SERVICE_A2NOC			590
> +#define SM8350_SLAVE_SERVICE_CNOC			591
> +#define SM8350_SLAVE_SERVICE_GEM_NOC_1			592
> +#define SM8350_SLAVE_SERVICE_MNOC			593
> +#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC		594
> +#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC		595
> +#define SM8350_SLAVE_SERVICE_GEM_NOC_2			596
> +#define SM8350_SLAVE_SERVICE_SNOC			597
> +#define SM8350_SLAVE_SERVICE_GEM_NOC			598
> +#define SM8350_SLAVE_PCIE_0				599
> +#define SM8350_SLAVE_PCIE_1				600
> +#define SM8350_SLAVE_QDSS_STM				601
> +#define SM8350_SLAVE_TCU				602
> +#define SM8350_MASTER_LLCC_DISP				1000
> +#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP		1001
> +#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP		1002
> +#define SM8350_MASTER_MDP0_DISP				1003
> +#define SM8350_MASTER_MDP1_DISP				1004
> +#define SM8350_MASTER_ROTATOR_DISP			1005
> +#define SM8350_SLAVE_EBI1_DISP				1512
> +#define SM8350_SLAVE_LLCC_DISP				1513
> +#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP		1514
> +#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP		1515

Why are you using these big numbers? They are used as array indexes
and we will be wasting a lot of memory for unnecessary large arrays.

Thanks,
Georgi

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver
  2021-02-10 10:47 ` [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver Vinod Koul
@ 2021-02-10 11:40   ` Georgi Djakov
  2021-02-10 12:10     ` Vinod Koul
  0 siblings, 1 reply; 6+ messages in thread
From: Georgi Djakov @ 2021-02-10 11:40 UTC (permalink / raw)
  To: Vinod Koul
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Rob Herring,
	Odelu Kukatla, linux-pm, devicetree, linux-kernel

Hi Vinod,

On 2/10/21 12:47, Vinod Koul wrote:
> Add driver for the Qualcomm interconnect buses found in SM8i350 based

SM8i350?

> platforms. The topology consists of several NoCs that are controlled by
> a remote processor that collects the aggregated bandwidth for each
> master-slave pairs.
> 
> Generated from downstream interconnect driver written by David Dai
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>   drivers/interconnect/qcom/Kconfig  |  10 +
>   drivers/interconnect/qcom/Makefile |   2 +
>   drivers/interconnect/qcom/sm8350.c | 635 +++++++++++++++++++++++++++++
>   3 files changed, 647 insertions(+)
>   create mode 100644 drivers/interconnect/qcom/sm8350.c
> 
> diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
> index a8f93ba265f8..2ad0aea8336a 100644
> --- a/drivers/interconnect/qcom/Kconfig
> +++ b/drivers/interconnect/qcom/Kconfig
> @@ -85,5 +85,15 @@ config INTERCONNECT_QCOM_SM8250
>   	  This is a driver for the Qualcomm Network-on-Chip on sm8250-based
>   	  platforms.
>   
> +config INTERCONNECT_QCOM_SM8350
> +	tristate "Qualcomm SM8350 interconnect driver"
> +	depends on INTERCONNECT_QCOM
> +	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST

Maybe depend on INTERCONNECT_QCOM_RPMH_POSSIBLE instead of the above.

Thanks,
Georgi

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings
  2021-02-10 11:30 ` [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Georgi Djakov
@ 2021-02-10 12:07   ` Vinod Koul
  0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-10 12:07 UTC (permalink / raw)
  To: Georgi Djakov
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Rob Herring,
	Odelu Kukatla, linux-pm, devicetree, linux-kernel

Hi Gerogi,

On 10-02-21, 13:30, Georgi Djakov wrote:

> > +#define SM8350_MASTER_LLCC_DISP				1000
> > +#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP		1001
> > +#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP		1002
> > +#define SM8350_MASTER_MDP0_DISP				1003
> > +#define SM8350_MASTER_MDP1_DISP				1004
> > +#define SM8350_MASTER_ROTATOR_DISP			1005
> > +#define SM8350_SLAVE_EBI1_DISP				1512
> > +#define SM8350_SLAVE_LLCC_DISP				1513
> > +#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP		1514
> > +#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP		1515
> 
> Why are you using these big numbers? They are used as array indexes
> and we will be wasting a lot of memory for unnecessary large arrays.

Thanks for the explanation, yes that would be the case. I will split it
up and send v2

-- 
~Vinod

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver
  2021-02-10 11:40   ` Georgi Djakov
@ 2021-02-10 12:10     ` Vinod Koul
  0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-02-10 12:10 UTC (permalink / raw)
  To: Georgi Djakov
  Cc: linux-arm-msm, Bjorn Andersson, Andy Gross, Rob Herring,
	Odelu Kukatla, linux-pm, devicetree, linux-kernel

On 10-02-21, 13:40, Georgi Djakov wrote:
> Hi Vinod,
> 
> On 2/10/21 12:47, Vinod Koul wrote:
> > Add driver for the Qualcomm interconnect buses found in SM8i350 based
> 
> SM8i350?

fumble fingers :(

> 
> > platforms. The topology consists of several NoCs that are controlled by
> > a remote processor that collects the aggregated bandwidth for each
> > master-slave pairs.
> > 
> > Generated from downstream interconnect driver written by David Dai
> > 
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >   drivers/interconnect/qcom/Kconfig  |  10 +
> >   drivers/interconnect/qcom/Makefile |   2 +
> >   drivers/interconnect/qcom/sm8350.c | 635 +++++++++++++++++++++++++++++
> >   3 files changed, 647 insertions(+)
> >   create mode 100644 drivers/interconnect/qcom/sm8350.c
> > 
> > diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
> > index a8f93ba265f8..2ad0aea8336a 100644
> > --- a/drivers/interconnect/qcom/Kconfig
> > +++ b/drivers/interconnect/qcom/Kconfig
> > @@ -85,5 +85,15 @@ config INTERCONNECT_QCOM_SM8250
> >   	  This is a driver for the Qualcomm Network-on-Chip on sm8250-based
> >   	  platforms.
> > +config INTERCONNECT_QCOM_SM8350
> > +	tristate "Qualcomm SM8350 interconnect driver"
> > +	depends on INTERCONNECT_QCOM
> > +	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
> 
> Maybe depend on INTERCONNECT_QCOM_RPMH_POSSIBLE instead of the above.

That seems to be new thingy in next, sure will update to that as well

Thanks for quick review.

-- 
~Vinod

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-02-10 12:14 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-10 10:47 [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Vinod Koul
2021-02-10 10:47 ` [PATCH 2/2] interconnect: qcom: Add SM8350 interconnect provider driver Vinod Koul
2021-02-10 11:40   ` Georgi Djakov
2021-02-10 12:10     ` Vinod Koul
2021-02-10 11:30 ` [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM8350 DT bindings Georgi Djakov
2021-02-10 12:07   ` Vinod Koul

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).