From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
martin.botka@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Taniya Das <tdas@codeaurora.org>,
Craig Tatlor <ctatlor97@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH 2/6] clk: qcom: gcc-sdm660: Set HWCG bit to 1 on some clocks
Date: Sat, 20 Feb 2021 16:56:13 +0100 [thread overview]
Message-ID: <20210220155618.176559-2-konrad.dybcio@somainline.org> (raw)
In-Reply-To: <20210220155618.176559-1-konrad.dybcio@somainline.org>
According to the downstream kernel, some clocks need to have
HWCG disabled. Fix it.
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
drivers/clk/qcom/gcc-sdm660.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 597800ce1bdf..2bf4e29462e8 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -980,6 +980,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
static struct clk_branch gcc_aggre2_ufs_axi_clk = {
.halt_reg = 0x75034,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x75034,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75034,
.enable_mask = BIT(0),
@@ -1027,6 +1029,8 @@ static struct clk_branch gcc_bimc_gfx_clk = {
static struct clk_branch gcc_bimc_hmss_axi_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x48004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
@@ -1698,6 +1702,8 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
.halt_reg = 0x9000,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x9000,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x9000,
.enable_mask = BIT(0),
@@ -1956,6 +1962,8 @@ static struct clk_branch gcc_ufs_ahb_clk = {
static struct clk_branch gcc_ufs_axi_clk = {
.halt_reg = 0x75008,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x75008,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75008,
.enable_mask = BIT(0),
--
2.30.1
next prev parent reply other threads:[~2021-02-20 15:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-20 15:56 [PATCH 1/6] clk: qcom: gcc-sdm660: Fix hmss_gpll0_clk_src parent_map Konrad Dybcio
2021-02-20 15:56 ` Konrad Dybcio [this message]
2021-02-20 15:56 ` [PATCH 3/6] clk: qcom: gcc-sdm660: Add missing clocks and GDSCs Konrad Dybcio
2021-02-20 15:56 ` [PATCH 4/6] clk: qcom: gcc-sdm660: Remove gds_hw_ctrl from GDSCs Konrad Dybcio
2021-02-20 15:56 ` [PATCH 5/6] clk: qcom: gcc-sdm660: Account for needed adjustments in probe function Konrad Dybcio
2021-02-23 0:39 ` Stephen Boyd
2021-02-25 19:09 ` Konrad Dybcio
2021-04-01 1:53 ` Stephen Boyd
2021-04-01 21:10 ` Konrad Dybcio
2021-05-26 19:11 ` Konrad Dybcio
2021-05-26 22:32 ` Stephen Boyd
2021-02-20 15:56 ` [PATCH 6/6] clk: qcom: gcc-sdm660: Add CLK_SET_RATE_PARENT where applicable Konrad Dybcio
2021-02-23 0:42 ` Stephen Boyd
2021-02-25 19:27 ` Konrad Dybcio
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