Cleanup several Qualcomm clock drivers by removing unused entries from parents map, removing test clock, etc. Changes since v3: - Use ARRAY_SIZE() for num_parents and parent_hws instead of parent_data where applicable as suggested by Marijn Suijten These changes are applied both as a part of 'convert ot parent data' patches and as separate changes to respective clock drivers (which already used parent_data). Changes since v2: - Comment out unsupported video_pll0_out_odd/_even clocks instead of removing them or just using .name for them. The clocks are unsupported, but mux values are provided for the future reference. Changes since v1: - Remove unused entries from gpucc-sc7180, gpucc-sdm845, videocc-sc7180 and videocc-sm8150 drivers - Restore video_pll0_out_odd/_even entries in videocc-sdm845 driver as requested by Taniya Das.
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/dispcc-sc7180.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index f487515701e3..3334bf9cfb94 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -19,8 +19,6 @@ enum { P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, P_DISP_CC_PLL0_OUT_EVEN, P_DISP_CC_PLL0_OUT_MAIN, P_DP_PHY_PLL_LINK_CLK, -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 588575e1169d..86275814e055 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -21,23 +21,15 @@ enum { P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, P_DISP_CC_PLL0_OUT_MAIN, P_DISP_CC_PLL1_OUT_EVEN, P_DISP_CC_PLL1_OUT_MAIN, P_DP_PHY_PLL_LINK_CLK, P_DP_PHY_PLL_VCO_DIV_CLK, - P_DPTX1_PHY_PLL_LINK_CLK, - P_DPTX1_PHY_PLL_VCO_DIV_CLK, - P_DPTX2_PHY_PLL_LINK_CLK, - P_DPTX2_PHY_PLL_VCO_DIV_CLK, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_DSI1_PHY_PLL_OUT_BYTECLK, P_DSI1_PHY_PLL_OUT_DSICLK, - P_EDP_PHY_PLL_LINK_CLK, - P_EDP_PHY_PLL_VCO_DIV_CLK, }; static struct pll_vco vco_table[] = { -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index ab594a0f0c40..86626a027f6f 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -25,7 +25,6 @@ enum { P_BI_TCXO, P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_EVEN, P_GPLL0_OUT_MAIN, P_GPLL4_OUT_MAIN, -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sc7180.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index 88a739b6fec3..d738251cba17 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -26,12 +26,9 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, - P_GPU_CC_PLL1_OUT_EVEN, P_GPU_CC_PLL1_OUT_MAIN, - P_GPU_CC_PLL1_OUT_ODD, }; static const struct pll_vco fabia_vco[] = { -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sdm845.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index 5663698b306b..2d7dc89915e8 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -30,9 +30,7 @@ enum { P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, - P_GPU_CC_PLL1_OUT_EVEN, P_GPU_CC_PLL1_OUT_MAIN, - P_GPU_CC_PLL1_OUT_ODD, }; static const struct parent_map gpu_cc_parent_map_0[] = { -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sm8150.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c index 27c40754b2c7..2b952f561537 100644 --- a/drivers/clk/qcom/gpucc-sm8150.c +++ b/drivers/clk/qcom/gpucc-sm8150.c @@ -21,7 +21,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_CC_PLL1_OUT_MAIN, -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/gpucc-sm8250.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c index 3fa7d1f9ff98..67c136a77efb 100644 --- a/drivers/clk/qcom/gpucc-sm8250.c +++ b/drivers/clk/qcom/gpucc-sm8250.c @@ -26,7 +26,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_CC_PLL0_OUT_MAIN, -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/videocc-sc7180.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index 276e5ecd4840..ed57bbb19f88 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -19,11 +19,7 @@ enum { P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, - P_VIDEO_PLL0_OUT_EVEN, P_VIDEO_PLL0_OUT_MAIN, - P_VIDEO_PLL0_OUT_ODD, }; static const struct pll_vco fabia_vco[] = { -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sm8150.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index 3087e2ec8fd4..85b0bbc2b151 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -20,11 +20,7 @@ enum { P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, - P_VIDEO_PLL0_OUT_EVEN, P_VIDEO_PLL0_OUT_MAIN, - P_VIDEO_PLL0_OUT_ODD, }; static struct pll_vco trion_vco[] = { -- 2.30.2
Drop unused enum entries from the list of parent enums. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sm8250.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index b0efadc19634..06a8a2c98deb 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -21,8 +21,6 @@ enum { P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, P_VIDEO_PLL0_OUT_MAIN, P_VIDEO_PLL1_OUT_MAIN, }; -- 2.30.2
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sdm845.c | 216 ++++++++++++++++--------------- 1 file changed, 109 insertions(+), 107 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 5c932cd17b14..aef1024c5318 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -33,6 +33,21 @@ enum { P_DP_PHY_PLL_VCO_DIV_CLK, }; +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, @@ -40,11 +55,11 @@ static const struct parent_map disp_cc_parent_map_0[] = { { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_0[] = { - "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi1_phy_pll_out_byteclk", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_1[] = { @@ -54,11 +69,11 @@ static const struct parent_map disp_cc_parent_map_1[] = { { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_1[] = { - "bi_tcxo", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" }, + { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_2[] = { @@ -66,9 +81,9 @@ static const struct parent_map disp_cc_parent_map_2[] = { { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_2[] = { - "bi_tcxo", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -79,12 +94,12 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_3[] = { - "bi_tcxo", - "disp_cc_pll0", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "core_bi_pll_test_se", +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { @@ -94,24 +109,11 @@ static const struct parent_map disp_cc_parent_map_4[] = { { P_CORE_BI_PLL_TEST_SE, 7 }, }; -static const char * const disp_cc_parent_names_4[] = { - "bi_tcxo", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_dsiclk", - "core_bi_pll_test_se", -}; - -static struct clk_alpha_pll disp_cc_pll0 = { - .offset = 0x0, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_fabia_ops, - }, - }, +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; /* Return the HW recalc rate for idle use case */ @@ -122,8 +124,8 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .parent_map = disp_cc_parent_map_0, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -137,8 +139,8 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .parent_map = disp_cc_parent_map_0, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -157,8 +159,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk_src", - .parent_names = disp_cc_parent_names_2, - .num_parents = 2, + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -171,8 +173,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .parent_map = disp_cc_parent_map_1, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .ops = &clk_byte2_ops, }, }; @@ -184,8 +186,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .parent_map = disp_cc_parent_map_1, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -198,8 +200,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { .parent_map = disp_cc_parent_map_1, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel1_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -212,8 +214,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .parent_map = disp_cc_parent_map_1, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_dp_ops, }, @@ -232,8 +234,8 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -246,8 +248,8 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 4, + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -273,8 +275,8 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -287,8 +289,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .parent_map = disp_cc_parent_map_4, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", - .parent_names = disp_cc_parent_names_4, - .num_parents = 4, + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -302,8 +304,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .parent_map = disp_cc_parent_map_4, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk_src", - .parent_names = disp_cc_parent_names_4, - .num_parents = 4, + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -326,8 +328,8 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -340,8 +342,8 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", - .parent_names = disp_cc_parent_names_2, - .num_parents = 2, + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -381,8 +383,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -399,8 +401,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_div_clk_src", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -417,8 +419,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -436,8 +438,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -454,8 +456,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_div_clk_src", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -472,8 +474,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte1_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -490,8 +492,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_aux_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -508,8 +510,8 @@ static struct clk_branch disp_cc_mdss_dp_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_crypto_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -526,8 +528,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_link_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -545,8 +547,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_link_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -562,8 +564,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_pixel1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -580,8 +582,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_pixel_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -598,8 +600,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_esc0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -616,8 +618,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_esc1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -634,8 +636,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -652,8 +654,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -670,8 +672,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_pclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -689,8 +691,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_pclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -707,8 +709,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_rot_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -738,8 +740,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -756,8 +758,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sdm845.c | 44 +++++++++++++++++---------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index 2d7dc89915e8..b38a4bccdc96 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -33,22 +33,6 @@ enum { P_GPU_CC_PLL1_OUT_MAIN, }; -static const struct parent_map gpu_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPU_CC_PLL1_OUT_MAIN, 3 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gpu_cc_parent_names_0[] = { - "bi_tcxo", - "gpu_cc_pll1", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src", - "core_bi_pll_test_se", -}; - static const struct alpha_pll_config gpu_cc_pll1_config = { .l = 0x1a, .alpha = 0xaab, @@ -60,13 +44,31 @@ static struct clk_alpha_pll gpu_cc_pll1 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpu_cc_pll1", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, }, }; +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), @@ -82,8 +84,8 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", - .parent_names = gpu_cc_parent_names_0, - .num_parents = 5, + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -96,8 +98,8 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gmu_clk", - .parent_names = (const char *[]){ - "gpu_cc_gmu_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sdm845.c | 56 ++++++++++++++++--------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index 5d6a7724a194..f1dd97032a4b 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -21,25 +21,9 @@ enum { P_BI_TCXO, P_CORE_BI_PLL_TEST_SE, - P_VIDEO_PLL0_OUT_EVEN, P_VIDEO_PLL0_OUT_MAIN, - P_VIDEO_PLL0_OUT_ODD, -}; - -static const struct parent_map video_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_VIDEO_PLL0_OUT_MAIN, 1 }, - { P_VIDEO_PLL0_OUT_EVEN, 2 }, - { P_VIDEO_PLL0_OUT_ODD, 3 }, - { P_CORE_BI_PLL_TEST_SE, 4 }, -}; - -static const char * const video_cc_parent_names_0[] = { - "bi_tcxo", - "video_pll0", - "video_pll0_out_even", - "video_pll0_out_odd", - "core_bi_pll_test_se", + /* P_VIDEO_PLL0_OUT_EVEN, + P_VIDEO_PLL0_OUT_ODD, */ }; static const struct alpha_pll_config video_pll0_config = { @@ -53,13 +37,31 @@ static struct clk_alpha_pll video_pll0 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "video_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, }, }; +static const struct parent_map video_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, + /* { P_VIDEO_PLL0_OUT_EVEN, 2 }, + { P_VIDEO_PLL0_OUT_ODD, 3 }, */ + { P_CORE_BI_PLL_TEST_SE, 4 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &video_pll0.clkr.hw }, + /* { .name = "video_pll0_out_even" }, + { .name = "video_pll0_out_odd" }, */ + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), @@ -78,8 +80,8 @@ static struct clk_rcg2 video_cc_venus_clk_src = { .freq_tbl = ftbl_video_cc_venus_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "video_cc_venus_clk_src", - .parent_names = video_cc_parent_names_0, - .num_parents = 5, + .parent_data = video_cc_parent_data_0, + .num_parents = ARRAY_SIZE(video_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -158,8 +160,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_vcodec0_core_clk", - .parent_names = (const char *[]){ - "video_cc_venus_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -189,8 +191,8 @@ static struct clk_branch video_cc_vcodec1_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_vcodec1_core_clk", - .parent_names = (const char *[]){ - "video_cc_venus_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -233,8 +235,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_venus_ctl_core_clk", - .parent_names = (const char *[]){ - "video_cc_venus_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sdm845.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index b38a4bccdc96..110b54401bc6 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -27,7 +27,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_CC_PLL1_OUT_MAIN, @@ -58,7 +57,6 @@ static const struct parent_map gpu_cc_parent_map_0[] = { { P_GPU_CC_PLL1_OUT_MAIN, 3 }, { P_GPLL0_OUT_MAIN, 5 }, { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gpu_cc_parent_data_0[] = { @@ -66,7 +64,6 @@ static const struct clk_parent_data gpu_cc_parent_data_0[] = { { .hw = &gpu_cc_pll1.clkr.hw }, { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" }, { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { -- 2.30.2
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sdm845.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index aef1024c5318..735adfefc379 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -21,7 +21,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, @@ -52,38 +51,32 @@ static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" }, { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DP_PHY_PLL_LINK_CLK, 1 }, { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" }, { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_3[] = { @@ -91,7 +84,6 @@ static const struct parent_map disp_cc_parent_map_3[] = { { P_DISP_CC_PLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_MAIN, 4 }, { P_GPLL0_OUT_MAIN_DIV, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { @@ -99,21 +91,18 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { { .hw = &disp_cc_pll0.clkr.hw }, { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" }, { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" }, { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; /* Return the HW recalc rate for idle use case */ -- 2.30.2
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sdm845.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index f1dd97032a4b..24251f5d70b4 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -20,7 +20,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_VIDEO_PLL0_OUT_MAIN, /* P_VIDEO_PLL0_OUT_EVEN, P_VIDEO_PLL0_OUT_ODD, */ @@ -51,7 +50,6 @@ static const struct parent_map video_cc_parent_map_0[] = { { P_VIDEO_PLL0_OUT_MAIN, 1 }, /* { P_VIDEO_PLL0_OUT_EVEN, 2 }, { P_VIDEO_PLL0_OUT_ODD, 3 }, */ - { P_CORE_BI_PLL_TEST_SE, 4 }, }; static const struct clk_parent_data video_cc_parent_data_0[] = { @@ -59,7 +57,6 @@ static const struct clk_parent_data video_cc_parent_data_0[] = { { .hw = &video_pll0.clkr.hw }, /* { .name = "video_pll0_out_even" }, { .name = "video_pll0_out_odd" }, */ - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sc7180.c | 68 ++++++++++++++++---------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c index 3334bf9cfb94..538e4963c915 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -63,8 +63,8 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_pll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_pll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_pll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -317,8 +317,8 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -335,8 +335,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -381,8 +381,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -399,8 +399,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -417,8 +417,8 @@ static struct clk_branch disp_cc_mdss_dp_crypto_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -435,8 +435,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -453,8 +453,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -470,8 +470,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -488,8 +488,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -506,8 +506,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -524,8 +524,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -541,8 +541,8 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -559,8 +559,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -577,8 +577,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -595,8 +595,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -613,8 +613,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8250.c | 116 +++++++++++++++---------------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 86275814e055..de09cd5c209f 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -448,8 +448,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -463,8 +463,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte1_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ops, @@ -478,8 +478,8 @@ static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dp_link1_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ro_ops, @@ -493,8 +493,8 @@ static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dp_link_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_regmap_div_ro_ops, @@ -509,8 +509,8 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -527,8 +527,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -545,8 +545,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -563,8 +563,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -581,8 +581,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_byte1_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -599,8 +599,8 @@ static struct clk_branch disp_cc_mdss_dp_aux1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -617,8 +617,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -635,8 +635,8 @@ static struct clk_branch disp_cc_mdss_dp_link1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -653,8 +653,8 @@ static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link1_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -670,8 +670,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -688,8 +688,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_intf_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -705,8 +705,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -723,8 +723,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -741,8 +741,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -759,8 +759,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -777,8 +777,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_esc1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -795,8 +795,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -813,8 +813,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -830,8 +830,8 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -848,8 +848,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -866,8 +866,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_pclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -884,8 +884,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rot_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -902,8 +902,8 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -920,8 +920,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -938,8 +938,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sc7180.c | 164 +++++++++++++++++----------------- 1 file changed, 82 insertions(+), 82 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index 88e896abb663..4c2f3445e037 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -65,8 +65,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, @@ -78,8 +78,8 @@ static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gcc_pll0_main_div_cdiv", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_fixed_factor_ops, @@ -848,8 +848,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -866,8 +866,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -968,8 +968,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -987,8 +987,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = { .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -1030,8 +1030,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { .enable_mask = BIT(18), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_aon_ops, @@ -1046,8 +1046,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { .enable_mask = BIT(19), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pll0_main_div_cdiv.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1091,8 +1091,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1109,8 +1109,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1127,8 +1127,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1144,8 +1144,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1160,8 +1160,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pll0_main_div_cdiv.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1284,8 +1284,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_npu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1300,8 +1300,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_npu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pll0_main_div_cdiv.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1318,8 +1318,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pdm2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1394,8 +1394,8 @@ static struct clk_branch gcc_qspi_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qspi_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qspi_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1438,8 +1438,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1456,8 +1456,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1474,8 +1474,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1492,8 +1492,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1510,8 +1510,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1528,8 +1528,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1572,8 +1572,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1590,8 +1590,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1608,8 +1608,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1626,8 +1626,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1644,8 +1644,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1662,8 +1662,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1749,8 +1749,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1767,8 +1767,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1798,8 +1798,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1817,8 +1817,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -1865,8 +1865,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1885,8 +1885,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1905,8 +1905,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1951,8 +1951,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1969,8 +1969,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2032,8 +2032,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2050,8 +2050,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2108,8 +2108,8 @@ static struct clk_branch gcc_video_gpll0_div_clk_src = { .enable_mask = BIT(20), .hw.init = &(struct clk_init_data){ .name = "gcc_video_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pll0_main_div_cdiv.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pll0_main_div_cdiv.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sc7280.c | 248 +++++++++++++++++----------------- 1 file changed, 124 insertions(+), 124 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 22736c16ed16..ef734db316df 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_ops, @@ -92,8 +92,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gpll0_out_odd", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_ops, @@ -175,8 +175,8 @@ static struct clk_branch gcc_mss_gpll0_main_div_clk_src = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_gpll0_main_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1244,8 +1244,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_cpuss_ahb_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1259,8 +1259,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1274,8 +1274,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1379,8 +1379,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1399,8 +1399,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1419,8 +1419,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1469,8 +1469,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1489,8 +1489,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1510,8 +1510,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = { .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -1557,8 +1557,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gcc_disp_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1605,8 +1605,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1623,8 +1623,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1641,8 +1641,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1658,8 +1658,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1675,8 +1675,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1734,8 +1734,8 @@ static struct clk_branch gcc_pcie0_phy_rchng_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_phy_rchng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1752,8 +1752,8 @@ static struct clk_branch gcc_pcie1_phy_rchng_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie1_phy_rchng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1770,8 +1770,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1816,8 +1816,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1860,8 +1860,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .enable_mask = BIT(29), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1906,8 +1906,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(30), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1965,8 +1965,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pdm2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2084,8 +2084,8 @@ static struct clk_branch gcc_qspi_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qspi_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qspi_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2128,8 +2128,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2146,8 +2146,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2164,8 +2164,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2182,8 +2182,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2200,8 +2200,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2218,8 +2218,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2236,8 +2236,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s6_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2254,8 +2254,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s7_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2298,8 +2298,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2316,8 +2316,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2334,8 +2334,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2352,8 +2352,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2370,8 +2370,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2388,8 +2388,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2406,8 +2406,8 @@ static struct clk_branch gcc_qupv3_wrap1_s6_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s6_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2424,8 +2424,8 @@ static struct clk_branch gcc_qupv3_wrap1_s7_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s7_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2515,8 +2515,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2535,8 +2535,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2566,8 +2566,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2597,8 +2597,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2618,8 +2618,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -2709,8 +2709,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2729,8 +2729,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2749,8 +2749,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2767,8 +2767,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2785,8 +2785,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2803,8 +2803,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_tx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2823,8 +2823,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2841,8 +2841,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2891,8 +2891,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2941,8 +2941,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2959,8 +2959,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2979,8 +2979,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3076,8 +3076,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3094,8 +3094,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3114,8 +3114,8 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sdx55.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index e3b9030b2bae..4fca19006a77 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_ops, @@ -106,8 +106,8 @@ static struct clk_alpha_pll_postdiv gpll4_out_even = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll4.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll4.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_ops, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8150.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 8e9b5b3cceaf..e642fe785c12 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -69,8 +69,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_trion_ops, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8250.c | 252 +++++++++++++++++----------------- 1 file changed, 126 insertions(+), 126 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index 86626a027f6f..5ceadb35289f 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -63,8 +63,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_ops, @@ -1015,8 +1015,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_cpuss_ahb_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1030,8 +1030,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1045,8 +1045,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1077,8 +1077,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_card_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1097,8 +1097,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1115,8 +1115,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1133,8 +1133,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1205,8 +1205,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1223,8 +1223,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1241,8 +1241,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = { .enable_mask = BIT(21), .hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, @@ -1337,8 +1337,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1355,8 +1355,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1373,8 +1373,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1390,8 +1390,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1407,8 +1407,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1530,8 +1530,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { .enable_mask = BIT(18), .hw.init = &(struct clk_init_data){ .name = "gcc_npu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1547,8 +1547,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { .enable_mask = BIT(19), .hw.init = &(struct clk_init_data){ .name = "gcc_npu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1565,8 +1565,8 @@ static struct clk_branch gcc_pcie0_phy_refgen_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_phy_refgen_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1583,8 +1583,8 @@ static struct clk_branch gcc_pcie1_phy_refgen_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie1_phy_refgen_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1601,8 +1601,8 @@ static struct clk_branch gcc_pcie2_phy_refgen_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie2_phy_refgen_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_phy_refgen_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1619,8 +1619,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .enable_mask = BIT(29), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1793,8 +1793,8 @@ static struct clk_branch gcc_pcie_2_aux_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_2_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_2_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1893,8 +1893,8 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1937,8 +1937,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pdm2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2097,8 +2097,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2115,8 +2115,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2133,8 +2133,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2151,8 +2151,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2169,8 +2169,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2187,8 +2187,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2205,8 +2205,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s6_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2223,8 +2223,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s7_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2267,8 +2267,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2285,8 +2285,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2303,8 +2303,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2321,8 +2321,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2339,8 +2339,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2357,8 +2357,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2401,8 +2401,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2419,8 +2419,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2437,8 +2437,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = { .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2455,8 +2455,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2473,8 +2473,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2491,8 +2491,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2606,8 +2606,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2637,8 +2637,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2681,8 +2681,8 @@ static struct clk_branch gcc_tsif_ref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_tsif_ref_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_tsif_ref_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2729,8 +2729,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2749,8 +2749,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2769,8 +2769,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2828,8 +2828,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2863,8 +2863,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2883,8 +2883,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2903,8 +2903,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2962,8 +2962,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2980,8 +2980,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3030,8 +3030,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3080,8 +3080,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3098,8 +3098,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3142,8 +3142,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3160,8 +3160,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8350.c | 310 +++++++++++++++++----------------- 1 file changed, 154 insertions(+), 156 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 1c23b9f84900..10364398407d 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gpll0_out_even", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, @@ -1246,8 +1246,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1261,8 +1261,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1323,8 +1323,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_card_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1343,8 +1343,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1363,8 +1363,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1383,8 +1383,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1403,8 +1403,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1423,8 +1423,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1490,8 +1490,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1510,8 +1510,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_cfg_noc_usb3_sec_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1592,8 +1592,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1610,8 +1610,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1628,8 +1628,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gp3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1646,8 +1646,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1664,8 +1664,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_gpll0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_gpll0_out_even.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_gpll0_out_even.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1723,8 +1723,8 @@ static struct clk_branch gcc_pcie0_phy_rchng_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie0_phy_rchng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1741,8 +1741,8 @@ static struct clk_branch gcc_pcie1_phy_rchng_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie1_phy_rchng_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1759,8 +1759,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(3), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1822,8 +1822,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_0_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1868,8 +1868,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .enable_mask = BIT(29), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1931,8 +1931,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(30), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pcie_1_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1977,8 +1977,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_pdm2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2124,8 +2124,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2142,8 +2142,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2160,8 +2160,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2178,8 +2178,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2196,8 +2196,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2214,8 +2214,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2232,8 +2232,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s6_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2250,8 +2250,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s7_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2324,8 +2324,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { .enable_mask = BIT(22), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2342,8 +2342,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { .enable_mask = BIT(23), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2360,8 +2360,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { .enable_mask = BIT(24), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2378,8 +2378,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { .enable_mask = BIT(25), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2396,8 +2396,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { .enable_mask = BIT(26), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2414,8 +2414,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2458,8 +2458,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2476,8 +2476,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2494,8 +2494,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = { .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2512,8 +2512,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2530,8 +2530,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2548,8 +2548,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s5_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2639,8 +2639,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2670,8 +2670,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2731,8 +2731,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2751,8 +2751,8 @@ static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2771,8 +2771,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2791,8 +2791,8 @@ static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2811,8 +2811,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2831,8 +2831,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_rx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2869,8 +2869,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_rx_symbol_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2888,8 +2888,8 @@ static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_tx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2908,8 +2908,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2928,8 +2928,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_card_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2963,8 +2963,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2983,8 +2983,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3003,8 +3003,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3023,8 +3023,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3043,8 +3043,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3063,8 +3063,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3082,8 +3082,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3101,8 +3101,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3120,8 +3120,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_tx_symbol_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3140,8 +3140,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3160,8 +3160,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3178,8 +3178,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3209,9 +3209,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = - &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3241,8 +3240,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3272,9 +3271,8 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_mock_utmi_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = - &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3304,8 +3302,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3322,8 +3320,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3343,8 +3341,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3374,8 +3372,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3392,8 +3390,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_com_aux_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -3411,8 +3409,8 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_pipe_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sm8150.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c index 2b952f561537..80fb6f73601d 100644 --- a/drivers/clk/qcom/gpucc-sm8150.c +++ b/drivers/clk/qcom/gpucc-sm8150.c @@ -144,8 +144,8 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gmu_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpu_cc_gmu_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -201,8 +201,8 @@ static struct clk_branch gpu_cc_gx_gmu_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gmu_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpu_cc_gmu_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gpucc-sm8250.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c index 67c136a77efb..9c1f8ce32da4 100644 --- a/drivers/clk/qcom/gpucc-sm8250.c +++ b/drivers/clk/qcom/gpucc-sm8250.c @@ -147,8 +147,8 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cx_gmu_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpu_cc_gmu_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -204,8 +204,8 @@ static struct clk_branch gpu_cc_gx_gmu_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_gx_gmu_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpu_cc_gmu_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sm8150.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index 85b0bbc2b151..1afdbe4a249d 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -99,8 +99,8 @@ static struct clk_branch video_cc_iris_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_iris_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_iris_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_iris_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -117,8 +117,8 @@ static struct clk_branch video_cc_mvs0_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs0_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_iris_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_iris_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -135,8 +135,8 @@ static struct clk_branch video_cc_mvs1_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs1_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_iris_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_iris_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -153,8 +153,8 @@ static struct clk_branch video_cc_mvsc_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvsc_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_iris_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_iris_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Switch to using parent_hws instead of parent_data when parents are defined in this driver and so accessible using clk_hw. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/videocc-sm8250.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 06a8a2c98deb..7b435a1c2c4b 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -158,8 +158,8 @@ static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "video_cc_mvs0c_div2_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -173,8 +173,8 @@ static struct clk_regmap_div video_cc_mvs0_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "video_cc_mvs0_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -188,8 +188,8 @@ static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { .width = 2, .clkr.hw.init = &(struct clk_init_data) { .name = "video_cc_mvs1c_div2_div_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -205,8 +205,8 @@ static struct clk_branch video_cc_mvs0c_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs0c_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -223,8 +223,8 @@ static struct clk_branch video_cc_mvs0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs0_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -241,8 +241,8 @@ static struct clk_branch video_cc_mvs1_div2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs1_div2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -259,8 +259,8 @@ static struct clk_branch video_cc_mvs1c_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_mvs1c_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- 2.30.2
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sc7180.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index 4c2f3445e037..cbc520da67f3 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -285,7 +285,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parent_data_0_ao, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -309,7 +309,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_4, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -323,7 +323,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_4, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -337,7 +337,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_4, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -357,7 +357,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -378,7 +378,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qspi_core_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -619,7 +619,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_floor_ops, }, }; @@ -666,7 +666,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_5, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_floor_ops, }, }; @@ -689,7 +689,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -731,7 +731,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_3, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -752,7 +752,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -813,7 +813,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; -- 2.30.2
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sc8180x.c | 122 ++++++++++++++++----------------- 1 file changed, 61 insertions(+), 61 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index 90525ae1bb3a..c41b9f010585 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -277,7 +277,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -300,7 +300,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_ptp_clk_src", .parent_data = gcc_parents_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_6), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -326,7 +326,7 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_rgmii_clk_src", .parent_data = gcc_parents_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_6), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -350,7 +350,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parents_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -365,7 +365,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parents_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -380,7 +380,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parents_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -395,7 +395,7 @@ static struct clk_rcg2 gcc_gp4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp4_clk_src", .parent_data = gcc_parents_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -410,7 +410,7 @@ static struct clk_rcg2 gcc_gp5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp5_clk_src", .parent_data = gcc_parents_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -436,7 +436,7 @@ static struct clk_rcg2 gcc_npu_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_npu_axi_clk_src", .parent_data = gcc_parents_3, - .num_parents = 7, + .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -457,7 +457,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -472,7 +472,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -487,7 +487,7 @@ static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -502,7 +502,7 @@ static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_3_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -523,7 +523,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_refgen_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -545,7 +545,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -568,7 +568,7 @@ static struct clk_rcg2 gcc_qspi_1_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qspi_1_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -583,7 +583,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qspi_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -619,7 +619,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -634,7 +634,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -649,7 +649,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -664,7 +664,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -679,7 +679,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -694,7 +694,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -724,7 +724,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -739,7 +739,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -754,7 +754,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -769,7 +769,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -784,7 +784,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -799,7 +799,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -814,7 +814,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -829,7 +829,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -844,7 +844,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -859,7 +859,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -874,7 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -889,7 +889,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -904,7 +904,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -930,7 +930,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parents_7, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_7), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -955,7 +955,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parents_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -975,7 +975,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk_src", .parent_data = gcc_parents_8, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_8), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -998,7 +998,7 @@ static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_2_axi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1013,7 +1013,7 @@ static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_2_ice_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1033,7 +1033,7 @@ static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_2_phy_aux_clk_src", .parent_data = gcc_parents_4, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_parents_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1048,7 +1048,7 @@ static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_2_unipro_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1072,7 +1072,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1094,7 +1094,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1109,7 +1109,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk_src", .parent_data = gcc_parents_4, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_parents_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1131,7 +1131,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1155,7 +1155,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1170,7 +1170,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1185,7 +1185,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parents_4, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_parents_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1200,7 +1200,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1224,7 +1224,7 @@ static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mp_master_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1247,7 +1247,7 @@ static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mp_mock_utmi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1262,7 +1262,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1277,7 +1277,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1292,7 +1292,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1307,7 +1307,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_mock_utmi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1322,7 +1322,7 @@ static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_mp_phy_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1337,7 +1337,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1352,7 +1352,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, -- 2.30.2
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8150.c | 96 +++++++++++++++++------------------ 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index e642fe785c12..245794485719 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -241,7 +241,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -264,7 +264,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_ptp_clk_src", .parent_data = gcc_parents_5, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -290,7 +290,7 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_rgmii_clk_src", .parent_data = gcc_parents_5, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -314,7 +314,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parents_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -329,7 +329,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parents_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -344,7 +344,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parents_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -365,7 +365,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -380,7 +380,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_refgen_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -423,7 +423,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -446,7 +446,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qspi_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -480,7 +480,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -510,7 +510,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -525,7 +525,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -540,7 +540,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -555,7 +555,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -570,7 +570,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -585,7 +585,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -615,7 +615,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -630,7 +630,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -645,7 +645,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -660,7 +660,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -675,7 +675,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -690,7 +690,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s0_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -705,7 +705,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s1_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -720,7 +720,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s2_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -735,7 +735,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s3_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -750,7 +750,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s4_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -765,7 +765,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_qupv3_wrap2_s5_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -791,7 +791,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parents_6, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_6), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -816,7 +816,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parents_3, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -836,7 +836,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk_src", .parent_data = gcc_parents_7, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parents_7), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -860,7 +860,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -883,7 +883,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk_src", .parent_data = gcc_parents_4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -949,7 +949,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -964,7 +964,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -979,7 +979,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parents_4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parents_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -994,7 +994,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1018,7 +1018,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1040,7 +1040,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1055,7 +1055,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1070,7 +1070,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_mock_utmi_clk_src", .parent_data = gcc_parents_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parents_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1085,7 +1085,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1100,7 +1100,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk_src", .parent_data = gcc_parents_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parents_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, -- 2.30.2
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8250.c | 92 +++++++++++++++++------------------ 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index 5ceadb35289f..9755ef4888c1 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -199,7 +199,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_cpuss_ahb_clk_src", .parent_data = gcc_parent_data_0_ao, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -223,7 +223,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -237,7 +237,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -251,7 +251,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -271,7 +271,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -285,7 +285,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -299,7 +299,7 @@ static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -319,7 +319,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_refgen_clk_src", .parent_data = gcc_parent_data_0_ao, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), .ops = &clk_rcg2_ops, }, }; @@ -340,7 +340,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -368,7 +368,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -384,7 +384,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -416,7 +416,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -432,7 +432,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -448,7 +448,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -464,7 +464,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -480,7 +480,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -496,7 +496,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -512,7 +512,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -544,7 +544,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -560,7 +560,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -576,7 +576,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -592,7 +592,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -608,7 +608,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { .name = "gcc_qupv3_wrap2_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -624,7 +624,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { .name = "gcc_qupv3_wrap2_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -640,7 +640,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { .name = "gcc_qupv3_wrap2_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { .name = "gcc_qupv3_wrap2_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -672,7 +672,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { .name = "gcc_qupv3_wrap2_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -688,7 +688,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { .name = "gcc_qupv3_wrap2_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }; @@ -720,7 +720,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_4, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_floor_ops, }, }; @@ -743,7 +743,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_floor_ops, }, }; @@ -762,7 +762,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk_src", .parent_data = gcc_parent_data_5, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_rcg2_ops, }, }; @@ -784,7 +784,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -806,7 +806,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -825,7 +825,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk_src", .parent_data = gcc_parent_data_3, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -846,7 +846,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -869,7 +869,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -883,7 +883,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -897,7 +897,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_3, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -911,7 +911,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -934,7 +934,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -948,7 +948,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -962,7 +962,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -1004,7 +1004,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; -- 2.30.2
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gcc-sm8350.c | 108 +++++++++++++++++----------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 10364398407d..6d0a9e2d5104 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -297,7 +297,7 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_4, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -312,7 +312,7 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_5, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -327,7 +327,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_rx_symbol_0_clk_src", .parent_data = gcc_parent_data_7, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -342,7 +342,7 @@ static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_rx_symbol_1_clk_src", .parent_data = gcc_parent_data_8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -357,7 +357,7 @@ static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_tx_symbol_0_clk_src", .parent_data = gcc_parent_data_9, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -372,7 +372,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_0_clk_src", .parent_data = gcc_parent_data_10, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -387,7 +387,7 @@ static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_rx_symbol_1_clk_src", .parent_data = gcc_parent_data_11, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -402,7 +402,7 @@ static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_tx_symbol_0_clk_src", .parent_data = gcc_parent_data_12, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -417,7 +417,7 @@ static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_pipe_clk_src", .parent_data = gcc_parent_data_13, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_13), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -432,7 +432,7 @@ static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = { .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_pipe_clk_src", .parent_data = gcc_parent_data_14, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_14), .ops = &clk_regmap_mux_closest_ops, }, }, @@ -454,7 +454,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -469,7 +469,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -484,7 +484,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk_src", .parent_data = gcc_parent_data_1, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -505,7 +505,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -526,7 +526,7 @@ static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -541,7 +541,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -556,7 +556,7 @@ static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_phy_rchng_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -576,7 +576,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -600,7 +600,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -617,7 +617,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -634,7 +634,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -651,7 +651,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -668,7 +668,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -702,7 +702,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -719,7 +719,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -755,7 +755,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -772,7 +772,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -789,7 +789,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -806,7 +806,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -823,7 +823,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -840,7 +840,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -857,7 +857,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { .name = "gcc_qupv3_wrap2_s0_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -874,7 +874,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { .name = "gcc_qupv3_wrap2_s1_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -891,7 +891,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { .name = "gcc_qupv3_wrap2_s2_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { .name = "gcc_qupv3_wrap2_s3_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { .name = "gcc_qupv3_wrap2_s4_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -942,7 +942,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { .name = "gcc_qupv3_wrap2_s5_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }; @@ -974,7 +974,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_6, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -996,7 +996,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_floor_ops, }, @@ -1019,7 +1019,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_axi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1041,7 +1041,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1061,7 +1061,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_phy_aux_clk_src", .parent_data = gcc_parent_data_3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1076,7 +1076,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_card_unipro_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1091,7 +1091,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_axi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1106,7 +1106,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_ice_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1121,7 +1121,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_phy_aux_clk_src", .parent_data = gcc_parent_data_3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1136,7 +1136,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_ufs_phy_unipro_core_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1174,7 +1174,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1189,7 +1189,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_master_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1204,7 +1204,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sec_mock_utmi_clk_src", .parent_data = gcc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -1234,7 +1234,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_usb3_sec_phy_aux_clk_src", .parent_data = gcc_parent_data_2, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, -- 2.30.2
On Tue, 6 Apr 2021 at 01:47, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote: > > Cleanup several Qualcomm clock drivers by removing unused entries from > parents map, removing test clock, etc. > > Changes since v3: > - Use ARRAY_SIZE() for num_parents and parent_hws instead of > parent_data where applicable as suggested by Marijn Suijten > These changes are applied both as a part of 'convert ot parent data' > patches and as separate changes to respective clock drivers (which > already used parent_data). > > Changes since v2: > - Comment out unsupported video_pll0_out_odd/_even clocks instead of > removing them or just using .name for them. The clocks are > unsupported, but mux values are provided for the future reference. > > Changes since v1: > - Remove unused entries from gpucc-sc7180, gpucc-sdm845, videocc-sc7180 > and videocc-sm8150 drivers > - Restore video_pll0_out_odd/_even entries in videocc-sdm845 driver as > requested by Taniya Das. For your convenience: The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15: Linux 5.12-rc2 (2021-03-05 17:33:41 -0800) are available in the Git repository at: https://git.linaro.org/people/dmitry.baryshkov/kernel.git qcom-clk-cleanup for you to fetch changes up to 576546d30f7df4813b0bb5874486f08f82f28ec1: clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents (2021-04-05 23:48:03 +0300) ---------------------------------------------------------------- Dmitry Baryshkov (33): clk: qcom: dispcc-sc7180: drop unused enum entries clk: qcom: dispcc-sm8250: drop unused enum entries clk: qcom: gcc-sm8250: drop unused enum entries clk: qcom: gpucc-sc7180: drop unused enum entries clk: qcom: gpucc-sdm845: drop unused enum entries clk: qcom: gpucc-sm8150: drop unused enum entries clk: qcom: gpucc-sm8250: drop unused enum entries clk: qcom: videocc-sc7180: drop unused enum entries clk: qcom: videocc-sm8150: drop unused enum entries clk: qcom: videocc-sm8250: drop unused enum entries clk: qcom: dispcc-sdm845: convert to parent data clk: qcom: gpucc-sdm845: convert to parent data clk: qcom: videocc-sdm845: convert to parent data clk: qcom: gpucc-sdm845: get rid of the test clock clk: qcom: dispcc-sdm845: get rid of the test clock clk: qcom: videocc-sdm845: get rid of the test clock clk: qcom: dispcc-sc7180: use parent_hws where possible clk: qcom: dispcc-sm8250: use parent_hws where possible clk: qcom: gcc-sc7180: use parent_hws where possible clk: qcom: gcc-sc7280: use parent_hws where possible clk: qcom: gcc-sdx55: use parent_hws where possible clk: qcom: gcc-sm8150: use parent_hws where possible clk: qcom: gcc-sm8250: use parent_hws where possible clk: qcom: gcc-sm8350: use parent_hws where possible clk: qcom: gpucc-sm8150: use parent_hws where possible clk: qcom: gpucc-sm8250: use parent_hws where possible clk: qcom: videocc-sm8150: use parent_hws where possible clk: qcom: videocc-sm8250: use parent_hws where possible clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents drivers/clk/qcom/dispcc-sc7180.c | 70 ++++--- drivers/clk/qcom/dispcc-sdm845.c | 217 ++++++++++---------- drivers/clk/qcom/dispcc-sm8250.c | 124 ++++++----- drivers/clk/qcom/gcc-sc7180.c | 196 +++++++++--------- drivers/clk/qcom/gcc-sc7280.c | 248 +++++++++++----------- drivers/clk/qcom/gcc-sc8180x.c | 122 +++++------ drivers/clk/qcom/gcc-sdx55.c | 8 +- drivers/clk/qcom/gcc-sm8150.c | 100 ++++----- drivers/clk/qcom/gcc-sm8250.c | 345 ++++++++++++++++--------------- drivers/clk/qcom/gcc-sm8350.c | 418 +++++++++++++++++++------------------- drivers/clk/qcom/gpucc-sc7180.c | 3 - drivers/clk/qcom/gpucc-sdm845.c | 45 ++-- drivers/clk/qcom/gpucc-sm8150.c | 9 +- drivers/clk/qcom/gpucc-sm8250.c | 9 +- drivers/clk/qcom/videocc-sc7180.c | 4 - drivers/clk/qcom/videocc-sdm845.c | 55 +++-- drivers/clk/qcom/videocc-sm8150.c | 20 +- drivers/clk/qcom/videocc-sm8250.c | 30 ++- 18 files changed, 991 insertions(+), 1032 deletions(-) -- With best wishes Dmitry
Quoting Dmitry Baryshkov (2021-04-05 15:47:10)
> Cleanup several Qualcomm clock drivers by removing unused entries from
> parents map, removing test clock, etc.
Checkpatch complains about block comments. I'll fix it up when applying.
Quoting Dmitry Baryshkov (2021-04-05 15:47:11)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:12)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:13)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:14)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:15)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:16)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:17)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:18)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Taniya Das <tdas@codeaurora.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:19)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:20)
> Drop unused enum entries from the list of parent enums.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:21)
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:22)
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:23)
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:24)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream. Remove it.
>
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:25)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream. Remove it.
>
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:26)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream. Remove it.
>
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:27)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:28)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:29)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:30)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:31)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:32)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:33)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:34)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:35)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:36)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:37)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:38)
> Switch to using parent_hws instead of parent_data when parents are
> defined in this driver and so accessible using clk_hw.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:39)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:40)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:41)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:42)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next
Quoting Dmitry Baryshkov (2021-04-05 15:47:43)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Applied to clk-next