From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0D45C433B4 for ; Thu, 8 Apr 2021 15:07:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 839FA6105A for ; Thu, 8 Apr 2021 15:07:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231953AbhDHPHf (ORCPT ); Thu, 8 Apr 2021 11:07:35 -0400 Received: from mail-ot1-f44.google.com ([209.85.210.44]:38666 "EHLO mail-ot1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231866AbhDHPHf (ORCPT ); Thu, 8 Apr 2021 11:07:35 -0400 Received: by mail-ot1-f44.google.com with SMTP id w21-20020a9d63950000b02901ce7b8c45b4so2596853otk.5; Thu, 08 Apr 2021 08:07:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=G3U2SbtiYaAheMlUlClApXmCYS1Yjxtn4KGjfZLQ0TU=; b=sr4DdE65ZBObtSUlTSbebwA43lPzSu+wMG6ku1rQOtK1b89oMQn8WghRPsZYMgUA90 q4eyI1oPG2sLVU31sY1aojaOhK8V3XWeuQXhQUh+WZ0FIE8e5ibOl7Ua+BTYrXabo5wq L5bdhDdrz6swf+W2RZncJO0Z5FFVAmaly2epH8mCOgUy/qhPnG+hIK1CevVMFSxsNDH8 DEBhZO77xW7RJc9XPK4rcCnofO5dzIY74CWLdwq0l0rsc1AF+c4zcIcqFWukM++kYIXA M9ICusQ++bUTi8GC1RyEWF3vcvNYMLvMK3jwVMrPY/HSf7UgGZQvIfTR/2mLxnhZqIT4 qHpQ== X-Gm-Message-State: AOAM531XXhpyRsWRUVM03Fcs+4FH5AHE2Lqv3KSMkHJiRO8QfpczCPj0 DzBe3kV9aMLBhknl2ImKNg== X-Google-Smtp-Source: ABdhPJzOI9cXLjKmxK5bZcjTJl8izeGCaCFA2UFBIO3kY2hsg5UWd4/Se3hmqNmzH2UGEo7L2ZT3yQ== X-Received: by 2002:a05:6830:908:: with SMTP id v8mr8287889ott.217.1617894443118; Thu, 08 Apr 2021 08:07:23 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id y11sm6431032ots.80.2021.04.08.08.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 08:07:22 -0700 (PDT) Received: (nullmailer pid 1488595 invoked by uid 1000); Thu, 08 Apr 2021 15:07:20 -0000 Date: Thu, 8 Apr 2021 10:07:20 -0500 From: Rob Herring To: Krishna Manikandan Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kalyan_t@codeaurora.org, tanmay@codeaurora.org, abhinavk@codeaurora.org, robdclark@gmail.com, swboyd@chromium.org, bjorn.andersson@linaro.org, vinod.koul@linaro.org, dianders@chromium.org, khsieh@codeaurora.org, sean@poorly.run, Chandan Uddaraju , Vara Reddy Subject: Re: [PATCH v15 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller Message-ID: <20210408150720.GA1486270@robh.at.kernel.org> References: <1617620770-26202-1-git-send-email-mkrishn@codeaurora.org> <1617620770-26202-4-git-send-email-mkrishn@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1617620770-26202-4-git-send-email-mkrishn@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Apr 05, 2021 at 04:36:10PM +0530, Krishna Manikandan wrote: > Add bindings for Snapdragon DisplayPort controller driver. > > Signed-off-by: Chandan Uddaraju > Signed-off-by: Vara Reddy > Signed-off-by: Tanmay Shah > Signed-off-by: Kuogee Hsieh > Signed-off-by: Krishna Manikandan > > Changes in V2: > -Provide details about sel-gpio > > Changes in V4: > -Provide details about max dp lanes > -Change the commit text > > Changes in V5: > -moved dp.txt to yaml file > > Changes in v6: > - Squash all AUX LUT properties into one pattern Property > - Make aux-cfg[0-9]-settings properties optional > - Remove PLL/PHY bindings from DP controller dts > - Add DP clocks description > - Remove _clk suffix from clock names > - Rename pixel clock to stream_pixel > - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..) > - Fix indentation > - Add Display Port as interface of DPU in DPU bindings > and add port mapping accordingly. > > Chages in v7: > - Add dp-controller.yaml file common between multiple SOC > - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml > - change compatible string and add SOC name to it. > - Remove Root clock generator for pixel clock > - Add assigned-clocks and assigned-clock-parents bindings > - Remove redundant properties, descriptions and blank lines > - Add DP port in DPU bindings > - Update depends-on tag in commit message and rebase change accordingly > > Changes in v8: > - Add MDSS AHB clock in bindings > > Changes in v9: > - Remove redundant reg-name property > - Change assigned-clocks and assigned-clocks-parents counts to 2 > - Use IRQ flags in example dts > > Changes in v10: > - Change title of this patch as it does not contain PLL bindings anymore > - Remove redundant properties > - Remove use of IRQ flag > - Fix ports property > > Changes in v11: > - add ports required of both #address-cells and #size-cells > - add required operating-points-v2 > - add required #sound-dai-cells > - add required power-domains > - update maintainer list > > Changes in v12: > - remove soc node from examples (Stephen Boyd) > - split dpu-sc7180.yaml changes to separate patch (Stephen Boyd) > > Changes in v13: > - add assigned-clocks > - add assigned-clock-parents > --- > .../bindings/display/msm/dp-controller.yaml | 162 +++++++++++++++++++++ > 1 file changed, 162 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > new file mode 100644 > index 0000000..3a02c6c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -0,0 +1,162 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MSM Display Port Controller > + > +maintainers: > + - Kuogee Hsieh > + > +description: | > + Device tree bindings for DisplayPort host controller for MSM targets > + that are compatible with VESA DisplayPort interface specification. > + > +properties: > + compatible: > + enum: > + - qcom,sc7180-dp > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: AHB clock to enable register access > + - description: Display Port AUX clock > + - description: Display Port Link clock > + - description: Link interface clock between DP and PHY > + - description: Display Port Pixel clock > + > + clock-names: > + items: > + - const: core_iface > + - const: core_aux > + - const: ctrl_link > + - const: ctrl_link_iface > + - const: stream_pixel > + > + assigned-clocks: > + items: > + - description: link clock source > + - description: pixel clock source > + > + assigned-clock-parents: > + items: > + - description: phy 0 parent > + - description: phy 1 parent > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: dp > + > + operating-points-v2: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + "#sound-dai-cells": > + const: 0 > + > + ports: > + type: object graph.yaml reference... > + description: | > + A ports node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. Please read what video-interfaces.txt says now. > + properties: > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + port@0: > + type: object > + description: Input endpoint of the controller > + > + port@1: > + type: object > + description: Output endpoint of the controller > + > + required: > + - "#address-cells" > + - "#size-cells" > + > + additionalProperties: false > + > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - phys > + - phy-names > + - "#sound-dai-cells" > + - power-domains > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + displayport-controller@ae90000 { > + compatible = "qcom,sc7180-dp"; > + reg = <0xae90000 0x1400>; > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; > + clock-names = "core_iface", "core_aux", > + "ctrl_link", > + "ctrl_link_iface", "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; > + > + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; > + > + phys = <&dp_phy>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + power-domains = <&rpmhpd SC7180_CX>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + endpoint { > + remote-endpoint = <&typec>; > + }; > + }; > + }; > + }; > +... > -- > 2.7.4 >