* [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS
@ 2021-04-18 12:29 Bartosz Dudziak
2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree
Cc: Bartosz Dudziak
Enable booting of Samsung Galaxy S III Neo mobile phone with MSM8226 SoC.
Implemented clocks are on top of MSM8974 GCC driver because there is really
little difference between them. UART serial communication is working.
Changes in v2:
- Removed alphabet sort includes in MSM8974 GCC driver
- Keep using qcom_cc_probe() function instead of qcom_cc_really_probe()
- Add only MSM8226 SoC related includes to qcom GCC clock bindings
- Changed DTS files license to BSD 3 Clause
- Made changes in qcom-msm8226.dtsi DTS file:
> Remove occurrences of clock-frequency property from timer nodes
> Removed model and compatible properties
> Renamed pin controller label to "tlmm"
> Moved compatible and reg properties first in the nodes
> Lowercase hex address values
> Fix make dtbs_check warning in memory node
Bartosz Dudziak (5):
dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings
clk: qcom: gcc: Add support for Global Clock controller found on
MSM8226
arm: dts: qcom: Add support for MSM8226 SoC
dt-bindings: arm: qcom: Document MSM8226 SoC binding
arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo
phone
.../devicetree/bindings/arm/qcom.yaml | 6 +
.../devicetree/bindings/clock/qcom,gcc.yaml | 5 +-
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 25 +++
arch/arm/boot/dts/qcom-msm8226.dtsi | 147 +++++++++++++++
drivers/clk/qcom/gcc-msm8974.c | 169 +++++++++++++++++-
6 files changed, 344 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts
create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak @ 2021-04-18 12:29 ` Bartosz Dudziak 2021-04-20 15:04 ` Rob Herring 2021-06-28 0:01 ` Stephen Boyd 2021-04-18 12:29 ` [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 Bartosz Dudziak ` (4 subsequent siblings) 5 siblings, 2 replies; 11+ messages in thread From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree Cc: Bartosz Dudziak Add compatible device strings and the include files for the MSM8226 GCC. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> --- Documentation/devicetree/bindings/clock/qcom,gcc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index ee0467fb5e..eddf10e6a4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -26,8 +26,8 @@ description: | - dt-bindings/reset/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8660.h - dt-bindings/reset/qcom,gcc-msm8660.h - - dt-bindings/clock/qcom,gcc-msm8974.h - - dt-bindings/reset/qcom,gcc-msm8974.h + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/clock/qcom,gcc-msm8994.h - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h @@ -41,6 +41,7 @@ properties: - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-ipq8064 + - qcom,gcc-msm8226 - qcom,gcc-msm8660 - qcom,gcc-msm8916 - qcom,gcc-msm8939 -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings 2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak @ 2021-04-20 15:04 ` Rob Herring 2021-06-28 0:01 ` Stephen Boyd 1 sibling, 0 replies; 11+ messages in thread From: Rob Herring @ 2021-04-20 15:04 UTC (permalink / raw) To: Bartosz Dudziak Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-msm, linux-kernel, devicetree On Sun, Apr 18, 2021 at 02:29:05PM +0200, Bartosz Dudziak wrote: > Add compatible device strings and the include files for the MSM8226 GCC. > > Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> > --- > Documentation/devicetree/bindings/clock/qcom,gcc.yaml | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings 2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak 2021-04-20 15:04 ` Rob Herring @ 2021-06-28 0:01 ` Stephen Boyd 1 sibling, 0 replies; 11+ messages in thread From: Stephen Boyd @ 2021-06-28 0:01 UTC (permalink / raw) To: Andy Gross, Bartosz Dudziak, Bjorn Andersson, Michael Turquette, Rob Herring, devicetree, linux-arm-msm, linux-clk, linux-kernel Cc: Bartosz Dudziak Quoting Bartosz Dudziak (2021-04-18 05:29:05) > Add compatible device strings and the include files for the MSM8226 GCC. > > Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak @ 2021-04-18 12:29 ` Bartosz Dudziak 2021-06-28 0:01 ` Stephen Boyd 2021-04-18 12:29 ` [PATCH v2 3/5] arm: dts: qcom: Add support for MSM8226 SoC Bartosz Dudziak ` (3 subsequent siblings) 5 siblings, 1 reply; 11+ messages in thread From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree Cc: Bartosz Dudziak Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> --- drivers/clk/qcom/gcc-msm8974.c | 169 +++++++++++++++++++++++++++++++-- 1 file changed, 162 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 740d3c44c0..bf305fa9e5 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -719,6 +719,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = { + F(50000000, P_GPLL0, 12, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_ce1_clk[] = { F(50000000, P_GPLL0, 12, 0, 0), F(75000000, P_GPLL0, 8, 0, 0), @@ -761,6 +767,11 @@ static struct clk_rcg2 ce2_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_gp_clk[] = { F(4800000, P_XO, 4, 0, 0), F(6000000, P_GPLL0, 10, 1, 10), @@ -1955,6 +1966,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", + .parent_names = (const char *[]){ + "system_noc_clk_src", + }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1993,6 +2008,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x0cc8, + .clkr = { + .enable_reg = 0x0cc8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_prng_ahb_clk = { .halt_reg = 0x0d04, .halt_check = BRANCH_HALT_VOTED, @@ -2430,6 +2459,121 @@ static struct gdsc usb_hs_hsic_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; +static struct clk_regmap *gcc_msm8226_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL0_VOTE] = &gpll0_vote, + [GPLL1] = &gpll1.clkr, + [GPLL1_VOTE] = &gpll1_vote, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, + [CE1_CLK_SRC] = &ce1_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, + [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, + [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, + [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, + [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, + [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, + [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, + [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, + [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, +}; + +static const struct qcom_reset_map gcc_msm8226_resets[] = { + [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, + [GCC_USB_HS_BCR] = { 0x0480 }, + [GCC_USB2A_PHY_BCR] = { 0x04a8 }, +}; + +static struct gdsc *gcc_msm8226_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, +}; + +static const struct regmap_config gcc_msm8226_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a80, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_msm8226_desc = { + .config = &gcc_msm8226_regmap_config, + .clks = gcc_msm8226_clocks, + .num_clks = ARRAY_SIZE(gcc_msm8226_clocks), + .resets = gcc_msm8226_resets, + .num_resets = ARRAY_SIZE(gcc_msm8226_resets), + .gdscs = gcc_msm8226_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs), +}; + static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -2682,13 +2826,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { }; static const struct of_device_id gcc_msm8974_match_table[] = { - { .compatible = "qcom,gcc-msm8974" }, - { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, - { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, + { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc }, + { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc }, { } }; MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); +static void msm8226_clock_override(void) +{ + ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226; + gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; +} + static void msm8974_pro_clock_override(void) { sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; @@ -2708,16 +2861,18 @@ static int gcc_msm8974_probe(struct platform_device *pdev) { int ret; struct device *dev = &pdev->dev; - bool pro; const struct of_device_id *id; id = of_match_device(gcc_msm8974_match_table, dev); if (!id) return -ENODEV; - pro = !!(id->data); - if (pro) - msm8974_pro_clock_override(); + if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) { + if (id->data == &gcc_msm8226_desc) + msm8226_clock_override(); + else + msm8974_pro_clock_override(); + } ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); if (ret) -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 2021-04-18 12:29 ` [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 Bartosz Dudziak @ 2021-06-28 0:01 ` Stephen Boyd 0 siblings, 0 replies; 11+ messages in thread From: Stephen Boyd @ 2021-06-28 0:01 UTC (permalink / raw) To: Andy Gross, Bartosz Dudziak, Bjorn Andersson, Michael Turquette, Rob Herring, devicetree, linux-arm-msm, linux-clk, linux-kernel Cc: Bartosz Dudziak Quoting Bartosz Dudziak (2021-04-18 05:29:06) > Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies > which are different in this older chip. Register all the clocks to the > framework for the clients to be able to request for them. > > Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/5] arm: dts: qcom: Add support for MSM8226 SoC 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 Bartosz Dudziak @ 2021-04-18 12:29 ` Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding Bartosz Dudziak ` (2 subsequent siblings) 5 siblings, 0 replies; 11+ messages in thread From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree Cc: Bartosz Dudziak Implement basic device tree support for MSM8226 SoC which belongs to the Snapdragon 400 family. For now, this file adds the basic nodes like gcc, pinctrl and other required configuration for booting up to the serial console. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> --- arch/arm/boot/dts/qcom-msm8226.dtsi | 147 ++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi new file mode 100644 index 0000000000..2de69d5687 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-msm8974.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8226"; + reg = <0xfc400000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + }; + + blsp1_uart3: serial@f991f000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991f000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + timer@f9020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@f9021000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 2 + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 + (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak ` (2 preceding siblings ...) 2021-04-18 12:29 ` [PATCH v2 3/5] arm: dts: qcom: Add support for MSM8226 SoC Bartosz Dudziak @ 2021-04-18 12:29 ` Bartosz Dudziak 2021-04-20 15:04 ` Rob Herring 2021-04-18 12:29 ` [PATCH v2 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone Bartosz Dudziak 2021-11-12 22:23 ` [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Pavel Machek 5 siblings, 1 reply; 11+ messages in thread From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree Cc: Bartosz Dudziak Document the MSM8226 SoC device-tree binding. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 11ec349d56..73902ce46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -31,6 +31,7 @@ description: | ipq6018 ipq8074 mdm9615 + msm8226 msm8916 msm8974 msm8992 @@ -111,6 +112,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - samsung,s3ve3g + - const: qcom,msm8226 + - items: - enum: - qcom,msm8960-cdp -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding 2021-04-18 12:29 ` [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding Bartosz Dudziak @ 2021-04-20 15:04 ` Rob Herring 0 siblings, 0 replies; 11+ messages in thread From: Rob Herring @ 2021-04-20 15:04 UTC (permalink / raw) To: Bartosz Dudziak Cc: Rob Herring, Andy Gross, linux-kernel, Michael Turquette, Stephen Boyd, linux-arm-msm, devicetree, Bjorn Andersson, linux-clk On Sun, 18 Apr 2021 14:29:08 +0200, Bartosz Dudziak wrote: > Document the MSM8226 SoC device-tree binding. > > Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> > --- > Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak ` (3 preceding siblings ...) 2021-04-18 12:29 ` [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding Bartosz Dudziak @ 2021-04-18 12:29 ` Bartosz Dudziak 2021-11-12 22:23 ` [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Pavel Machek 5 siblings, 0 replies; 11+ messages in thread From: Bartosz Dudziak @ 2021-04-18 12:29 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree Cc: Bartosz Dudziak Add DTS support for the Samsung Galaxy S III Neo (codenamed s3ve3g) phone. Initial version have just a working serial console. Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e5d4ab4e7..080ff37fdb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -920,6 +920,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts new file mode 100644 index 0000000000..d159188c8b --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "qcom-msm8226.dtsi" + +/ { + model = "Samsung Galaxy S III Neo"; + compatible = "samsung,s3ve3g", "qcom,msm8226"; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak ` (4 preceding siblings ...) 2021-04-18 12:29 ` [PATCH v2 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone Bartosz Dudziak @ 2021-11-12 22:23 ` Pavel Machek 5 siblings, 0 replies; 11+ messages in thread From: Pavel Machek @ 2021-11-12 22:23 UTC (permalink / raw) To: Bartosz Dudziak Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring, linux-clk, linux-arm-msm, linux-kernel, devicetree [-- Attachment #1: Type: text/plain, Size: 441 bytes --] Hi! > Enable booting of Samsung Galaxy S III Neo mobile phone with MSM8226 SoC. > Implemented clocks are on top of MSM8974 GCC driver because there is really > little difference between them. UART serial communication is > working. Thanks for support for a phone. You may want to cc phone-devel@vger.kernel.org in future with phone-related patches. Best regards, Pavel -- http://www.livejournal.com/~pavelmachek [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 181 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-11-12 22:23 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-18 12:29 [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Bartosz Dudziak 2021-04-20 15:04 ` Rob Herring 2021-06-28 0:01 ` Stephen Boyd 2021-04-18 12:29 ` [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 Bartosz Dudziak 2021-06-28 0:01 ` Stephen Boyd 2021-04-18 12:29 ` [PATCH v2 3/5] arm: dts: qcom: Add support for MSM8226 SoC Bartosz Dudziak 2021-04-18 12:29 ` [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding Bartosz Dudziak 2021-04-20 15:04 ` Rob Herring 2021-04-18 12:29 ` [PATCH v2 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone Bartosz Dudziak 2021-11-12 22:23 ` [PATCH v2 0/5] Samsung Galaxy S III Neo Initial DTS Pavel Machek
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