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From: kernel test robot <lkp@intel.com>
To: Thara Gopinath <thara.gopinath@linaro.org>,
	herbert@gondor.apana.org.au, davem@davemloft.net,
	bjorn.andersson@linaro.org
Cc: kbuild-all@lists.01.org, clang-built-linux@googlegroups.com,
	ebiggers@google.com, ardb@kernel.org, sivaprak@codeaurora.org,
	linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org
Subject: Re: [Patch v3 6/7] crypto: qce: common: Add support for AEAD algorithms
Date: Thu, 22 Apr 2021 04:15:46 +0800
Message-ID: <202104220438.rrPLxer6-lkp@intel.com> (raw)
In-Reply-To: <20210420033602.1729947-7-thara.gopinath@linaro.org>


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Hi Thara,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on cryptodev/master]
[also build test WARNING on next-20210421]
[cannot apply to crypto/master v5.12-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Thara-Gopinath/Add-support-for-AEAD-algorithms-in-Qualcomm-Crypto-Engine-driver/20210420-113944
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: x86_64-randconfig-a013-20210421 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project d87b9b81ccb95217181ce75515c6c68bbb408ca4)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://github.com/0day-ci/linux/commit/b152c1b17bb6ad7923f0f3f8bc5ef81fb4cd054a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Thara-Gopinath/Add-support-for-AEAD-algorithms-in-Qualcomm-Crypto-Engine-driver/20210420-113944
        git checkout b152c1b17bb6ad7923f0f3f8bc5ef81fb4cd054a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/crypto/qce/common.c:478:14: warning: variable 'auth_ivsize' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
                   } else if (IS_SHA256_HMAC(rctx->flags)) {
                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/crypto/qce/common.h:68:32: note: expanded from macro 'IS_SHA256_HMAC'
   #define IS_SHA256_HMAC(flags)           (flags & QCE_HASH_SHA256_HMAC)
                                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/crypto/qce/common.c:482:18: note: uninitialized use occurs here
                   authiv_words = auth_ivsize / sizeof(u32);
                                  ^~~~~~~~~~~
   drivers/crypto/qce/common.c:478:10: note: remove the 'if' if its condition is always true
                   } else if (IS_SHA256_HMAC(rctx->flags)) {
                          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/crypto/qce/common.c:434:26: note: initialize the variable 'auth_ivsize' to silence this warning
           unsigned int auth_ivsize;
                                   ^
                                    = 0
   1 warning generated.


vim +478 drivers/crypto/qce/common.c

   418	
   419	static int qce_setup_regs_aead(struct crypto_async_request *async_req)
   420	{
   421		struct aead_request *req = aead_request_cast(async_req);
   422		struct qce_aead_reqctx *rctx = aead_request_ctx(req);
   423		struct qce_aead_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
   424		struct qce_alg_template *tmpl = to_aead_tmpl(crypto_aead_reqtfm(req));
   425		struct qce_device *qce = tmpl->qce;
   426		u32 enckey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
   427		u32 enciv[QCE_MAX_IV_SIZE / sizeof(u32)] = {0};
   428		u32 authkey[QCE_SHA_HMAC_KEY_SIZE / sizeof(u32)] = {0};
   429		u32 authiv[SHA256_DIGEST_SIZE / sizeof(u32)] = {0};
   430		u32 authnonce[QCE_MAX_NONCE / sizeof(u32)] = {0};
   431		unsigned int enc_keylen = ctx->enc_keylen;
   432		unsigned int auth_keylen = ctx->auth_keylen;
   433		unsigned int enc_ivsize = rctx->ivsize;
   434		unsigned int auth_ivsize;
   435		unsigned int enckey_words, enciv_words;
   436		unsigned int authkey_words, authiv_words, authnonce_words;
   437		unsigned long flags = rctx->flags;
   438		u32 encr_cfg, auth_cfg, config, totallen;
   439		u32 iv_last_word;
   440	
   441		qce_setup_config(qce);
   442	
   443		/* Write encryption key */
   444		enckey_words = qce_be32_to_cpu_array(enckey, ctx->enc_key, enc_keylen);
   445		qce_write_array(qce, REG_ENCR_KEY0, enckey, enckey_words);
   446	
   447		/* Write encryption iv */
   448		enciv_words = qce_be32_to_cpu_array(enciv, rctx->iv, enc_ivsize);
   449		qce_write_array(qce, REG_CNTR0_IV0, enciv, enciv_words);
   450	
   451		if (IS_CCM(rctx->flags)) {
   452			iv_last_word = enciv[enciv_words - 1];
   453			qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1);
   454			qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words);
   455			qce_write(qce, REG_CNTR_MASK, ~0);
   456			qce_write(qce, REG_CNTR_MASK0, ~0);
   457			qce_write(qce, REG_CNTR_MASK1, ~0);
   458			qce_write(qce, REG_CNTR_MASK2, ~0);
   459		}
   460	
   461		/* Clear authentication IV and KEY registers of previous values */
   462		qce_clear_array(qce, REG_AUTH_IV0, 16);
   463		qce_clear_array(qce, REG_AUTH_KEY0, 16);
   464	
   465		/* Clear byte count */
   466		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
   467	
   468		/* Write authentication key */
   469		authkey_words = qce_be32_to_cpu_array(authkey, ctx->auth_key, auth_keylen);
   470		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)authkey, authkey_words);
   471	
   472		/* Write initial authentication IV only for HMAC algorithms */
   473		if (IS_SHA_HMAC(rctx->flags)) {
   474			/* Write default authentication iv */
   475			if (IS_SHA1_HMAC(rctx->flags)) {
   476				auth_ivsize = SHA1_DIGEST_SIZE;
   477				memcpy(authiv, std_iv_sha1, auth_ivsize);
 > 478			} else if (IS_SHA256_HMAC(rctx->flags)) {
   479				auth_ivsize = SHA256_DIGEST_SIZE;
   480				memcpy(authiv, std_iv_sha256, auth_ivsize);
   481			}
   482			authiv_words = auth_ivsize / sizeof(u32);
   483			qce_write_array(qce, REG_AUTH_IV0, (u32 *)authiv, authiv_words);
   484		} else if (IS_CCM(rctx->flags)) {
   485			/* Write nonce for CCM algorithms */
   486			authnonce_words = qce_be32_to_cpu_array(authnonce, rctx->ccm_nonce, QCE_MAX_NONCE);
   487			qce_write_array(qce, REG_AUTH_INFO_NONCE0, authnonce, authnonce_words);
   488		}
   489	
   490		/* Set up ENCR_SEG_CFG */
   491		encr_cfg = qce_encr_cfg(flags, enc_keylen);
   492		if (IS_ENCRYPT(flags))
   493			encr_cfg |= BIT(ENCODE_SHIFT);
   494		qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
   495	
   496		/* Set up AUTH_SEG_CFG */
   497		auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize);
   498		auth_cfg |= BIT(AUTH_LAST_SHIFT);
   499		auth_cfg |= BIT(AUTH_FIRST_SHIFT);
   500		if (IS_ENCRYPT(flags)) {
   501			if (IS_CCM(rctx->flags))
   502				auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT;
   503			else
   504				auth_cfg |= AUTH_POS_AFTER << AUTH_POS_SHIFT;
   505		} else {
   506			if (IS_CCM(rctx->flags))
   507				auth_cfg |= AUTH_POS_AFTER << AUTH_POS_SHIFT;
   508			else
   509				auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT;
   510		}
   511		qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
   512	
   513		totallen = rctx->cryptlen + rctx->assoclen;
   514	
   515		/* Set the encryption size and start offset */
   516		if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags))
   517			qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize);
   518		else
   519			qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
   520		qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff);
   521	
   522		/* Set the authentication size and start offset */
   523		qce_write(qce, REG_AUTH_SEG_SIZE, totallen);
   524		qce_write(qce, REG_AUTH_SEG_START, 0);
   525	
   526		/* Write total length */
   527		if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags))
   528			qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize);
   529		else
   530			qce_write(qce, REG_SEG_SIZE, totallen);
   531	
   532		/* get little endianness */
   533		config = qce_config_reg(qce, 1);
   534		qce_write(qce, REG_CONFIG, config);
   535	
   536		/* Start the process */
   537		qce_crypto_go(qce, !IS_CCM(flags));
   538	
   539		return 0;
   540	}
   541	#endif
   542	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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  reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20  3:35 [Patch v3 0/7] Add support for AEAD algorithms in Qualcomm Crypto Engine driver Thara Gopinath
2021-04-20  3:35 ` [Patch v3 1/7] crypto: qce: common: Add MAC failed error checking Thara Gopinath
2021-04-20  3:35 ` [Patch v3 2/7] crypto: qce: common: Make result dump optional Thara Gopinath
2021-04-20  3:35 ` [Patch v3 3/7] crypto: qce: Add mode for rfc4309 Thara Gopinath
2021-04-20  3:35 ` [Patch v3 4/7] crypto: qce: Add support for AEAD algorithms Thara Gopinath
2021-04-20  3:36 ` [Patch v3 5/7] crypto: qce: common: Clean up qce_auth_cfg Thara Gopinath
2021-04-20  3:36 ` [Patch v3 6/7] crypto: qce: common: Add support for AEAD algorithms Thara Gopinath
2021-04-21 20:15   ` kernel test robot [this message]
2021-04-29  5:25   ` [kbuild] " Dan Carpenter
2021-04-20  3:36 ` [Patch v3 7/7] crypto: qce: aead: Schedule fallback algorithm Thara Gopinath

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