* [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250
@ 2021-05-13 17:52 Jonathan Marek
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Jonathan Marek @ 2021-05-13 17:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: robert.foss, andrey.konovalov, Andy Gross, Bjorn Andersson,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:COMMON CLK FRAMEWORK, open list, Michael Turquette,
Rob Herring, Stephen Boyd
Add support for the camera clock controller found on SM8250.
Jonathan Marek (3):
clk: qcom: clk-alpha-pll: add support for zonda pll
dt-bindings: clock: add QCOM SM8250 camera clock bindings
clk: qcom: Add camera clock controller driver for SM8250
.../bindings/clock/qcom,camcc-sm8250.yaml | 73 +
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8250.c | 2456 +++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.c | 245 ++
drivers/clk/qcom/clk-alpha-pll.h | 6 +
include/dt-bindings/clock/qcom,camcc-sm8250.h | 138 +
7 files changed, 2926 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
create mode 100644 drivers/clk/qcom/camcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,camcc-sm8250.h
--
2.26.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-13 17:52 [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
@ 2021-05-13 17:52 ` Jonathan Marek
2021-05-18 11:15 ` Robert Foss
` (2 more replies)
2021-05-13 17:52 ` [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings Jonathan Marek
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2 siblings, 3 replies; 14+ messages in thread
From: Jonathan Marek @ 2021-05-13 17:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: robert.foss, andrey.konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list:COMMON CLK FRAMEWORK,
open list
Ported over from the downstream driver. Will be used by SM8250 CAMCC.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/clk/qcom/clk-alpha-pll.c | 245 +++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 6 +
2 files changed, 251 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index c6eb99169ddc..7b332a8935f4 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x1c,
[PLL_OFF_STATUS] = 0x2c,
},
+ [CLK_ALPHA_PLL_TYPE_ZONDA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_USER_CTL] = 0x0c,
+ [PLL_OFF_CONFIG_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL_U] = 0x14,
+ [PLL_OFF_CONFIG_CTL_U1] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_TEST_CTL_U] = 0x20,
+ [PLL_OFF_TEST_CTL_U1] = 0x24,
+ [PLL_OFF_OPMODE] = 0x28,
+ [PLL_OFF_STATUS] = 0x38,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
+/* ZONDA PLL specific */
+#define ZONDA_PLL_OUT_MASK 0xf
+#define ZONDA_STAY_IN_CFA BIT(16)
+#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
+
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
#define wait_for_pll_enable_lock(pll) \
wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
+#define wait_for_zonda_pll_freq_lock(pll) \
+ wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
+
#define wait_for_pll_disable(pll) \
wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
@@ -1398,6 +1419,13 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
+const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
+ .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
+ .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+ .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
+};
+EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
+
/**
* clk_lucid_pll_configure - configure the lucid pll
*
@@ -1777,3 +1805,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
+
+void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+ const struct alpha_pll_config *config)
+{
+ if (config->l)
+ regmap_write(regmap, PLL_L_VAL(pll), config->l);
+
+ if (config->alpha)
+ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+
+ if (config->config_ctl_val)
+ regmap_write(regmap, PLL_CONFIG_CTL(pll),
+ config->config_ctl_val);
+
+ if (config->config_ctl_hi_val)
+ regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
+ config->config_ctl_hi_val);
+
+ if (config->config_ctl_hi1_val)
+ regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
+ config->config_ctl_hi1_val);
+
+ if (config->user_ctl_val)
+ regmap_write(regmap, PLL_USER_CTL(pll),
+ config->user_ctl_val);
+
+ if (config->user_ctl_hi_val)
+ regmap_write(regmap, PLL_USER_CTL_U(pll),
+ config->user_ctl_hi_val);
+
+ if (config->user_ctl_hi1_val)
+ regmap_write(regmap, PLL_USER_CTL_U1(pll),
+ config->user_ctl_hi1_val);
+
+ if (config->test_ctl_val)
+ regmap_write(regmap, PLL_TEST_CTL(pll),
+ config->test_ctl_val);
+
+ if (config->test_ctl_hi_val)
+ regmap_write(regmap, PLL_TEST_CTL_U(pll),
+ config->test_ctl_hi_val);
+
+ if (config->test_ctl_hi1_val)
+ regmap_write(regmap, PLL_TEST_CTL_U1(pll),
+ config->test_ctl_hi1_val);
+
+ regmap_update_bits(regmap, PLL_MODE(pll),
+ PLL_BYPASSNL, 0);
+
+ /* Disable PLL output */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+
+ /* Set operation mode to OFF */
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
+
+ /* PLL should be in OFF mode before continuing */
+ wmb();
+
+ /* Place the PLL in STANDBY mode */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+
+static int clk_zonda_pll_enable(struct clk_hw *hw)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ struct regmap *regmap = pll->clkr.regmap;
+ u32 val;
+ int ret;
+
+ ret = regmap_read(regmap, PLL_MODE(pll), &val);
+ if (ret)
+ return ret;
+
+ /* If in FSM mode, just vote for it */
+ if (val & PLL_VOTE_FSM_ENA) {
+ ret = clk_enable_regmap(hw);
+ if (ret)
+ return ret;
+ return wait_for_pll_enable_active(pll);
+ }
+
+ /* Get the PLL out of bypass mode */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
+
+ /*
+ * H/W requires a 1us delay between disabling the bypass and
+ * de-asserting the reset.
+ */
+ mb();
+ udelay(1);
+
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+
+ /* Set operation mode to RUN */
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
+
+ ret = regmap_read(regmap, PLL_TEST_CTL(pll), &val);
+ if (ret)
+ return ret;
+
+ /* If cfa mode then poll for freq lock */
+ if (val & ZONDA_STAY_IN_CFA)
+ ret = wait_for_zonda_pll_freq_lock(pll);
+ else
+ ret = wait_for_pll_enable_lock(pll);
+ if (ret)
+ return ret;
+
+ /* Enable the PLL outputs */
+ ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
+ ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
+ if (ret)
+ return ret;
+
+ /* Enable the global PLL outputs */
+ ret = regmap_update_bits(regmap, PLL_MODE(pll),
+ PLL_OUTCTRL, PLL_OUTCTRL);
+ if (ret)
+ return ret;
+
+ /* Ensure that the write above goes through before returning. */
+ mb();
+
+ return 0;
+}
+
+static void clk_zonda_pll_disable(struct clk_hw *hw)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ struct regmap *regmap = pll->clkr.regmap;
+ u32 val;
+ int ret;
+
+ ret = regmap_read(regmap, PLL_MODE(pll), &val);
+ if (ret)
+ return;
+
+ /* If in FSM mode, just unvote it */
+ if (val & PLL_VOTE_FSM_ENA) {
+ clk_disable_regmap(hw);
+ return;
+ }
+
+ /* Disable the global PLL output */
+ ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+
+ /* Disable the PLL outputs */
+ regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
+
+ /* Put the PLL in bypass and reset */
+ regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
+
+ /* Place the PLL mode in OFF state */
+ regmap_write(regmap, PLL_OPMODE(pll), 0x0);
+}
+
+static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ unsigned long rrate;
+ u32 test_ctl_val;
+ u32 l;
+ u64 a;
+ int ret;
+
+ rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_BITWIDTH);
+
+ ret = alpha_pll_check_rate_margin(hw, rrate, rate);
+ if (ret < 0)
+ return ret;
+
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+
+ /* Wait before polling for the frequency latch */
+ udelay(5);
+
+ /* Read stay in cfa mode */
+ ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
+ if (ret)
+ return ret;
+
+ /* If cfa mode then poll for freq lock */
+ if (test_ctl_val & ZONDA_STAY_IN_CFA)
+ ret = wait_for_zonda_pll_freq_lock(pll);
+ else
+ ret = wait_for_pll_enable_lock(pll);
+ if (ret)
+ return ret;
+
+ /* Wait for PLL output to stabilize */
+ udelay(100);
+ return 0;
+}
+
+static unsigned long
+clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l, frac;
+
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
+
+ return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
+}
+
+const struct clk_ops clk_alpha_pll_zonda_ops = {
+ .enable = clk_zonda_pll_enable,
+ .disable = clk_zonda_pll_disable,
+ .is_enabled = clk_trion_pll_is_enabled,
+ .recalc_rate = clk_zonda_pll_recalc_rate,
+ .round_rate = clk_alpha_pll_round_rate,
+ .set_rate = clk_zonda_pll_set_rate,
+};
+EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 6943e933be0f..4871af27cf76 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -16,6 +16,7 @@ enum {
CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_AGERA,
+ CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_MAX,
};
@@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
+extern const struct clk_ops clk_alpha_pll_zonda_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops;
+
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
#define clk_lucid_pll_configure(pll, regmap, config) \
clk_trion_pll_configure(pll, regmap, config)
+void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+ const struct alpha_pll_config *config);
#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings
2021-05-13 17:52 [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
@ 2021-05-13 17:52 ` Jonathan Marek
2021-05-14 13:06 ` Rob Herring
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2 siblings, 1 reply; 14+ messages in thread
From: Jonathan Marek @ 2021-05-13 17:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: robert.foss, andrey.konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, Rob Herring,
open list:COMMON CLK FRAMEWORK,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SM8250 SoC.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
.../bindings/clock/qcom,camcc-sm8250.yaml | 73 +++++++++
include/dt-bindings/clock/qcom,camcc-sm8250.h | 138 ++++++++++++++++++
2 files changed, 211 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
create mode 100644 include/dt-bindings/clock/qcom,camcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
new file mode 100644
index 000000000000..54bb57147505
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
+
+maintainers:
+ - Jonathan Marek <jonathan@marek.ca>
+
+description: |
+ Qualcomm camera clock control module which supports the clocks, resets and
+ power domains on SM8250.
+
+ See also dt-bindings/clock/qcom,camcc-sm8250.h
+
+properties:
+ compatible:
+ const: qcom,sm8250-camcc
+
+properties:
+ compatible:
+ enum:
+ -
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@ad00000 {
+ compatible = "qcom,sm8250-camcc";
+ reg = <0x0ad00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,camcc-sm8250.h b/include/dt-bindings/clock/qcom,camcc-sm8250.h
new file mode 100644
index 000000000000..383ead17608d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,camcc-sm8250.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_AREG_CLK 1
+#define CAM_CC_BPS_AXI_CLK 2
+#define CAM_CC_BPS_CLK 3
+#define CAM_CC_BPS_CLK_SRC 4
+#define CAM_CC_CAMNOC_AXI_CLK 5
+#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
+#define CAM_CC_CAMNOC_DCD_XO_CLK 7
+#define CAM_CC_CCI_0_CLK 8
+#define CAM_CC_CCI_0_CLK_SRC 9
+#define CAM_CC_CCI_1_CLK 10
+#define CAM_CC_CCI_1_CLK_SRC 11
+#define CAM_CC_CORE_AHB_CLK 12
+#define CAM_CC_CPAS_AHB_CLK 13
+#define CAM_CC_CPHY_RX_CLK_SRC 14
+#define CAM_CC_CSI0PHYTIMER_CLK 15
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16
+#define CAM_CC_CSI1PHYTIMER_CLK 17
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18
+#define CAM_CC_CSI2PHYTIMER_CLK 19
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20
+#define CAM_CC_CSI3PHYTIMER_CLK 21
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22
+#define CAM_CC_CSI4PHYTIMER_CLK 23
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 24
+#define CAM_CC_CSI5PHYTIMER_CLK 25
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 26
+#define CAM_CC_CSIPHY0_CLK 27
+#define CAM_CC_CSIPHY1_CLK 28
+#define CAM_CC_CSIPHY2_CLK 29
+#define CAM_CC_CSIPHY3_CLK 30
+#define CAM_CC_CSIPHY4_CLK 31
+#define CAM_CC_CSIPHY5_CLK 32
+#define CAM_CC_FAST_AHB_CLK_SRC 33
+#define CAM_CC_FD_CORE_CLK 34
+#define CAM_CC_FD_CORE_CLK_SRC 35
+#define CAM_CC_FD_CORE_UAR_CLK 36
+#define CAM_CC_GDSC_CLK 37
+#define CAM_CC_ICP_AHB_CLK 38
+#define CAM_CC_ICP_CLK 39
+#define CAM_CC_ICP_CLK_SRC 40
+#define CAM_CC_IFE_0_AHB_CLK 41
+#define CAM_CC_IFE_0_AREG_CLK 42
+#define CAM_CC_IFE_0_AXI_CLK 43
+#define CAM_CC_IFE_0_CLK 44
+#define CAM_CC_IFE_0_CLK_SRC 45
+#define CAM_CC_IFE_0_CPHY_RX_CLK 46
+#define CAM_CC_IFE_0_CSID_CLK 47
+#define CAM_CC_IFE_0_CSID_CLK_SRC 48
+#define CAM_CC_IFE_0_DSP_CLK 49
+#define CAM_CC_IFE_1_AHB_CLK 50
+#define CAM_CC_IFE_1_AREG_CLK 51
+#define CAM_CC_IFE_1_AXI_CLK 52
+#define CAM_CC_IFE_1_CLK 53
+#define CAM_CC_IFE_1_CLK_SRC 54
+#define CAM_CC_IFE_1_CPHY_RX_CLK 55
+#define CAM_CC_IFE_1_CSID_CLK 56
+#define CAM_CC_IFE_1_CSID_CLK_SRC 57
+#define CAM_CC_IFE_1_DSP_CLK 58
+#define CAM_CC_IFE_LITE_AHB_CLK 59
+#define CAM_CC_IFE_LITE_AXI_CLK 60
+#define CAM_CC_IFE_LITE_CLK 61
+#define CAM_CC_IFE_LITE_CLK_SRC 62
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 63
+#define CAM_CC_IFE_LITE_CSID_CLK 64
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 65
+#define CAM_CC_IPE_0_AHB_CLK 66
+#define CAM_CC_IPE_0_AREG_CLK 67
+#define CAM_CC_IPE_0_AXI_CLK 68
+#define CAM_CC_IPE_0_CLK 69
+#define CAM_CC_IPE_0_CLK_SRC 70
+#define CAM_CC_JPEG_CLK 71
+#define CAM_CC_JPEG_CLK_SRC 72
+#define CAM_CC_MCLK0_CLK 73
+#define CAM_CC_MCLK0_CLK_SRC 74
+#define CAM_CC_MCLK1_CLK 75
+#define CAM_CC_MCLK1_CLK_SRC 76
+#define CAM_CC_MCLK2_CLK 77
+#define CAM_CC_MCLK2_CLK_SRC 78
+#define CAM_CC_MCLK3_CLK 79
+#define CAM_CC_MCLK3_CLK_SRC 80
+#define CAM_CC_MCLK4_CLK 81
+#define CAM_CC_MCLK4_CLK_SRC 82
+#define CAM_CC_MCLK5_CLK 83
+#define CAM_CC_MCLK5_CLK_SRC 84
+#define CAM_CC_MCLK6_CLK 85
+#define CAM_CC_MCLK6_CLK_SRC 86
+#define CAM_CC_PLL0 87
+#define CAM_CC_PLL0_OUT_EVEN 88
+#define CAM_CC_PLL0_OUT_ODD 89
+#define CAM_CC_PLL1 90
+#define CAM_CC_PLL1_OUT_EVEN 91
+#define CAM_CC_PLL2 92
+#define CAM_CC_PLL2_OUT_MAIN 93
+#define CAM_CC_PLL3 94
+#define CAM_CC_PLL3_OUT_EVEN 95
+#define CAM_CC_PLL4 96
+#define CAM_CC_PLL4_OUT_EVEN 97
+#define CAM_CC_SBI_AHB_CLK 98
+#define CAM_CC_SBI_AXI_CLK 99
+#define CAM_CC_SBI_CLK 100
+#define CAM_CC_SBI_CPHY_RX_CLK 101
+#define CAM_CC_SBI_CSID_CLK 102
+#define CAM_CC_SBI_CSID_CLK_SRC 103
+#define CAM_CC_SBI_DIV_CLK_SRC 104
+#define CAM_CC_SBI_IFE_0_CLK 105
+#define CAM_CC_SBI_IFE_1_CLK 106
+#define CAM_CC_SLEEP_CLK 107
+#define CAM_CC_SLEEP_CLK_SRC 108
+#define CAM_CC_SLOW_AHB_CLK_SRC 109
+#define CAM_CC_XO_CLK_SRC 110
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_ICP_BCR 1
+#define CAM_CC_IFE_0_BCR 2
+#define CAM_CC_IFE_1_BCR 3
+#define CAM_CC_IPE_0_BCR 4
+#define CAM_CC_SBI_BCR 5
+
+/* CAM_CC GDSCRs */
+#define BPS_GDSC 0
+#define IPE_0_GDSC 1
+#define SBI_GDSC 2
+#define IFE_0_GDSC 3
+#define IFE_1_GDSC 4
+#define TITAN_TOP_GDSC 5
+
+#endif
--
2.26.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250
2021-05-13 17:52 [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
2021-05-13 17:52 ` [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings Jonathan Marek
@ 2021-05-13 17:52 ` Jonathan Marek
2021-05-18 11:39 ` Vinod Koul
2021-05-18 11:42 ` Robert Foss
2 siblings, 2 replies; 14+ messages in thread
From: Jonathan Marek @ 2021-05-13 17:52 UTC (permalink / raw)
To: linux-arm-msm
Cc: robert.foss, andrey.konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list,
open list:COMMON CLK FRAMEWORK
Add support for the camera clock controller found on SM8250.
Based on the downstream driver.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/camcc-sm8250.c | 2456 +++++++++++++++++++++++++++++++
3 files changed, 2464 insertions(+)
create mode 100644 drivers/clk/qcom/camcc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 45646b867cdb..4f48c71dd964 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -483,6 +483,13 @@ config SDX_GCC_55
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
+config SM_CAMCC_8250
+ tristate "SM8250 Camera Clock Controller"
+ select SM_GCC_8250
+ help
+ Support for the camera clock controller on SM8250 devices.
+ Say Y if you want to support camera devices and camera functionality.
+
config SM_DISPCC_8250
tristate "SM8150 and SM8250 Display Clock Controller"
depends on SM_GCC_8150 || SM_GCC_8250
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 464f0af360d8..87144813962f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -73,6 +73,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
+obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
new file mode 100644
index 000000000000..ea89f879d7e4
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sm8250.c
@@ -0,0 +1,2456 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,camcc-sm8250.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_CAM_CC_PLL0_OUT_EVEN,
+ P_CAM_CC_PLL0_OUT_MAIN,
+ P_CAM_CC_PLL0_OUT_ODD,
+ P_CAM_CC_PLL1_OUT_EVEN,
+ P_CAM_CC_PLL2_OUT_EARLY,
+ P_CAM_CC_PLL2_OUT_MAIN,
+ P_CAM_CC_PLL3_OUT_EVEN,
+ P_CAM_CC_PLL4_OUT_EVEN,
+ P_SLEEP_CLK,
+};
+
+static struct pll_vco lucid_vco[] = {
+ { 249600000, 2000000000, 0 },
+};
+
+static struct pll_vco zonda_vco[] = {
+ { 595200000, 3600000000, 0 },
+};
+
+static const struct alpha_pll_config cam_cc_pll0_config = {
+ .l = 0x3E,
+ .alpha = 0x8000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x00003100,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_cam_cc_pll0_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll0_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ops,
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
+ { 0x3, 3 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
+ .offset = 0x0,
+ .post_div_shift = 12,
+ .post_div_table = post_div_table_cam_cc_pll0_out_odd,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll0_out_odd",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll0.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll1_config = {
+ .l = 0x1F,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x00000100,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
+ .offset = 0x1000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_cam_cc_pll1_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll1_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll1.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll2_config = {
+ .l = 0x4B,
+ //.cal_l = 0x4B,
+ .alpha = 0x0,
+ .config_ctl_val = 0x08200920,
+ .config_ctl_hi_val = 0x05002015,
+ .config_ctl_hi1_val = 0x00000000,
+ .user_ctl_val = 0x00000100,
+ .user_ctl_hi_val = 0x00000000,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll2 = {
+ .offset = 0x2000,
+ .vco_table = zonda_vco,
+ .num_vco = ARRAY_SIZE(zonda_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll2",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_zonda_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
+ .offset = 0x2000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_cam_cc_pll2_out_main,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
+ .width = 2,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll2_out_main",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll2.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_zonda_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll3_config = {
+ .l = 0x24,
+ .alpha = 0x7555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x00000100,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll3 = {
+ .offset = 0x3000,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll3",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
+ .offset = 0x3000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_cam_cc_pll3_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll3_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll3.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ops,
+ },
+};
+
+static const struct alpha_pll_config cam_cc_pll4_config = {
+ .l = 0x24,
+ .alpha = 0x7555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00002261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x00000100,
+ .user_ctl_hi_val = 0x00000805,
+ .user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll cam_cc_pll4 = {
+ .offset = 0x4000,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll4",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
+ { 0x1, 2 },
+ { }
+};
+
+static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
+ .offset = 0x4000,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_cam_cc_pll4_out_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_pll4_out_even",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_pll4.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_alpha_pll_postdiv_lucid_ops,
+ },
+};
+
+static const struct parent_map cam_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL0_OUT_MAIN, 1 },
+ { P_CAM_CC_PLL0_OUT_EVEN, 2 },
+ { P_CAM_CC_PLL0_OUT_ODD, 3 },
+ { P_CAM_CC_PLL2_OUT_MAIN, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_0[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &cam_cc_pll0.clkr.hw },
+ { .hw = &cam_cc_pll0_out_even.clkr.hw },
+ { .hw = &cam_cc_pll0_out_odd.clkr.hw },
+ { .hw = &cam_cc_pll2_out_main.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL2_OUT_EARLY, 5 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_1[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &cam_cc_pll2.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL3_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_2[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &cam_cc_pll3_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL4_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_3[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &cam_cc_pll4_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_4[] = {
+ { P_BI_TCXO, 0 },
+ { P_CAM_CC_PLL1_OUT_EVEN, 4 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_4[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = &cam_cc_pll1_out_even.clkr.hw },
+};
+
+static const struct parent_map cam_cc_parent_map_5[] = {
+ { P_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_5[] = {
+ { .fw_name = "sleep_clk" },
+};
+
+static const struct parent_map cam_cc_parent_map_6[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo" },
+};
+
+static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
+ F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_bps_clk_src = {
+ .cmd_rcgr = 0x7010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_bps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_bps_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
+ .cmd_rcgr = 0xc0f8,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_camnoc_axi_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cci_0_clk_src = {
+ .cmd_rcgr = 0xc0bc,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cci_0_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_cci_1_clk_src = {
+ .cmd_rcgr = 0xc0d8,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cci_1_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
+ .cmd_rcgr = 0xa068,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cphy_rx_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
+ .cmd_rcgr = 0x6000,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi0phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
+ .cmd_rcgr = 0x6020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi1phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
+ .cmd_rcgr = 0x6040,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi2phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
+ .cmd_rcgr = 0x6060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi3phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
+ .cmd_rcgr = 0x6080,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi4phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
+ .cmd_rcgr = 0x60a0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi5phytimer_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
+ F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
+ F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
+ .cmd_rcgr = 0x703c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_fast_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_fd_core_clk_src = {
+ .cmd_rcgr = 0xc098,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_fd_core_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_icp_clk_src = {
+ .cmd_rcgr = 0xc074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_icp_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_0_clk_src = {
+ .cmd_rcgr = 0xa010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_2,
+ .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_clk_src",
+ .parent_data = cam_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div cam_cc_sbi_div_clk_src = {
+ .reg = 0x9010,
+ .shift = 0,
+ .width = 3,
+ .clkr.hw.init = &(struct clk_init_data) {
+ .name = "cam_cc_sbi_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
+ .cmd_rcgr = 0xa040,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_1_clk_src = {
+ .cmd_rcgr = 0xb010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_3,
+ .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_clk_src",
+ .parent_data = cam_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
+ .cmd_rcgr = 0xb040,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
+ F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
+ .cmd_rcgr = 0xc000,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
+ .cmd_rcgr = 0xc01c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
+ .cmd_rcgr = 0x8010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_4,
+ .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ipe_0_clk_src",
+ .parent_data = cam_cc_parent_data_4,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_jpeg_clk_src = {
+ .cmd_rcgr = 0xc048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_bps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_jpeg_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
+ F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_mclk0_clk_src = {
+ .cmd_rcgr = 0x5000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk0_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk1_clk_src = {
+ .cmd_rcgr = 0x501c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk1_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk2_clk_src = {
+ .cmd_rcgr = 0x5038,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk2_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk3_clk_src = {
+ .cmd_rcgr = 0x5054,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk3_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk4_clk_src = {
+ .cmd_rcgr = 0x5070,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk4_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk5_clk_src = {
+ .cmd_rcgr = 0x508c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk5_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_mclk6_clk_src = {
+ .cmd_rcgr = 0x50a8,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_1,
+ .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk6_clk_src",
+ .parent_data = cam_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 cam_cc_sbi_csid_clk_src = {
+ .cmd_rcgr = 0x901c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_csid_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
+ F(32768, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_sleep_clk_src = {
+ .cmd_rcgr = 0xc170,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_5,
+ .freq_tbl = ftbl_cam_cc_sleep_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sleep_clk_src",
+ .parent_data = cam_cc_parent_data_5,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
+ .cmd_rcgr = 0x7058,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_0,
+ .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_slow_ahb_clk_src",
+ .parent_data = cam_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 cam_cc_xo_clk_src = {
+ .cmd_rcgr = 0xc154,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = cam_cc_parent_map_6,
+ .freq_tbl = ftbl_cam_cc_xo_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "cam_cc_xo_clk_src",
+ .parent_data = cam_cc_parent_data_6,
+ .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch cam_cc_bps_ahb_clk = {
+ .halt_reg = 0x7070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7070,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_bps_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_areg_clk = {
+ .halt_reg = 0x7054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_bps_areg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fast_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_axi_clk = {
+ .halt_reg = 0x7038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_bps_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_bps_clk = {
+ .halt_reg = 0x7028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_bps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_bps_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_axi_clk = {
+ .halt_reg = 0xc114,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc114,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_camnoc_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
+ .halt_reg = 0xc11c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc11c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_camnoc_dcd_xo_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_xo_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_0_clk = {
+ .halt_reg = 0xc0d4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0d4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cci_0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cci_0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cci_1_clk = {
+ .halt_reg = 0xc0f0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0f0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cci_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cci_1_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_core_ahb_clk = {
+ .halt_reg = 0xc150,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0xc150,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_core_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_cpas_ahb_clk = {
+ .halt_reg = 0xc0f4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0f4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_cpas_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi0phytimer_clk = {
+ .halt_reg = 0x6018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi0phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi0phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi1phytimer_clk = {
+ .halt_reg = 0x6038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi1phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi1phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi2phytimer_clk = {
+ .halt_reg = 0x6058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi2phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi2phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi3phytimer_clk = {
+ .halt_reg = 0x6078,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6078,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi3phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi3phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi4phytimer_clk = {
+ .halt_reg = 0x6098,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6098,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi4phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi4phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csi5phytimer_clk = {
+ .halt_reg = 0x60b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x60b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csi5phytimer_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_csi5phytimer_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy0_clk = {
+ .halt_reg = 0x601c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy1_clk = {
+ .halt_reg = 0x603c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x603c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy2_clk = {
+ .halt_reg = 0x605c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy3_clk = {
+ .halt_reg = 0x607c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x607c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy3_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy4_clk = {
+ .halt_reg = 0x609c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x609c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy4_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_csiphy5_clk = {
+ .halt_reg = 0x60bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x60bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_csiphy5_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_fd_core_clk = {
+ .halt_reg = 0xc0b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_fd_core_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fd_core_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_fd_core_uar_clk = {
+ .halt_reg = 0xc0b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc0b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_fd_core_uar_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fd_core_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_gdsc_clk = {
+ .halt_reg = 0xc16c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc16c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_gdsc_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_xo_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_ahb_clk = {
+ .halt_reg = 0xc094,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_icp_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_icp_clk = {
+ .halt_reg = 0xc08c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc08c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_icp_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_icp_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_ahb_clk = {
+ .halt_reg = 0xa088,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa088,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_areg_clk = {
+ .halt_reg = 0xa030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_areg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fast_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_axi_clk = {
+ .halt_reg = 0xa084,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_clk = {
+ .halt_reg = 0xa028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
+ .halt_reg = 0xa080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_csid_clk = {
+ .halt_reg = 0xa058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_csid_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_0_csid_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_0_dsp_clk = {
+ .halt_reg = 0xa03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xa03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_0_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_ahb_clk = {
+ .halt_reg = 0xb068,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb068,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_areg_clk = {
+ .halt_reg = 0xb030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_areg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fast_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_axi_clk = {
+ .halt_reg = 0xb064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb064,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_clk = {
+ .halt_reg = 0xb028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_1_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
+ .halt_reg = 0xb060,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_csid_clk = {
+ .halt_reg = 0xb058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_csid_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_1_csid_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_1_dsp_clk = {
+ .halt_reg = 0xb03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_1_dsp_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_1_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_ahb_clk = {
+ .halt_reg = 0xc040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_axi_clk = {
+ .halt_reg = 0xc044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_clk = {
+ .halt_reg = 0xc018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_lite_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
+ .halt_reg = 0xc03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ife_lite_csid_clk = {
+ .halt_reg = 0xc034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ife_lite_csid_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_lite_csid_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_0_ahb_clk = {
+ .halt_reg = 0x8040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ipe_0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_0_areg_clk = {
+ .halt_reg = 0x803c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x803c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ipe_0_areg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_fast_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_0_axi_clk = {
+ .halt_reg = 0x8038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ipe_0_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_ipe_0_clk = {
+ .halt_reg = 0x8028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_ipe_0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ipe_0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_jpeg_clk = {
+ .halt_reg = 0xc060,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc060,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_jpeg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_jpeg_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk0_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk1_clk = {
+ .halt_reg = 0x5034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk1_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk2_clk = {
+ .halt_reg = 0x5050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5050,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk2_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk3_clk = {
+ .halt_reg = 0x506c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x506c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk3_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk3_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk4_clk = {
+ .halt_reg = 0x5088,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5088,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk4_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk4_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk5_clk = {
+ .halt_reg = 0x50a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk5_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk5_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_mclk6_clk = {
+ .halt_reg = 0x50c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_mclk6_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_mclk6_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_ahb_clk = {
+ .halt_reg = 0x9040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_slow_ahb_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_axi_clk = {
+ .halt_reg = 0x903c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x903c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_camnoc_axi_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_clk = {
+ .halt_reg = 0x9014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_sbi_div_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_cphy_rx_clk = {
+ .halt_reg = 0x9038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9038,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_cphy_rx_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_cphy_rx_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_csid_clk = {
+ .halt_reg = 0x9034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_csid_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_sbi_csid_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_ife_0_clk = {
+ .halt_reg = 0x9044,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_ife_0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_0_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sbi_ife_1_clk = {
+ .halt_reg = 0x9048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sbi_ife_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_ife_1_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch cam_cc_sleep_clk = {
+ .halt_reg = 0xc188,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xc188,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "cam_cc_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &cam_cc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc bps_gdsc = {
+ .gdscr = 0x7004,
+ .pd = {
+ .name = "bps_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ipe_0_gdsc = {
+ .gdscr = 0x8004,
+ .pd = {
+ .name = "ipe_0_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc sbi_gdsc = {
+ .gdscr = 0x9004,
+ .pd = {
+ .name = "sbi_gdsc",
+ },
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ife_0_gdsc = {
+ .gdscr = 0xa004,
+ .pd = {
+ .name = "ife_0_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc ife_1_gdsc = {
+ .gdscr = 0xb004,
+ .pd = {
+ .name = "ife_1_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc titan_top_gdsc = {
+ .gdscr = 0xc144,
+ .pd = {
+ .name = "titan_top_gdsc",
+ },
+ .flags = POLL_CFG_GDSCR,
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct clk_regmap *cam_cc_sm8250_clocks[] = {
+ [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
+ [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
+ [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
+ [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
+ [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
+ [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
+ [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
+ [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
+ [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
+ [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
+ [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
+ [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
+ [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
+ [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
+ [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
+ [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
+ [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
+ [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
+ [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
+ [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
+ [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
+ [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
+ [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
+ [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
+ [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
+ [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
+ [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
+ [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
+ [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
+ [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
+ [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
+ [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
+ [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
+ [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
+ [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
+ [CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr,
+ [CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr,
+ [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
+ [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
+ [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
+ [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
+ [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
+ [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
+ [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
+ [CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr,
+ [CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr,
+ [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
+ [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
+ [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
+ [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
+ [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
+ [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
+ [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
+ [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
+ [CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
+ [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
+ [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
+ [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
+ [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
+ [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
+ [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
+ [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
+ [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
+ [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
+ [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
+ [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
+ [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
+ [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
+ [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
+ [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
+ [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
+ [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
+ [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
+ [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
+ [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
+ [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
+ [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
+ [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
+ [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
+ [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
+ [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
+ [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
+ [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
+ [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
+ [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
+ [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
+ [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
+ [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
+ [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
+ [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
+ [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
+ [CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr,
+ [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
+ [CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,
+ [CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,
+ [CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,
+ [CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,
+ [CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,
+ [CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,
+ [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
+ [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
+ [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
+ [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
+};
+
+static struct gdsc *cam_cc_sm8250_gdscs[] = {
+ [BPS_GDSC] = &bps_gdsc,
+ [IPE_0_GDSC] = &ipe_0_gdsc,
+ [SBI_GDSC] = &sbi_gdsc,
+ [IFE_0_GDSC] = &ife_0_gdsc,
+ [IFE_1_GDSC] = &ife_1_gdsc,
+ [TITAN_TOP_GDSC] = &titan_top_gdsc,
+};
+
+static const struct qcom_reset_map cam_cc_sm8250_resets[] = {
+ [CAM_CC_BPS_BCR] = { 0x7000 },
+ [CAM_CC_ICP_BCR] = { 0xc070 },
+ [CAM_CC_IFE_0_BCR] = { 0xa000 },
+ [CAM_CC_IFE_1_BCR] = { 0xb000 },
+ [CAM_CC_IPE_0_BCR] = { 0x8000 },
+ [CAM_CC_SBI_BCR] = { 0x9000 },
+};
+
+static const struct regmap_config cam_cc_sm8250_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xe004,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc cam_cc_sm8250_desc = {
+ .config = &cam_cc_sm8250_regmap_config,
+ .clks = cam_cc_sm8250_clocks,
+ .num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks),
+ .resets = cam_cc_sm8250_resets,
+ .num_resets = ARRAY_SIZE(cam_cc_sm8250_resets),
+ .gdscs = cam_cc_sm8250_gdscs,
+ .num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs),
+};
+
+static const struct of_device_id cam_cc_sm8250_match_table[] = {
+ { .compatible = "qcom,sm8250-camcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table);
+
+static int cam_cc_sm8250_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
+ clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
+ clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
+ clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
+
+ return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);;
+}
+
+static struct platform_driver cam_cc_sm8250_driver = {
+ .probe = cam_cc_sm8250_probe,
+ .driver = {
+ .name = "cam_cc-sm8250",
+ .of_match_table = cam_cc_sm8250_match_table,
+ },
+};
+
+static int __init cam_cc_sm8250_init(void)
+{
+ return platform_driver_register(&cam_cc_sm8250_driver);
+}
+subsys_initcall(cam_cc_sm8250_init);
+
+static void __exit cam_cc_sm8250_exit(void)
+{
+ platform_driver_unregister(&cam_cc_sm8250_driver);
+}
+module_exit(cam_cc_sm8250_exit);
+
+MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
+MODULE_LICENSE("GPL v2");
--
2.26.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings
2021-05-13 17:52 ` [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings Jonathan Marek
@ 2021-05-14 13:06 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2021-05-14 13:06 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-kernel, Michael Turquette, linux-arm-msm, robert.foss,
devicetree, andrey.konovalov, Andy Gross, Stephen Boyd,
linux-clk, Bjorn Andersson, Rob Herring
On Thu, 13 May 2021 13:52:54 -0400, Jonathan Marek wrote:
> Add device tree bindings for camera clock controller for
> Qualcomm Technology Inc's SM8250 SoC.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> .../bindings/clock/qcom,camcc-sm8250.yaml | 73 +++++++++
> include/dt-bindings/clock/qcom,camcc-sm8250.h | 138 ++++++++++++++++++
> 2 files changed, 211 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
> create mode 100644 include/dt-bindings/clock/qcom,camcc-sm8250.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml:22:1: [error] duplication of key "properties" in mapping (key-duplicates)
dtschema/dtc warnings/errors:
make[1]: *** Deleting file 'Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.example.dts'
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 421, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 121, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 714, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 435, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 253, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 284, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 4, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 22, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
Traceback (most recent call last):
File "/usr/local/bin/dt-doc-validate", line 67, in <module>
ret = check_doc(f)
File "/usr/local/bin/dt-doc-validate", line 25, in check_doc
testtree = dtschema.load(filename, line_number=line_number)
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 625, in load
return yaml.load(f.read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 421, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 121, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 714, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 435, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 253, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 284, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 4, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 22, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
make[1]: *** Deleting file 'Documentation/devicetree/bindings/processed-schema-examples.json'
Traceback (most recent call last):
File "/usr/local/bin/dt-mk-schema", line 38, in <module>
schemas = dtschema.process_schemas(args.schemas, core_schema=(not args.useronly))
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 587, in process_schemas
sch = process_schema(os.path.abspath(filename))
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 561, in process_schema
schema = load_schema(filename)
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 126, in load_schema
return do_load(os.path.join(schema_basedir, schema))
File "/usr/local/lib/python3.8/dist-packages/dtschema/lib.py", line 112, in do_load
return yaml.load(tmp)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 421, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 121, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 714, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 435, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 253, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 284, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 4, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 22, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
make[1]: *** [Documentation/devicetree/bindings/Makefile:62: Documentation/devicetree/bindings/processed-schema-examples.json] Error 1
make: *** [Makefile:1416: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1478165
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
@ 2021-05-18 11:15 ` Robert Foss
2021-05-18 11:32 ` Vinod Koul
2021-05-19 4:52 ` Taniya Das
2 siblings, 0 replies; 14+ messages in thread
From: Robert Foss @ 2021-05-18 11:15 UTC (permalink / raw)
To: Jonathan Marek
Cc: MSM, Andrey Konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list:COMMON CLK FRAMEWORK,
open list
Hey Jonathan,
On Thu, 13 May 2021 at 19:53, Jonathan Marek <jonathan@marek.ca> wrote:
>
> Ported over from the downstream driver. Will be used by SM8250 CAMCC.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 245 +++++++++++++++++++++++++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> 2 files changed, 251 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index c6eb99169ddc..7b332a8935f4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_TEST_CTL_U] = 0x1c,
> [PLL_OFF_STATUS] = 0x2c,
> },
> + [CLK_ALPHA_PLL_TYPE_ZONDA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_USER_CTL] = 0x0c,
> + [PLL_OFF_CONFIG_CTL] = 0x10,
> + [PLL_OFF_CONFIG_CTL_U] = 0x14,
> + [PLL_OFF_CONFIG_CTL_U1] = 0x18,
> + [PLL_OFF_TEST_CTL] = 0x1c,
> + [PLL_OFF_TEST_CTL_U] = 0x20,
> + [PLL_OFF_TEST_CTL_U1] = 0x24,
> + [PLL_OFF_OPMODE] = 0x28,
> + [PLL_OFF_STATUS] = 0x38,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> @@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
> #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
>
> +/* ZONDA PLL specific */
> +#define ZONDA_PLL_OUT_MASK 0xf
> +#define ZONDA_STAY_IN_CFA BIT(16)
> +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
> +
> #define pll_alpha_width(p) \
> ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
> ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
> @@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
> #define wait_for_pll_enable_lock(pll) \
> wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
>
> +#define wait_for_zonda_pll_freq_lock(pll) \
> + wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
> +
> #define wait_for_pll_disable(pll) \
> wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
>
> @@ -1398,6 +1419,13 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
>
> +const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
> + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
> + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
> + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
> +
> /**
> * clk_lucid_pll_configure - configure the lucid pll
> *
> @@ -1777,3 +1805,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
> .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
> };
> EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
> +
> +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> + const struct alpha_pll_config *config)
> +{
> + if (config->l)
> + regmap_write(regmap, PLL_L_VAL(pll), config->l);
> +
> + if (config->alpha)
> + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> + if (config->config_ctl_val)
> + regmap_write(regmap, PLL_CONFIG_CTL(pll),
> + config->config_ctl_val);
> +
> + if (config->config_ctl_hi_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> + config->config_ctl_hi_val);
> +
> + if (config->config_ctl_hi1_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
> + config->config_ctl_hi1_val);
> +
> + if (config->user_ctl_val)
> + regmap_write(regmap, PLL_USER_CTL(pll),
> + config->user_ctl_val);
> +
> + if (config->user_ctl_hi_val)
> + regmap_write(regmap, PLL_USER_CTL_U(pll),
> + config->user_ctl_hi_val);
> +
> + if (config->user_ctl_hi1_val)
> + regmap_write(regmap, PLL_USER_CTL_U1(pll),
> + config->user_ctl_hi1_val);
> +
> + if (config->test_ctl_val)
> + regmap_write(regmap, PLL_TEST_CTL(pll),
> + config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val)
> + regmap_write(regmap, PLL_TEST_CTL_U(pll),
> + config->test_ctl_hi_val);
> +
> + if (config->test_ctl_hi1_val)
> + regmap_write(regmap, PLL_TEST_CTL_U1(pll),
> + config->test_ctl_hi1_val);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_BYPASSNL, 0);
> +
> + /* Disable PLL output */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Set operation mode to OFF */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +
> + /* PLL should be in OFF mode before continuing */
> + wmb();
> +
> + /* Place the PLL in STANDBY mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +}
> +
> +static int clk_zonda_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If in FSM mode, just vote for it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + ret = clk_enable_regmap(hw);
> + if (ret)
> + return ret;
> + return wait_for_pll_enable_active(pll);
> + }
> +
> + /* Get the PLL out of bypass mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
> +
> + /*
> + * H/W requires a 1us delay between disabling the bypass and
> + * de-asserting the reset.
> + */
> + mb();
> + udelay(1);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +
> + /* Set operation mode to RUN */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> +
> + ret = regmap_read(regmap, PLL_TEST_CTL(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Enable the PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> + ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
> + if (ret)
> + return ret;
> +
> + /* Enable the global PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_OUTCTRL, PLL_OUTCTRL);
> + if (ret)
> + return ret;
> +
> + /* Ensure that the write above goes through before returning. */
> + mb();
> +
> + return 0;
> +}
> +
> +static void clk_zonda_pll_disable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return;
> +
> + /* If in FSM mode, just unvote it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + clk_disable_regmap(hw);
> + return;
> + }
> +
> + /* Disable the global PLL output */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Disable the PLL outputs */
> + regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
> +
> + /* Put the PLL in bypass and reset */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
> +
> + /* Place the PLL mode in OFF state */
> + regmap_write(regmap, PLL_OPMODE(pll), 0x0);
> +}
> +
> +static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + unsigned long rrate;
> + u32 test_ctl_val;
> + u32 l;
> + u64 a;
> + int ret;
> +
> + rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_BITWIDTH);
> +
> + ret = alpha_pll_check_rate_margin(hw, rrate, rate);
> + if (ret < 0)
> + return ret;
> +
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +
> + /* Wait before polling for the frequency latch */
> + udelay(5);
> +
> + /* Read stay in cfa mode */
> + ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (test_ctl_val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Wait for PLL output to stabilize */
> + udelay(100);
> + return 0;
> +}
> +
> +static unsigned long
> +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l, frac;
> +
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> +
> + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
> +}
> +
> +const struct clk_ops clk_alpha_pll_zonda_ops = {
> + .enable = clk_zonda_pll_enable,
> + .disable = clk_zonda_pll_disable,
> + .is_enabled = clk_trion_pll_is_enabled,
> + .recalc_rate = clk_zonda_pll_recalc_rate,
> + .round_rate = clk_alpha_pll_round_rate,
> + .set_rate = clk_zonda_pll_set_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 6943e933be0f..4871af27cf76 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -16,6 +16,7 @@ enum {
> CLK_ALPHA_PLL_TYPE_TRION,
> CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
> CLK_ALPHA_PLL_TYPE_AGERA,
> + CLK_ALPHA_PLL_TYPE_ZONDA,
> CLK_ALPHA_PLL_TYPE_MAX,
> };
>
> @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
> extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
> extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
>
> +extern const struct clk_ops clk_alpha_pll_zonda_ops;
> +extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops;
> +
> void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> const struct alpha_pll_config *config);
> void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> @@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> #define clk_lucid_pll_configure(pll, regmap, config) \
> clk_trion_pll_configure(pll, regmap, config)
>
> +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> + const struct alpha_pll_config *config);
>
>
> #endif
I'm seeing some checkpatch --strict warnings, with those fixed this
patch looks good to me.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
2021-05-18 11:15 ` Robert Foss
@ 2021-05-18 11:32 ` Vinod Koul
2021-05-18 13:06 ` Jonathan Marek
2021-05-19 4:52 ` Taniya Das
2 siblings, 1 reply; 14+ messages in thread
From: Vinod Koul @ 2021-05-18 11:32 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, robert.foss, andrey.konovalov, Andy Gross,
Bjorn Andersson, Michael Turquette, Stephen Boyd,
open list:COMMON CLK FRAMEWORK, open list
On 13-05-21, 13:52, Jonathan Marek wrote:
> Ported over from the downstream driver. Will be used by SM8250 CAMCC.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 245 +++++++++++++++++++++++++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> 2 files changed, 251 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index c6eb99169ddc..7b332a8935f4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_TEST_CTL_U] = 0x1c,
> [PLL_OFF_STATUS] = 0x2c,
> },
> + [CLK_ALPHA_PLL_TYPE_ZONDA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_USER_CTL] = 0x0c,
> + [PLL_OFF_CONFIG_CTL] = 0x10,
> + [PLL_OFF_CONFIG_CTL_U] = 0x14,
> + [PLL_OFF_CONFIG_CTL_U1] = 0x18,
> + [PLL_OFF_TEST_CTL] = 0x1c,
> + [PLL_OFF_TEST_CTL_U] = 0x20,
> + [PLL_OFF_TEST_CTL_U1] = 0x24,
> + [PLL_OFF_OPMODE] = 0x28,
> + [PLL_OFF_STATUS] = 0x38,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> @@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
> #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
>
> +/* ZONDA PLL specific */
> +#define ZONDA_PLL_OUT_MASK 0xf
> +#define ZONDA_STAY_IN_CFA BIT(16)
> +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
This seems similar to ALPHA_PLL_ACK_LATCH..?
> +
> #define pll_alpha_width(p) \
> ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
> ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
> @@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
> #define wait_for_pll_enable_lock(pll) \
> wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
>
> +#define wait_for_zonda_pll_freq_lock(pll) \
> + wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
> +
> #define wait_for_pll_disable(pll) \
> wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
>
> @@ -1398,6 +1419,13 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
>
> +const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
> + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
> + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
> + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
Why add one more ops when we can reuse clk_alpha_pll_postdiv_fabia_ops
for this?
> +
> /**
> * clk_lucid_pll_configure - configure the lucid pll
> *
> @@ -1777,3 +1805,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
> .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
> };
> EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
> +
> +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> + const struct alpha_pll_config *config)
> +{
> + if (config->l)
> + regmap_write(regmap, PLL_L_VAL(pll), config->l);
> +
> + if (config->alpha)
> + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> + if (config->config_ctl_val)
> + regmap_write(regmap, PLL_CONFIG_CTL(pll),
> + config->config_ctl_val);
this and below can fit in a single line and look neater
> +
> + if (config->config_ctl_hi_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> + config->config_ctl_hi_val);
> +
> + if (config->config_ctl_hi1_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
> + config->config_ctl_hi1_val);
> +
> + if (config->user_ctl_val)
> + regmap_write(regmap, PLL_USER_CTL(pll),
> + config->user_ctl_val);
> +
> + if (config->user_ctl_hi_val)
> + regmap_write(regmap, PLL_USER_CTL_U(pll),
> + config->user_ctl_hi_val);
> +
> + if (config->user_ctl_hi1_val)
> + regmap_write(regmap, PLL_USER_CTL_U1(pll),
> + config->user_ctl_hi1_val);
> +
> + if (config->test_ctl_val)
> + regmap_write(regmap, PLL_TEST_CTL(pll),
> + config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val)
> + regmap_write(regmap, PLL_TEST_CTL_U(pll),
> + config->test_ctl_hi_val);
> +
> + if (config->test_ctl_hi1_val)
> + regmap_write(regmap, PLL_TEST_CTL_U1(pll),
> + config->test_ctl_hi1_val);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_BYPASSNL, 0);
> +
> + /* Disable PLL output */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Set operation mode to OFF */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +
> + /* PLL should be in OFF mode before continuing */
> + wmb();
Why a barrier?
> +
> + /* Place the PLL in STANDBY mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +}
> +
> +static int clk_zonda_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If in FSM mode, just vote for it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + ret = clk_enable_regmap(hw);
> + if (ret)
> + return ret;
> + return wait_for_pll_enable_active(pll);
> + }
> +
> + /* Get the PLL out of bypass mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
> +
> + /*
> + * H/W requires a 1us delay between disabling the bypass and
> + * de-asserting the reset.
> + */
> + mb();
> + udelay(1);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +
> + /* Set operation mode to RUN */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> +
> + ret = regmap_read(regmap, PLL_TEST_CTL(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Enable the PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> + ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
> + if (ret)
> + return ret;
> +
> + /* Enable the global PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_OUTCTRL, PLL_OUTCTRL);
> + if (ret)
> + return ret;
> +
> + /* Ensure that the write above goes through before returning. */
> + mb();
> +
> + return 0;
> +}
> +
> +static void clk_zonda_pll_disable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return;
> +
> + /* If in FSM mode, just unvote it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + clk_disable_regmap(hw);
> + return;
> + }
> +
> + /* Disable the global PLL output */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Disable the PLL outputs */
> + regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
> +
> + /* Put the PLL in bypass and reset */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
> +
> + /* Place the PLL mode in OFF state */
> + regmap_write(regmap, PLL_OPMODE(pll), 0x0);
> +}
> +
> +static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + unsigned long rrate;
> + u32 test_ctl_val;
> + u32 l;
> + u64 a;
> + int ret;
> +
> + rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_BITWIDTH);
> +
> + ret = alpha_pll_check_rate_margin(hw, rrate, rate);
> + if (ret < 0)
> + return ret;
> +
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +
> + /* Wait before polling for the frequency latch */
> + udelay(5);
> +
> + /* Read stay in cfa mode */
> + ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (test_ctl_val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Wait for PLL output to stabilize */
> + udelay(100);
> + return 0;
> +}
> +
> +static unsigned long
> +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l, frac;
> +
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> +
> + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
> +}
sounds like you could use clk_trion_pll_recalc_rate() instead
--
~Vinod
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
@ 2021-05-18 11:39 ` Vinod Koul
2021-05-18 11:42 ` Robert Foss
1 sibling, 0 replies; 14+ messages in thread
From: Vinod Koul @ 2021-05-18 11:39 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, robert.foss, andrey.konovalov, Andy Gross,
Bjorn Andersson, Michael Turquette, Stephen Boyd, open list,
open list:COMMON CLK FRAMEWORK
On 13-05-21, 13:52, Jonathan Marek wrote:
> +static const struct alpha_pll_config cam_cc_pll1_config = {
> + .l = 0x1F,
> + .alpha = 0x4000,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00002261,
> + .config_ctl_hi1_val = 0x329A699C,
lower hexes here and few other places as well
> +
> +static const struct alpha_pll_config cam_cc_pll2_config = {
> + .l = 0x4B,
> + //.cal_l = 0x4B,
debug artifact?
--
~Vinod
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-18 11:39 ` Vinod Koul
@ 2021-05-18 11:42 ` Robert Foss
2021-05-18 12:35 ` Jonathan Marek
1 sibling, 1 reply; 14+ messages in thread
From: Robert Foss @ 2021-05-18 11:42 UTC (permalink / raw)
To: Jonathan Marek
Cc: MSM, Andrey Konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list,
open list:COMMON CLK FRAMEWORK
Hey Jonathan,
> +static int cam_cc_sm8250_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
> + clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
> + clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
> + clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
> +
> + return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);;
Remove a semicolon.
> +}
> +
> +static struct platform_driver cam_cc_sm8250_driver = {
> + .probe = cam_cc_sm8250_probe,
> + .driver = {
> + .name = "cam_cc-sm8250",
Maybe conforming with the naming scheme of "sdm845-camcc" is the
better way to go.
> + .of_match_table = cam_cc_sm8250_match_table,
> + },
> +};
> +
> +static int __init cam_cc_sm8250_init(void)
> +{
> + return platform_driver_register(&cam_cc_sm8250_driver);
> +}
> +subsys_initcall(cam_cc_sm8250_init);
> +
> +static void __exit cam_cc_sm8250_exit(void)
> +{
> + platform_driver_unregister(&cam_cc_sm8250_driver);
> +}
> +module_exit(cam_cc_sm8250_exit);
> +
> +MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.26.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250
2021-05-18 11:42 ` Robert Foss
@ 2021-05-18 12:35 ` Jonathan Marek
2021-05-18 12:41 ` Robert Foss
0 siblings, 1 reply; 14+ messages in thread
From: Jonathan Marek @ 2021-05-18 12:35 UTC (permalink / raw)
To: Robert Foss
Cc: MSM, Andrey Konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list,
open list:COMMON CLK FRAMEWORK
On 5/18/21 7:42 AM, Robert Foss wrote:
> Hey Jonathan,
>
>
>> +static int cam_cc_sm8250_probe(struct platform_device *pdev)
>> +{
>> + struct regmap *regmap;
>> +
>> + regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
>> + clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
>> + clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
>> + clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
>> +
>> + return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);;
>
> Remove a semicolon.
>
>> +}
>> +
>> +static struct platform_driver cam_cc_sm8250_driver = {
>> + .probe = cam_cc_sm8250_probe,
>> + .driver = {
>> + .name = "cam_cc-sm8250",
>
> Maybe conforming with the naming scheme of "sdm845-camcc" is the
> better way to go.
>
On the other hand there is cam_cc-sc7180. But it doesn't matter either
way, I will change it.
>> + .of_match_table = cam_cc_sm8250_match_table,
>> + },
>> +};
>> +
>> +static int __init cam_cc_sm8250_init(void)
>> +{
>> + return platform_driver_register(&cam_cc_sm8250_driver);
>> +}
>> +subsys_initcall(cam_cc_sm8250_init);
>> +
>> +static void __exit cam_cc_sm8250_exit(void)
>> +{
>> + platform_driver_unregister(&cam_cc_sm8250_driver);
>> +}
>> +module_exit(cam_cc_sm8250_exit);
>> +
>> +MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.26.1
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250
2021-05-18 12:35 ` Jonathan Marek
@ 2021-05-18 12:41 ` Robert Foss
0 siblings, 0 replies; 14+ messages in thread
From: Robert Foss @ 2021-05-18 12:41 UTC (permalink / raw)
To: Jonathan Marek
Cc: MSM, Andrey Konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list,
open list:COMMON CLK FRAMEWORK
> >
> >> +}
> >> +
> >> +static struct platform_driver cam_cc_sm8250_driver = {
> >> + .probe = cam_cc_sm8250_probe,
> >> + .driver = {
> >> + .name = "cam_cc-sm8250",
> >
> > Maybe conforming with the naming scheme of "sdm845-camcc" is the
> > better way to go.
> >
>
> On the other hand there is cam_cc-sc7180. But it doesn't matter either
> way, I will change it.
>
Ah, I only looked at sdm845 for prior art. Either is fine then.
With this fixed & Vinods feedback, feel free to add my r-b.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-18 11:32 ` Vinod Koul
@ 2021-05-18 13:06 ` Jonathan Marek
2021-05-18 15:56 ` Vinod Koul
0 siblings, 1 reply; 14+ messages in thread
From: Jonathan Marek @ 2021-05-18 13:06 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-arm-msm, robert.foss, andrey.konovalov, Andy Gross,
Bjorn Andersson, Michael Turquette, Stephen Boyd,
open list:COMMON CLK FRAMEWORK, open list
On 5/18/21 7:32 AM, Vinod Koul wrote:
> On 13-05-21, 13:52, Jonathan Marek wrote:
...
>> +/* ZONDA PLL specific */
>> +#define ZONDA_PLL_OUT_MASK 0xf
>> +#define ZONDA_STAY_IN_CFA BIT(16)
>> +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
>
> This seems similar to ALPHA_PLL_ACK_LATCH..?
>
The bit is the same, and it is also used with wait_for_pll(), but the
meaning seems different (the usage pattern is different).
>> +const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
>> + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
>> + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
>> + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
>> +};
>> +EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
>
> Why add one more ops when we can reuse clk_alpha_pll_postdiv_fabia_ops
> for this?
>
No reason (copied from downstream), will fix.
>> +
>> + /* Set operation mode to OFF */
>> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
>> +
>> + /* PLL should be in OFF mode before continuing */
>> + wmb();
>
> Why a barrier?
>
Again no reason (copied from downstream, but it doesn't make sense to
have this barrier).
>> +static unsigned long
>> +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
>> +{
>> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>> + u32 l, frac;
>> +
>> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
>> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
>> +
>> + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
>> +}
>
> sounds like you could use clk_trion_pll_recalc_rate() instead
>
I had this thought as well, but alpha_width in
clk_trion_pll_recalc()_rate is 16, here ALPHA_BITWIDTH is 32, so I just
copied this from downstream.
I think changing pll_alpha_width() to return the right value for zonda
will work and allow sharing the function, if you think that's a good idea?
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-18 13:06 ` Jonathan Marek
@ 2021-05-18 15:56 ` Vinod Koul
0 siblings, 0 replies; 14+ messages in thread
From: Vinod Koul @ 2021-05-18 15:56 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, robert.foss, andrey.konovalov, Andy Gross,
Bjorn Andersson, Michael Turquette, Stephen Boyd,
open list:COMMON CLK FRAMEWORK, open list
On 18-05-21, 09:06, Jonathan Marek wrote:
> On 5/18/21 7:32 AM, Vinod Koul wrote:
> > > +static unsigned long
> > > +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > > +{
> > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> > > + u32 l, frac;
> > > +
> > > + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> > > + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> > > +
> > > + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
> > > +}
> >
> > sounds like you could use clk_trion_pll_recalc_rate() instead
> >
>
> I had this thought as well, but alpha_width in clk_trion_pll_recalc()_rate
> is 16, here ALPHA_BITWIDTH is 32, so I just copied this from downstream.
>
> I think changing pll_alpha_width() to return the right value for zonda will
> work and allow sharing the function, if you think that's a good idea?
Yes I thinking pll_alpha_width() should do the trick here
Thanks
--
~Vinod
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
2021-05-18 11:15 ` Robert Foss
2021-05-18 11:32 ` Vinod Koul
@ 2021-05-19 4:52 ` Taniya Das
2 siblings, 0 replies; 14+ messages in thread
From: Taniya Das @ 2021-05-19 4:52 UTC (permalink / raw)
To: Jonathan Marek, linux-arm-msm
Cc: robert.foss, andrey.konovalov, Andy Gross, Bjorn Andersson,
Michael Turquette, Stephen Boyd, open list:COMMON CLK FRAMEWORK,
open list
On 5/13/2021 11:22 PM, Jonathan Marek wrote:
> Ported over from the downstream driver. Will be used by SM8250 CAMCC.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 245 +++++++++++++++++++++++++++++++
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> 2 files changed, 251 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index c6eb99169ddc..7b332a8935f4 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_TEST_CTL_U] = 0x1c,
> [PLL_OFF_STATUS] = 0x2c,
> },
> + [CLK_ALPHA_PLL_TYPE_ZONDA] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_USER_CTL] = 0x0c,
> + [PLL_OFF_CONFIG_CTL] = 0x10,
> + [PLL_OFF_CONFIG_CTL_U] = 0x14,
> + [PLL_OFF_CONFIG_CTL_U1] = 0x18,
> + [PLL_OFF_TEST_CTL] = 0x1c,
> + [PLL_OFF_TEST_CTL_U] = 0x20,
> + [PLL_OFF_TEST_CTL_U1] = 0x24,
> + [PLL_OFF_OPMODE] = 0x28,
> + [PLL_OFF_STATUS] = 0x38,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> @@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
> #define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
>
> +/* ZONDA PLL specific */
> +#define ZONDA_PLL_OUT_MASK 0xf
> +#define ZONDA_STAY_IN_CFA BIT(16)
> +#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
> +
> #define pll_alpha_width(p) \
> ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
> ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
> @@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
> #define wait_for_pll_enable_lock(pll) \
> wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
>
> +#define wait_for_zonda_pll_freq_lock(pll) \
> + wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
> +
> #define wait_for_pll_disable(pll) \
> wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
>
> @@ -1398,6 +1419,13 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
>
> +const struct clk_ops clk_alpha_pll_postdiv_zonda_ops = {
> + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
> + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
> + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_postdiv_zonda_ops);
> +
> /**
> * clk_lucid_pll_configure - configure the lucid pll
> *
> @@ -1777,3 +1805,220 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
> .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
> };
> EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
> +
> +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> + const struct alpha_pll_config *config)
> +{
> + if (config->l)
> + regmap_write(regmap, PLL_L_VAL(pll), config->l);
> +
Please use
clk_alpha_pll_write_config
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll),
config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
config->test_ctl_hi1_val);
> + if (config->alpha)
> + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> + if (config->config_ctl_val)
> + regmap_write(regmap, PLL_CONFIG_CTL(pll),
> + config->config_ctl_val);
> +
> + if (config->config_ctl_hi_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> + config->config_ctl_hi_val);
> +
> + if (config->config_ctl_hi1_val)
> + regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
> + config->config_ctl_hi1_val);
> +
> + if (config->user_ctl_val)
> + regmap_write(regmap, PLL_USER_CTL(pll),
> + config->user_ctl_val);
> +
> + if (config->user_ctl_hi_val)
> + regmap_write(regmap, PLL_USER_CTL_U(pll),
> + config->user_ctl_hi_val);
> +
> + if (config->user_ctl_hi1_val)
> + regmap_write(regmap, PLL_USER_CTL_U1(pll),
> + config->user_ctl_hi1_val);
> +
> + if (config->test_ctl_val)
> + regmap_write(regmap, PLL_TEST_CTL(pll),
> + config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val)
> + regmap_write(regmap, PLL_TEST_CTL_U(pll),
> + config->test_ctl_hi_val);
> +
> + if (config->test_ctl_hi1_val)
> + regmap_write(regmap, PLL_TEST_CTL_U1(pll),
> + config->test_ctl_hi1_val);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_BYPASSNL, 0);
> +
> + /* Disable PLL output */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Set operation mode to OFF */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +
> + /* PLL should be in OFF mode before continuing */
> + wmb();
> +
> + /* Place the PLL in STANDBY mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +}
> +
> +static int clk_zonda_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If in FSM mode, just vote for it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + ret = clk_enable_regmap(hw);
> + if (ret)
> + return ret;
> + return wait_for_pll_enable_active(pll);
> + }
> +
> + /* Get the PLL out of bypass mode */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
> +
> + /*
> + * H/W requires a 1us delay between disabling the bypass and
> + * de-asserting the reset.
> + */
> + mb();
> + udelay(1);
> +
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +
> + /* Set operation mode to RUN */
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> +
> + ret = regmap_read(regmap, PLL_TEST_CTL(pll), &val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Enable the PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> + ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
> + if (ret)
> + return ret;
> +
> + /* Enable the global PLL outputs */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll),
> + PLL_OUTCTRL, PLL_OUTCTRL);
> + if (ret)
> + return ret;
> +
> + /* Ensure that the write above goes through before returning. */
> + mb();
> +
> + return 0;
> +}
> +
> +static void clk_zonda_pll_disable(struct clk_hw *hw)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + struct regmap *regmap = pll->clkr.regmap;
> + u32 val;
> + int ret;
> +
> + ret = regmap_read(regmap, PLL_MODE(pll), &val);
> + if (ret)
> + return;
> +
> + /* If in FSM mode, just unvote it */
> + if (val & PLL_VOTE_FSM_ENA) {
> + clk_disable_regmap(hw);
> + return;
> + }
> +
> + /* Disable the global PLL output */
> + ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> +
> + /* Disable the PLL outputs */
> + regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
> +
> + /* Put the PLL in bypass and reset */
> + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
> +
> + /* Place the PLL mode in OFF state */
> + regmap_write(regmap, PLL_OPMODE(pll), 0x0);
> +}
> +
> +static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + unsigned long rrate;
> + u32 test_ctl_val;
> + u32 l;
alpha_width = pll_alpha_width(pll);
> + u64 a;
> + int ret;
> +
> + rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_BITWIDTH);
> +
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
> + ret = alpha_pll_check_rate_margin(hw, rrate, rate);
> + if (ret < 0)
> + return ret;
> +
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +
> + /* Wait before polling for the frequency latch */
> + udelay(5);
> +
> + /* Read stay in cfa mode */
> + ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
> + if (ret)
> + return ret;
> +
> + /* If cfa mode then poll for freq lock */
> + if (test_ctl_val & ZONDA_STAY_IN_CFA)
> + ret = wait_for_zonda_pll_freq_lock(pll);
> + else
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + /* Wait for PLL output to stabilize */
> + udelay(100);
> + return 0;
> +}
> +
> +static unsigned long
> +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l, frac;
> +
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> +
> + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
alpha_width = pll_alpha_width(pll);
> +}
> +
> +const struct clk_ops clk_alpha_pll_zonda_ops = {
> + .enable = clk_zonda_pll_enable,
> + .disable = clk_zonda_pll_disable,
> + .is_enabled = clk_trion_pll_is_enabled,
> + .recalc_rate = clk_zonda_pll_recalc_rate,
> + .round_rate = clk_alpha_pll_round_rate,
> + .set_rate = clk_zonda_pll_set_rate,
> +};
> +EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index 6943e933be0f..4871af27cf76 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -16,6 +16,7 @@ enum {
> CLK_ALPHA_PLL_TYPE_TRION,
> CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
> CLK_ALPHA_PLL_TYPE_AGERA,
> + CLK_ALPHA_PLL_TYPE_ZONDA,
> CLK_ALPHA_PLL_TYPE_MAX,
> };
>
> @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
> extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
> extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
>
> +extern const struct clk_ops clk_alpha_pll_zonda_ops;
> +extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops;
> +
> void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> const struct alpha_pll_config *config);
> void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> @@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> #define clk_lucid_pll_configure(pll, regmap, config) \
> clk_trion_pll_configure(pll, regmap, config)
>
> +void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> + const struct alpha_pll_config *config);
>
>
> #endif
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-05-19 4:52 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-13 17:52 [PATCH 0/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-13 17:52 ` [PATCH 1/3] clk: qcom: clk-alpha-pll: add support for zonda pll Jonathan Marek
2021-05-18 11:15 ` Robert Foss
2021-05-18 11:32 ` Vinod Koul
2021-05-18 13:06 ` Jonathan Marek
2021-05-18 15:56 ` Vinod Koul
2021-05-19 4:52 ` Taniya Das
2021-05-13 17:52 ` [PATCH 2/3] dt-bindings: clock: add QCOM SM8250 camera clock bindings Jonathan Marek
2021-05-14 13:06 ` Rob Herring
2021-05-13 17:52 ` [PATCH 3/3] clk: qcom: Add camera clock controller driver for SM8250 Jonathan Marek
2021-05-18 11:39 ` Vinod Koul
2021-05-18 11:42 ` Robert Foss
2021-05-18 12:35 ` Jonathan Marek
2021-05-18 12:41 ` Robert Foss
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