linux-arm-msm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v2 0/6] drm/msm/dpu: rework irq handling
@ 2021-05-16 20:29 Dmitry Baryshkov
  2021-05-16 20:29 ` [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs Dmitry Baryshkov
                   ` (5 more replies)
  0 siblings, 6 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

Simplify IRQ handling. dpu_irq_map is a huge table consisting of all
possible IRQ entries (including a plenty of 'reserved' = not existing
IRQs). It is always used to lookup the interrupt index (in the table)
and then to use this index to lookup related interrupt register and
mask. For the long period of time these indices had 1:1 correspondence
to register/mask pairs. SC7280 introduced 'additional' IRQs removing
this correpondence.

Replace all IRQ lookup with stable irq indices, which correponds
directly to the register/bit pair. The irq indices are now fetched from
the hw catalog rather than being looked up using the hw block id and irq
type.

Changes since v1:
 - move IRQ indices to hw catalog rather than looking them up from the
   big dpu_irq_map table (as suggested by Bjorn).
 - add patch to squash irq enable/disable into
   dpu_core_irq_register_callback()/dpu_core_irq_unregister_callback()

Changes since RFC:
 - rebase on top of msm/msm-next to include SC7280 changes.


The following changes since commit f2f46b878777e0d3f885c7ddad48f477b4dea247:

  drm/msm/dp: initialize audio_comp when audio starts (2021-05-06 16:26:57 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/dmitry.baryshkov/kernel.git dpu-irq-simplify-2

for you to fetch changes up to ec3d935f9a18aeb3ebf5482eba7133cec020e047:

  drm/msm/dpu: simplify IRQ enabling/disabling (2021-05-16 23:19:56 +0300)

----------------------------------------------------------------
Dmitry Baryshkov (6):
      drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
      drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock
      drm/msm/dpu: define interrupt register names
      drm/msm/dpu: replace IRQ lookup with the data in hw catalog
      drm/msm/dpu: drop remains of old irq lookup subsystem
      drm/msm/dpu: simplify IRQ enabling/disabling

 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c       |  203 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h       |   43 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |   74 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |    4 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   40 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   33 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |  202 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   14 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c  | 1450 ++------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h  |  112 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h            |    2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h          |   36 +-
 12 files changed, 330 insertions(+), 1883 deletions(-)



^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 21:44   ` [Freedreno] " abhinavk
  2021-05-16 20:29 ` [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock Dmitry Baryshkov
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

There is little sense in reading interrupt statuses and right after that
going after the array of statuses to dispatch them. Merge both loops
into single function doing read and dispatch.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  | 10 +--
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 66 ++++++-------------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  8 ---
 3 files changed, 20 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index cdec3fbe6ff4..54b34746a587 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -376,15 +376,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
 
 irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
 {
-	/*
-	 * Read interrupt status from all sources. Interrupt status are
-	 * stored within hw_intr.
-	 * Function will also clear the interrupt status after reading.
-	 * Individual interrupt status bit will only get stored if it
-	 * is enabled.
-	 */
-	dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
-
 	/*
 	 * Dispatch to HW driver to handle interrupt lookup that is being
 	 * fired. When matching interrupt is located, HW driver will call to
@@ -392,6 +383,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
 	 * dpu_core_irq_callback_handler will perform the registered function
 	 * callback, and do the interrupt status clearing once the registered
 	 * callback is finished.
+	 * Function will also clear the interrupt status after reading.
 	 */
 	dpu_kms->hw_intr->ops.dispatch_irqs(
 			dpu_kms->hw_intr,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 48c96b812126..cf9bfd45aa59 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -1371,6 +1371,7 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 	int start_idx;
 	int end_idx;
 	u32 irq_status;
+	u32 enable_mask;
 	unsigned long irq_flags;
 
 	if (!intr)
@@ -1383,8 +1384,6 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 	 */
 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
 	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
-		irq_status = intr->save_irq_status[reg_idx];
-
 		/*
 		 * Each Interrupt register has a range of 64 indexes, and
 		 * that is static for dpu_irq_map.
@@ -1396,6 +1395,20 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 			start_idx >= ARRAY_SIZE(dpu_irq_map))
 			continue;
 
+		/* Read interrupt status */
+		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
+
+		/* Read enable mask */
+		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
+
+		/* and clear the interrupt */
+		if (irq_status)
+			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+				     irq_status);
+
+		/* Finally update IRQ status based on enable mask */
+		irq_status &= enable_mask;
+
 		/*
 		 * Search through matching intr status from irq map.
 		 * start_idx and end_idx defined the search range in
@@ -1429,6 +1442,10 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 				irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
 			}
 	}
+
+	/* ensure register writes go through */
+	wmb();
+
 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
 }
 
@@ -1580,41 +1597,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
 	return 0;
 }
 
-static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr)
-{
-	int i;
-	u32 enable_mask;
-	unsigned long irq_flags;
-
-	if (!intr)
-		return;
-
-	spin_lock_irqsave(&intr->irq_lock, irq_flags);
-	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
-		if (!test_bit(i, &intr->irq_mask))
-			continue;
-
-		/* Read interrupt status */
-		intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
-				dpu_intr_set[i].status_off);
-
-		/* Read enable mask */
-		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
-
-		/* and clear the interrupt */
-		if (intr->save_irq_status[i])
-			DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off,
-					intr->save_irq_status[i]);
-
-		/* Finally update IRQ status based on enable mask */
-		intr->save_irq_status[i] &= enable_mask;
-	}
-
-	/* ensure register writes go through */
-	wmb();
-
-	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
-}
 
 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 		int irq_idx)
@@ -1673,7 +1655,6 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
 	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
 	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
 	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
-	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
 	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
 	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
 }
@@ -1710,14 +1691,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 		return ERR_PTR(-ENOMEM);
 	}
 
-	intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
-			GFP_KERNEL);
-	if (intr->save_irq_status == NULL) {
-		kfree(intr->cache_irq_mask);
-		kfree(intr);
-		return ERR_PTR(-ENOMEM);
-	}
-
 	intr->irq_mask = m->mdss_irqs;
 	intr->obsolete_irq = m->obsolete_irq;
 
@@ -1730,7 +1703,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr *intr)
 {
 	if (intr) {
 		kfree(intr->cache_irq_mask);
-		kfree(intr->save_irq_status);
 		kfree(intr);
 	}
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 5d6f9a7a5195..5a1c304ba93f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -142,14 +142,6 @@ struct dpu_hw_intr_ops {
 			void (*cbfunc)(void *arg, int irq_idx),
 			void *arg);
 
-	/**
-	 * get_interrupt_statuses - Gets and store value from all interrupt
-	 *                          status registers that are currently fired.
-	 * @intr:	HW interrupt handle
-	 */
-	void (*get_interrupt_statuses)(
-			struct dpu_hw_intr *intr);
-
 	/**
 	 * clear_intr_status_nolock() - clears the HW interrupts without lock
 	 * @intr:	HW interrupt handle
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
  2021-05-16 20:29 ` [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 21:46   ` [Freedreno] " abhinavk
  2021-05-16 20:29 ` [PATCH v2 3/6] drm/msm/dpu: define interrupt register names Dmitry Baryshkov
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

Always call dpu_hw_intr_clear_intr_status_nolock() from the
dpu_hw_intr_dispatch_irqs(). This simplifies the callback function
(which call clears the interrupts anyway) and enforces clearing the hw
interrupt status.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  9 -----
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 39 +++++++++----------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  9 -----
 3 files changed, 18 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 54b34746a587..fd11a2aeab6c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -41,15 +41,6 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 		if (cb->func)
 			cb->func(cb->arg, irq_idx);
 	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
-
-	/*
-	 * Clear pending interrupt status in HW.
-	 * NOTE: dpu_core_irq_callback_handler is protected by top-level
-	 *       spinlock, so it is safe to clear any interrupt status here.
-	 */
-	dpu_kms->hw_intr->ops.clear_intr_status_nolock(
-			dpu_kms->hw_intr,
-			irq_idx);
 }
 
 int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index cf9bfd45aa59..8bd22e060437 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -1362,6 +1362,22 @@ static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
 	return -EINVAL;
 }
 
+static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
+		int irq_idx)
+{
+	int reg_idx;
+
+	if (!intr)
+		return;
+
+	reg_idx = dpu_irq_map[irq_idx].reg_idx;
+	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+			dpu_irq_map[irq_idx].irq_mask);
+
+	/* ensure register writes go through */
+	wmb();
+}
+
 static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 		void (*cbfunc)(void *, int),
 		void *arg)
@@ -1430,9 +1446,8 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 				 */
 				if (cbfunc)
 					cbfunc(arg, irq_idx);
-				else
-					intr->ops.clear_intr_status_nolock(
-							intr, irq_idx);
+
+				dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
 
 				/*
 				 * When callback finish, clear the irq_status
@@ -1597,23 +1612,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr)
 	return 0;
 }
 
-
-static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
-		int irq_idx)
-{
-	int reg_idx;
-
-	if (!intr)
-		return;
-
-	reg_idx = dpu_irq_map[irq_idx].reg_idx;
-	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
-			dpu_irq_map[irq_idx].irq_mask);
-
-	/* ensure register writes go through */
-	wmb();
-}
-
 static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 		int irq_idx, bool clear)
 {
@@ -1655,7 +1653,6 @@ static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
 	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
 	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
 	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
-	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
 	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 5a1c304ba93f..5bade5637ecc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -142,15 +142,6 @@ struct dpu_hw_intr_ops {
 			void (*cbfunc)(void *arg, int irq_idx),
 			void *arg);
 
-	/**
-	 * clear_intr_status_nolock() - clears the HW interrupts without lock
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 */
-	void (*clear_intr_status_nolock)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
 	/**
 	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
 	 *                        based on given lookup IRQ index.
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 3/6] drm/msm/dpu: define interrupt register names
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
  2021-05-16 20:29 ` [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs Dmitry Baryshkov
  2021-05-16 20:29 ` [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 21:51   ` [Freedreno] " abhinavk
  2021-05-16 20:29 ` [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog Dmitry Baryshkov
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

In order to make mdss_irqs readable (and error-prone) define names for
interrupt register indices.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 45 ++++++++++++++++---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 18 ++++++++
 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b569030a0847..9a77d64d3fd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -7,6 +7,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include "dpu_hw_mdss.h"
+#include "dpu_hw_interrupts.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_kms.h"
 
@@ -56,6 +57,23 @@
 
 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
 
+#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_INTR) | \
+			 BIT(MDP_INTF1_INTR) | \
+			 BIT(MDP_INTF2_INTR) | \
+			 BIT(MDP_INTF3_INTR) | \
+			 BIT(MDP_INTF4_INTR) | \
+			 BIT(MDP_AD4_0_INTR) | \
+			 BIT(MDP_AD4_1_INTR))
+
+#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_INTR) | \
+			 BIT(MDP_INTF1_INTR))
+
 #define INTR_SC7180_MASK \
 	(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
 	BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
@@ -63,6 +81,23 @@
 	BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
 	BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
 
+#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_7xxx_INTR) | \
+			 BIT(MDP_INTF1_7xxx_INTR) | \
+			 BIT(MDP_INTF5_7xxx_INTR))
+
+#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+			 BIT(MDP_SSPP_TOP0_INTR2) | \
+			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+			 BIT(MDP_INTF0_INTR) | \
+			 BIT(MDP_INTF1_INTR) | \
+			 BIT(MDP_INTF2_INTR) | \
+			 BIT(MDP_INTF3_INTR) | \
+			 BIT(MDP_INTF4_INTR))
+
+
 #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
 #define DEFAULT_DPU_LINE_WIDTH		2048
 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH	2560
@@ -1060,7 +1095,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
 		.perf = sdm845_perf_data,
-		.mdss_irqs = 0x3ff,
+		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
 
@@ -1091,7 +1126,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.reg_dma_count = 1,
 		.dma_cfg = sdm845_regdma,
 		.perf = sc7180_perf_data,
-		.mdss_irqs = 0x3f,
+		.mdss_irqs = IRQ_SC7180_MASK,
 		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }
@@ -1125,7 +1160,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.reg_dma_count = 1,
 		.dma_cfg = sm8150_regdma,
 		.perf = sm8150_perf_data,
-		.mdss_irqs = 0x3ff,
+		.mdss_irqs = IRQ_SDM845_MASK,
 	};
 }
 
@@ -1158,7 +1193,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.reg_dma_count = 1,
 		.dma_cfg = sm8250_regdma,
 		.perf = sm8250_perf_data,
-		.mdss_irqs = 0xff,
+		.mdss_irqs = IRQ_SM8250_MASK,
 	};
 }
 
@@ -1181,7 +1216,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif_count = ARRAY_SIZE(sdm845_vbif),
 		.vbif = sdm845_vbif,
 		.perf = sc7280_perf_data,
-		.mdss_irqs = 0x1c07,
+		.mdss_irqs = IRQ_SC7280_MASK,
 		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 5bade5637ecc..b26a3445a8eb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -74,6 +74,24 @@ enum dpu_intr_type {
 	DPU_IRQ_TYPE_RESERVED,
 };
 
+/* When making changes be sure to sync with dpu_intr_set */
+enum dpu_hw_intr_reg {
+	MDP_SSPP_TOP0_INTR,
+	MDP_SSPP_TOP0_INTR2,
+	MDP_SSPP_TOP0_HIST_INTR,
+	MDP_INTF0_INTR,
+	MDP_INTF1_INTR,
+	MDP_INTF2_INTR,
+	MDP_INTF3_INTR,
+	MDP_INTF4_INTR,
+	MDP_AD4_0_INTR,
+	MDP_AD4_1_INTR,
+	MDP_INTF0_7xxx_INTR,
+	MDP_INTF1_7xxx_INTR,
+	MDP_INTF5_7xxx_INTR,
+	MDP_INTR_MAX,
+};
+
 struct dpu_hw_intr;
 
 /**
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
                   ` (2 preceding siblings ...)
  2021-05-16 20:29 ` [PATCH v2 3/6] drm/msm/dpu: define interrupt register names Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 21:57   ` [Freedreno] " abhinavk
  2021-05-16 20:29 ` [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem Dmitry Baryshkov
  2021-05-16 20:29 ` [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling Dmitry Baryshkov
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to
maintain. There are only few interrupts used from that table. Newer
generations use different IRQ locations. Move this data to hw catalog.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  20 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h  |  13 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  64 +++-----
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |   2 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  |  36 ++---
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |  31 +---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 150 +++++++++++-------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  12 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 137 +++++++---------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h     |  28 ++--
 11 files changed, 229 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index fd11a2aeab6c..11c0abed21ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -43,16 +43,6 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
 }
 
-int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
-		enum dpu_intr_type intr_type, u32 instance_idx)
-{
-	if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
-		return -EINVAL;
-
-	return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
-			intr_type, instance_idx);
-}
-
 /**
  * _dpu_core_irq_enable - enable core interrupt given by the index
  * @dpu_kms:		Pointer to dpu kms context
@@ -70,7 +60,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
 		return -EINVAL;
 	}
 
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
 		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
@@ -133,7 +123,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
 		return -EINVAL;
 	}
 
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
 		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
@@ -208,7 +198,7 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx,
 		return -EINVAL;
 	}
 
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
 		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
@@ -243,7 +233,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
 		return -EINVAL;
 	}
 
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
+	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
 		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
@@ -328,7 +318,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
 	spin_lock_init(&dpu_kms->irq_obj.cb_lock);
 
 	/* Create irq callbacks for all possible irq_idx */
-	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
+	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
 	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
 			sizeof(struct list_head), GFP_KERNEL);
 	dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
index e30775e6585b..d147784d5531 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
@@ -29,19 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms);
  */
 irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
 
-/**
- * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW
- *                      interrupt mapping table.
- * @dpu_kms:		DPU handle
- * @intr_type:		DPU HW interrupt type for lookup
- * @instance_idx:	DPU HW block instance defined in dpu_hw_mdss.h
- * @return:		irq_idx or -EINVAL when fail to lookup
- */
-int dpu_core_irq_idx_lookup(
-		struct dpu_kms *dpu_kms,
-		enum dpu_intr_type intr_type,
-		uint32_t instance_idx);
-
 /**
  * dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs
  * @dpu_kms:		DPU handle
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 8d942052db8a..8a9d01e3b664 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -253,7 +253,7 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 }
 
 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
-		int32_t hw_id, struct dpu_encoder_wait_info *info);
+		u32 irq_idx, struct dpu_encoder_wait_info *info);
 
 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 		enum dpu_intr_idx intr_idx,
@@ -273,27 +273,27 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 
 	/* return EWOULDBLOCK since we know the wait isn't necessary */
 	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
-		DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx);
 		return -EWOULDBLOCK;
 	}
 
 	if (irq->irq_idx < 0) {
-		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
-			      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
+			      DRMID(phys_enc->parent), intr_idx,
 			      irq->name);
 		return 0;
 	}
 
-	DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
-		      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+	DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
+		      DRMID(phys_enc->parent), intr_idx,
 		      irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 		      atomic_read(wait_info->atomic_cnt));
 
 	ret = dpu_encoder_helper_wait_event_timeout(
 			DRMID(phys_enc->parent),
-			irq->hw_idx,
+			irq->irq_idx,
 			wait_info);
 
 	if (ret <= 0) {
@@ -303,9 +303,9 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 			unsigned long flags;
 
 			DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
-				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+				      "irq=%d, pp=%d, atomic_cnt=%d",
 				      DRMID(phys_enc->parent), intr_idx,
-				      irq->hw_idx, irq->irq_idx,
+				      irq->irq_idx,
 				      phys_enc->hw_pp->idx - PINGPONG_0,
 				      atomic_read(wait_info->atomic_cnt));
 			local_irq_save(flags);
@@ -315,16 +315,16 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 		} else {
 			ret = -ETIMEDOUT;
 			DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
-				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
+				      "irq=%d, pp=%d, atomic_cnt=%d",
 				      DRMID(phys_enc->parent), intr_idx,
-				      irq->hw_idx, irq->irq_idx,
+				      irq->irq_idx,
 				      phys_enc->hw_pp->idx - PINGPONG_0,
 				      atomic_read(wait_info->atomic_cnt));
 		}
 	} else {
 		ret = 0;
 		trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
-			intr_idx, irq->hw_idx, irq->irq_idx,
+			intr_idx, irq->irq_idx,
 			phys_enc->hw_pp->idx - PINGPONG_0,
 			atomic_read(wait_info->atomic_cnt));
 	}
@@ -344,19 +344,9 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 	}
 	irq = &phys_enc->irq[intr_idx];
 
-	if (irq->irq_idx >= 0) {
-		DPU_DEBUG_PHYS(phys_enc,
-				"skipping already registered irq %s type %d\n",
-				irq->name, irq->intr_type);
-		return 0;
-	}
-
-	irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
-			irq->intr_type, irq->hw_idx);
 	if (irq->irq_idx < 0) {
 		DPU_ERROR_PHYS(phys_enc,
-			"failed to lookup IRQ index for %s type:%d\n",
-			irq->name, irq->intr_type);
+			"invalid IRQ index:%d\n", irq->irq_idx);
 		return -EINVAL;
 	}
 
@@ -372,8 +362,8 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 
 	ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 	if (ret) {
-		DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_ERROR("enable failed id=%u, intr=%d, irq=%d",
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx);
 		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
 				irq->irq_idx, &irq->cb);
@@ -382,7 +372,7 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 	}
 
 	trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
-				irq->hw_idx, irq->irq_idx);
+				irq->irq_idx);
 
 	return ret;
 }
@@ -397,31 +387,29 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 
 	/* silently skip irqs that weren't registered */
 	if (irq->irq_idx < 0) {
-		DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx);
 		return 0;
 	}
 
 	ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
 	if (ret) {
-		DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_ERROR("disable failed id=%u, intr=%d, irq=%d ret=%d",
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx, ret);
 	}
 
 	ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 			&irq->cb);
 	if (ret) {
-		DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
-			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
+		DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
+			  DRMID(phys_enc->parent), intr_idx,
 			  irq->irq_idx, ret);
 	}
 
 	trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
-					     irq->hw_idx, irq->irq_idx);
-
-	irq->irq_idx = -EINVAL;
+					     irq->irq_idx);
 
 	return 0;
 }
@@ -1537,7 +1525,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
 
 static int dpu_encoder_helper_wait_event_timeout(
 		int32_t drm_id,
-		int32_t hw_id,
+		u32 irq_idx,
 		struct dpu_encoder_wait_info *info)
 {
 	int rc = 0;
@@ -1550,7 +1538,7 @@ static int dpu_encoder_helper_wait_event_timeout(
 				atomic_read(info->atomic_cnt) == 0, jiffies);
 		time = ktime_to_ms(ktime_get());
 
-		trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
+		trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
 						 expected_time,
 						 atomic_read(info->atomic_cnt));
 	/* If we timed out, counter is valid and time is less, wait again */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index ecbc4be98980..3bd12ce45a80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -167,7 +167,6 @@ enum dpu_intr_idx {
  * @name:		string name of interrupt
  * @intr_type:		Encoder interrupt type
  * @intr_idx:		Encoder interrupt enumeration
- * @hw_idx:		HW Block ID
  * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
  *			will be -EINVAL if IRQ is not registered
  * @irq_cb:		interrupt callback
@@ -176,7 +175,6 @@ struct dpu_encoder_irq {
 	const char *name;
 	enum dpu_intr_type intr_type;
 	enum dpu_intr_idx intr_idx;
-	int hw_idx;
 	int irq_idx;
 	struct dpu_irq_callback cb;
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b2be39b9144e..6f06e379b97f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -143,28 +143,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
-static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_irq *irq;
-
-	irq = &phys_enc->irq[INTR_IDX_CTL_START];
-	irq->hw_idx = phys_enc->hw_ctl->idx;
-	irq->irq_idx = -EINVAL;
-
-	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
-	irq->hw_idx = phys_enc->hw_pp->idx;
-	irq->irq_idx = -EINVAL;
-
-	irq = &phys_enc->irq[INTR_IDX_RDPTR];
-	irq->hw_idx = phys_enc->hw_pp->idx;
-	irq->irq_idx = -EINVAL;
-
-	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
-	irq->hw_idx = phys_enc->intf_idx;
-	irq->irq_idx = -EINVAL;
-}
-
 static void dpu_encoder_phys_cmd_mode_set(
 		struct dpu_encoder_phys *phys_enc,
 		struct drm_display_mode *mode,
@@ -172,6 +150,7 @@ static void dpu_encoder_phys_cmd_mode_set(
 {
 	struct dpu_encoder_phys_cmd *cmd_enc =
 		to_dpu_encoder_phys_cmd(phys_enc);
+	struct dpu_encoder_irq *irq;
 
 	if (!mode || !adj_mode) {
 		DPU_ERROR("invalid args\n");
@@ -181,7 +160,17 @@ static void dpu_encoder_phys_cmd_mode_set(
 	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
 	drm_mode_debug_printmodeline(adj_mode);
 
-	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
+	irq = &phys_enc->irq[INTR_IDX_CTL_START];
+	irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
+
+	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
+	irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
+
+	irq = &phys_enc->irq[INTR_IDX_RDPTR];
+	irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
+
+	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
+	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
 }
 
 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
@@ -795,7 +784,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 		irq = &phys_enc->irq[i];
 		INIT_LIST_HEAD(&irq->cb.list);
 		irq->irq_idx = -EINVAL;
-		irq->hw_idx = -EINVAL;
 		irq->cb.arg = phys_enc;
 	}
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0e06b7e73c7a..6cdb4ecbc173 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -363,38 +363,24 @@ static bool dpu_encoder_phys_vid_needs_single_flush(
 	return phys_enc->split_role != ENC_ROLE_SOLO;
 }
 
-static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_irq *irq;
-
-	/*
-	 * Initialize irq->hw_idx only when irq is not registered.
-	 * Prevent invalidating irq->irq_idx as modeset may be
-	 * called many times during dfps.
-	 */
-
-	irq = &phys_enc->irq[INTR_IDX_VSYNC];
-	if (irq->irq_idx < 0)
-		irq->hw_idx = phys_enc->intf_idx;
-
-	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
-	if (irq->irq_idx < 0)
-		irq->hw_idx = phys_enc->intf_idx;
-}
-
 static void dpu_encoder_phys_vid_mode_set(
 		struct dpu_encoder_phys *phys_enc,
 		struct drm_display_mode *mode,
 		struct drm_display_mode *adj_mode)
 {
+	struct dpu_encoder_irq *irq;
+
 	if (adj_mode) {
 		phys_enc->cached_mode = *adj_mode;
 		drm_mode_debug_printmodeline(adj_mode);
 		DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
 	}
 
-	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
+	irq = &phys_enc->irq[INTR_IDX_VSYNC];
+	irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
+
+	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
+	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
 }
 
 static int dpu_encoder_phys_vid_control_vblank_irq(
@@ -636,7 +622,7 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
 
 	if (enable) {
 		ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
-		if (ret)
+		if (WARN_ON(ret))
 			return;
 
 		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
@@ -738,7 +724,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 		irq = &phys_enc->irq[i];
 		INIT_LIST_HEAD(&irq->cb.list);
 		irq->irq_idx = -EINVAL;
-		irq->hw_idx = -EINVAL;
 		irq->cb.arg = phys_enc;
 	}
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 9a77d64d3fd4..f929131ed260 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -350,27 +350,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x1600, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 	{
 	.name = "ctl_4", .id = CTL_4,
 	.base = 0x1800, .len = 0xE4,
-	.features = 0
+	.features = 0,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 	},
 };
 
@@ -378,17 +383,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0xE4,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 };
 
@@ -396,32 +404,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x1000, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x1200, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
+	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x1400, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x1600, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 	{
 	.name = "ctl_4", .id = CTL_4,
 	.base = 0x1800, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
 	},
 	{
 	.name = "ctl_5", .id = CTL_5,
 	.base = 0x1a00, .len = 0x1e0,
-	.features = BIT(DPU_CTL_ACTIVE_CFG)
+	.features = BIT(DPU_CTL_ACTIVE_CFG),
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
 	},
 };
 
@@ -429,22 +443,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x15000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
 	.base = 0x16000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
 	},
 	{
 	.name = "ctl_2", .id = CTL_2,
 	.base = 0x17000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
 	},
 	{
 	.name = "ctl_3", .id = CTL_3,
 	.base = 0x18000, .len = 0x1E8,
-	.features = CTL_SC7280_MASK
+	.features = CTL_SC7280_MASK,
+	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
 	},
 };
 
@@ -725,42 +743,66 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
 	.len = 0x20, .version = 0x20000},
 };
 
-#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
+#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0xd4, \
 	.features = PINGPONG_SDM845_SPLIT_MASK, \
 	.merge_3d = _merge_3d, \
-	.sblk = &_sblk \
+	.sblk = &_sblk, \
+	.intr_done = _done, \
+	.intr_rdptr = _rdptr, \
 	}
-#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
+#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0xd4, \
 	.features = PINGPONG_SDM845_MASK, \
 	.merge_3d = _merge_3d, \
-	.sblk = &_sblk \
+	.sblk = &_sblk, \
+	.intr_done = _done, \
+	.intr_rdptr = _rdptr, \
 	}
 
 static const struct dpu_pingpong_cfg sdm845_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
 };
 
 static struct dpu_pingpong_cfg sc7180_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
 };
 
 static const struct dpu_pingpong_cfg sm8150_pp[] = {
-	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te),
-	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk),
-	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk),
-	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk),
+	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+			-1),
+	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
+			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+			-1),
 };
 
 /*************************************************************
@@ -781,47 +823,49 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
 };
 
 static const struct dpu_pingpong_cfg sc7280_pp[] = {
-	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
-	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
-	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
-	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
+	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
+	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
+	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
+	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
 };
 /*************************************************************
  * INTF sub blocks config
  *************************************************************/
-#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \
+#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = 0x280, \
 	.features = _features, \
 	.type = _type, \
 	.controller_id = _ctrl_id, \
-	.prog_fetch_lines_worst_case = _progfetch \
+	.prog_fetch_lines_worst_case = _progfetch, \
+	.intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
+	.intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
 	}
 
 static const struct dpu_intf_cfg sdm845_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK),
-	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK),
-	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 };
 
 static const struct dpu_intf_cfg sc7180_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
 };
 
 static const struct dpu_intf_cfg sm8150_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK),
-	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK),
-	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK),
-	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 };
 
 static const struct dpu_intf_cfg sc7280_intf[] = {
-	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK),
-	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK),
-	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK),
+	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
 };
 
 /*************************************************************
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4dfd8a20ad5c..316da2971320 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -464,13 +464,15 @@ struct dpu_mdp_cfg {
 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
 };
 
-/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
+/* struct dpu_ctl_cfg : MDP CTL instance info
  * @id:                index identifying this block
  * @base:              register base offset to mdss
  * @features           bit mask identifying sub-blocks/features
+ * @intr_start:        interrupt index for CTL_START
  */
 struct dpu_ctl_cfg {
 	DPU_HW_BLK_INFO;
+	s32 intr_start;
 };
 
 /**
@@ -526,11 +528,15 @@ struct dpu_dspp_cfg  {
  * @id                 enum identifying this block
  * @base               register offset of this block
  * @features           bit mask identifying sub-blocks/features
+ * @intr_done:         index for PINGPONG done interrupt
+ * @intr_rdptr:        index for PINGPONG readpointer done interrupt
  * @sblk               sub-blocks information
  */
 struct dpu_pingpong_cfg  {
 	DPU_HW_BLK_INFO;
 	u32 merge_3d;
+	s32 intr_done;
+	s32 intr_rdptr;
 	const struct dpu_pingpong_sub_blks *sblk;
 };
 
@@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg  {
  * @type:              Interface type(DSI, DP, HDMI)
  * @controller_id:     Controller Instance ID in case of multiple of intf type
  * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
+ * @intr_underrun:	index for INTF underrun interrupt
+ * @intr_vsync:	        index for INTF VSYNC interrupt
  */
 struct dpu_intf_cfg  {
 	DPU_HW_BLK_INFO;
 	u32 type;   /* interface type*/
 	u32 controller_id;
 	u32 prog_fetch_lines_worst_case;
+	s32 intr_underrun;
+	s32 intr_vsync;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 8bd22e060437..adc1f04ac257 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -196,6 +196,8 @@ struct dpu_irq_type {
 
 /*
  * struct dpu_intr_reg -  List of DPU interrupt registers
+ *
+ * When making changes be sure to sync with dpu_hw_intr_reg
  */
 static const struct dpu_intr_reg dpu_intr_set[] = {
 	{
@@ -265,6 +267,9 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
 	},
 };
 
+#define DPU_IRQ_REG(irq_idx)	(irq_idx / 32)
+#define DPU_IRQ_MASK(irq_idx)	(BIT(irq_idx % 32))
+
 /*
  * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this
  *			 table that have a matching interface type and
@@ -1345,23 +1350,6 @@ static const struct dpu_irq_type dpu_irq_map[] = {
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
 };
 
-static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
-	enum dpu_intr_type intr_type, u32 instance_idx)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
-		if (intr_type == dpu_irq_map[i].intr_type &&
-			instance_idx == dpu_irq_map[i].instance_idx &&
-			!(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
-			return i;
-	}
-
-	pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
-			intr_type, instance_idx);
-	return -EINVAL;
-}
-
 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 		int irq_idx)
 {
@@ -1370,9 +1358,8 @@ static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 	if (!intr)
 		return;
 
-	reg_idx = dpu_irq_map[irq_idx].reg_idx;
-	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
-			dpu_irq_map[irq_idx].irq_mask);
+	reg_idx = DPU_IRQ_REG(irq_idx);
+	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx));
 
 	/* ensure register writes go through */
 	wmb();
@@ -1384,10 +1371,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 {
 	int reg_idx;
 	int irq_idx;
-	int start_idx;
-	int end_idx;
 	u32 irq_status;
 	u32 enable_mask;
+	int bit;
 	unsigned long irq_flags;
 
 	if (!intr)
@@ -1400,15 +1386,7 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 	 */
 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
 	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
-		/*
-		 * Each Interrupt register has a range of 64 indexes, and
-		 * that is static for dpu_irq_map.
-		 */
-		start_idx = reg_idx * 64;
-		end_idx = start_idx + 64;
-
-		if (!test_bit(reg_idx, &intr->irq_mask) ||
-			start_idx >= ARRAY_SIZE(dpu_irq_map))
+		if (!test_bit(reg_idx, &intr->irq_mask))
 			continue;
 
 		/* Read interrupt status */
@@ -1425,37 +1403,33 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
 		/* Finally update IRQ status based on enable mask */
 		irq_status &= enable_mask;
 
+		if (!irq_status)
+			continue;
+
 		/*
-		 * Search through matching intr status from irq map.
-		 * start_idx and end_idx defined the search range in
-		 * the dpu_irq_map.
+		 * Search through matching intr status.
 		 */
-		for (irq_idx = start_idx;
-				(irq_idx < end_idx) && irq_status;
-				irq_idx++)
-			if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
-				(dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
-				!(intr->obsolete_irq &
-				BIT(dpu_irq_map[irq_idx].intr_type))) {
-				/*
-				 * Once a match on irq mask, perform a callback
-				 * to the given cbfunc. cbfunc will take care
-				 * the interrupt status clearing. If cbfunc is
-				 * not provided, then the interrupt clearing
-				 * is here.
-				 */
-				if (cbfunc)
-					cbfunc(arg, irq_idx);
-
-				dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
-
-				/*
-				 * When callback finish, clear the irq_status
-				 * with the matching mask. Once irq_status
-				 * is all cleared, the search can be stopped.
-				 */
-				irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
-			}
+		while ((bit = ffs(irq_status)) != 0) {
+			irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
+			/*
+			 * Once a match on irq mask, perform a callback
+			 * to the given cbfunc. cbfunc will take care
+			 * the interrupt status clearing. If cbfunc is
+			 * not provided, then the interrupt clearing
+			 * is here.
+			 */
+			if (cbfunc)
+				cbfunc(arg, irq_idx);
+
+			dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
+
+			/*
+			 * When callback finish, clear the irq_status
+			 * with the matching mask. Once irq_status
+			 * is all cleared, the search can be stopped.
+			 */
+			irq_status &= ~BIT(bit - 1);
+		}
 	}
 
 	/* ensure register writes go through */
@@ -1469,32 +1443,30 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
 	int reg_idx;
 	unsigned long irq_flags;
 	const struct dpu_intr_reg *reg;
-	const struct dpu_irq_type *irq;
 	const char *dbgstr = NULL;
 	uint32_t cache_irq_mask;
 
 	if (!intr)
 		return -EINVAL;
 
-	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
+	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
 		pr_err("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
 
-	irq = &dpu_irq_map[irq_idx];
-	reg_idx = irq->reg_idx;
+	reg_idx = DPU_IRQ_REG(irq_idx);
 	reg = &dpu_intr_set[reg_idx];
 
 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
-	if (cache_irq_mask & irq->irq_mask) {
+	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
 		dbgstr = "DPU IRQ already set:";
 	} else {
 		dbgstr = "DPU IRQ enabled:";
 
-		cache_irq_mask |= irq->irq_mask;
+		cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
 		/* Cleaning any pending interrupt */
-		DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
+		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
 		/* Enabling interrupts with the new mask */
 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
 
@@ -1505,8 +1477,8 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
 	}
 	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
 
-	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
-			irq->irq_mask, cache_irq_mask);
+	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
+			DPU_IRQ_MASK(irq_idx), cache_irq_mask);
 
 	return 0;
 }
@@ -1515,33 +1487,31 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
 {
 	int reg_idx;
 	const struct dpu_intr_reg *reg;
-	const struct dpu_irq_type *irq;
 	const char *dbgstr = NULL;
 	uint32_t cache_irq_mask;
 
 	if (!intr)
 		return -EINVAL;
 
-	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
+	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
 		pr_err("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
 
-	irq = &dpu_irq_map[irq_idx];
-	reg_idx = irq->reg_idx;
+	reg_idx = DPU_IRQ_REG(irq_idx);
 	reg = &dpu_intr_set[reg_idx];
 
 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
-	if ((cache_irq_mask & irq->irq_mask) == 0) {
+	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
 		dbgstr = "DPU IRQ is already cleared:";
 	} else {
 		dbgstr = "DPU IRQ mask disable:";
 
-		cache_irq_mask &= ~irq->irq_mask;
+		cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
 		/* Disable interrupts based on the new mask */
 		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
 		/* Cleaning any pending interrupt */
-		DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
+		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
 
 		/* ensure register write goes through */
 		wmb();
@@ -1549,8 +1519,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
 		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
 	}
 
-	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
-			irq->irq_mask, cache_irq_mask);
+	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
+			DPU_IRQ_MASK(irq_idx), cache_irq_mask);
 
 	return 0;
 }
@@ -1562,7 +1532,7 @@ static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
 	if (!intr)
 		return -EINVAL;
 
-	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
+	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
 		pr_err("invalid IRQ index: [%d]\n", irq_idx);
 		return -EINVAL;
 	}
@@ -1622,17 +1592,17 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 	if (!intr)
 		return 0;
 
-	if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
+	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
 		pr_err("invalid IRQ index: [%d]\n", irq_idx);
 		return 0;
 	}
 
 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
 
-	reg_idx = dpu_irq_map[irq_idx].reg_idx;
+	reg_idx = DPU_IRQ_REG(irq_idx);
 	intr_status = DPU_REG_READ(&intr->hw,
 			dpu_intr_set[reg_idx].status_off) &
-					dpu_irq_map[irq_idx].irq_mask;
+		DPU_IRQ_MASK(irq_idx);
 	if (intr_status && clear)
 		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
 				intr_status);
@@ -1647,7 +1617,6 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
 
 static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
 {
-	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
 	ops->enable_irq = dpu_hw_intr_enable_irq;
 	ops->disable_irq = dpu_hw_intr_disable_irq;
 	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
@@ -1679,7 +1648,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 	__intr_offset(m, addr, &intr->hw);
 	__setup_intr_ops(&intr->ops);
 
-	intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
+	intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
 
 	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
 			GFP_KERNEL);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index b26a3445a8eb..c6b3d373ce75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -92,23 +92,14 @@ enum dpu_hw_intr_reg {
 	MDP_INTR_MAX,
 };
 
+#define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
+
 struct dpu_hw_intr;
 
 /**
  * Interrupt operations.
  */
 struct dpu_hw_intr_ops {
-	/**
-	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
-	 *                 Used for all irq related ops
-	 * @intr:		HW interrupt handle
-	 * @intr_type:		Interrupt type defined in dpu_intr_type
-	 * @instance_idx:	HW interrupt block instance
-	 * @return:		irq_idx or -EINVAL for lookup fail
-	 */
-	int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
-			enum dpu_intr_type intr_type,
-			u32 instance_idx);
 
 	/**
 	 * enable_irq - Enable IRQ based on lookup IRQ index
@@ -179,7 +170,7 @@ struct dpu_hw_intr_ops {
  * @ops:              function pointer mapping for IRQ handling
  * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
  * @save_irq_status:  array of IRQ status reg storage created during init
- * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
+ * @total_irqs: total number of irq_idx mapped in the hw_interrupts
  * @irq_lock:         spinlock for accessing IRQ resources
  * @obsolete_irq:      irq types that are obsolete for a particular target
  */
@@ -188,7 +179,7 @@ struct dpu_hw_intr {
 	struct dpu_hw_intr_ops ops;
 	u32 *cache_irq_mask;
 	u32 *save_irq_status;
-	u32 irq_idx_tbl_size;
+	u32 total_irqs;
 	spinlock_t irq_lock;
 	unsigned long irq_mask;
 	unsigned long obsolete_irq;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 6714b088970f..e349ea78a49d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -188,24 +188,23 @@ DECLARE_EVENT_CLASS(dpu_enc_irq_template,
 		  __entry->irq_idx)
 );
 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+	TP_ARGS(drm_id, intr_idx, irq_idx)
 );
 DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx),
-	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
+	TP_ARGS(drm_id, intr_idx, irq_idx)
 );
 
 TRACE_EVENT(dpu_enc_irq_wait_success,
-	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
+	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
 		 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
 	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
 	TP_STRUCT__entry(
 		__field(	uint32_t,		drm_id		)
 		__field(	enum dpu_intr_idx,	intr_idx	)
-		__field(	int,			hw_idx		)
 		__field(	int,			irq_idx		)
 		__field(	enum dpu_pingpong,	pp_idx		)
 		__field(	int,			atomic_cnt	)
@@ -213,13 +212,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success,
 	TP_fast_assign(
 		__entry->drm_id = drm_id;
 		__entry->intr_idx = intr_idx;
-		__entry->hw_idx = hw_idx;
 		__entry->irq_idx = irq_idx;
 		__entry->pp_idx = pp_idx;
 		__entry->atomic_cnt = atomic_cnt;
 	),
-	TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
-		  __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
+	TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
+		  __entry->drm_id, __entry->hw_idx,
 		  __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
 );
 
@@ -514,12 +512,12 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
 );
 
 TRACE_EVENT(dpu_enc_wait_event_timeout,
-	TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
+	TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
 		 s64 expected_time, int atomic_cnt),
-	TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
+	TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
 	TP_STRUCT__entry(
 		__field(	uint32_t,	drm_id		)
-		__field(	int32_t,	hw_id		)
+		__field(	int,		irq_idx		)
 		__field(	int,		rc		)
 		__field(	s64,		time		)
 		__field(	s64,		expected_time	)
@@ -527,14 +525,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
 	),
 	TP_fast_assign(
 		__entry->drm_id = drm_id;
-		__entry->hw_id = hw_id;
+		__entry->irq_idx = irq_idx;
 		__entry->rc = rc;
 		__entry->time = time;
 		__entry->expected_time = expected_time;
 		__entry->atomic_cnt = atomic_cnt;
 	),
-	TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
-		  __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
+	TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
+		  __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
 		  __entry->expected_time, __entry->atomic_cnt)
 );
 
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
                   ` (3 preceding siblings ...)
  2021-05-16 20:29 ` [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 21:58   ` [Freedreno] " abhinavk
  2021-05-16 20:29 ` [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling Dmitry Baryshkov
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

There is no more need for the dpu_intr_type types, dpu_irq_map table,
individual intr defines and obsolete_irq field. Drop all of them now.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |    2 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  |    4 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |    2 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |    9 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |    2 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1234 -----------------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |   64 -
 7 files changed, 1317 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 3bd12ce45a80..e7270eb6b84b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -165,7 +165,6 @@ enum dpu_intr_idx {
 /**
  * dpu_encoder_irq - tracking structure for interrupts
  * @name:		string name of interrupt
- * @intr_type:		Encoder interrupt type
  * @intr_idx:		Encoder interrupt enumeration
  * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
  *			will be -EINVAL if IRQ is not registered
@@ -173,7 +172,6 @@ enum dpu_intr_idx {
  */
 struct dpu_encoder_irq {
 	const char *name;
-	enum dpu_intr_type intr_type;
 	enum dpu_intr_idx intr_idx;
 	int irq_idx;
 	struct dpu_irq_callback cb;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 6f06e379b97f..36064004d6ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -789,25 +789,21 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 
 	irq = &phys_enc->irq[INTR_IDX_CTL_START];
 	irq->name = "ctl_start";
-	irq->intr_type = DPU_IRQ_TYPE_CTL_START;
 	irq->intr_idx = INTR_IDX_CTL_START;
 	irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
 
 	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
 	irq->name = "pp_done";
-	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
 	irq->intr_idx = INTR_IDX_PINGPONG;
 	irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
 
 	irq = &phys_enc->irq[INTR_IDX_RDPTR];
 	irq->name = "pp_rd_ptr";
-	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
 	irq->intr_idx = INTR_IDX_RDPTR;
 	irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
 
 	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 	irq->name = "underrun";
-	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
 	irq->intr_idx = INTR_IDX_UNDERRUN;
 	irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 6cdb4ecbc173..4ef3d7357c2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -729,13 +729,11 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 
 	irq = &phys_enc->irq[INTR_IDX_VSYNC];
 	irq->name = "vsync_irq";
-	irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
 	irq->intr_idx = INTR_IDX_VSYNC;
 	irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
 
 	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
 	irq->name = "underrun";
-	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
 	irq->intr_idx = INTR_IDX_UNDERRUN;
 	irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index f929131ed260..d01c4c919504 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -74,13 +74,6 @@
 			 BIT(MDP_INTF0_INTR) | \
 			 BIT(MDP_INTF1_INTR))
 
-#define INTR_SC7180_MASK \
-	(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
-	BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
-	BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\
-	BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
-	BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
-
 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
 			 BIT(MDP_SSPP_TOP0_INTR2) | \
 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -1171,7 +1164,6 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.dma_cfg = sdm845_regdma,
 		.perf = sc7180_perf_data,
 		.mdss_irqs = IRQ_SC7180_MASK,
-		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }
 
@@ -1261,7 +1253,6 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
 		.vbif = sdm845_vbif,
 		.perf = sc7280_perf_data,
 		.mdss_irqs = IRQ_SC7280_MASK,
-		.obsolete_irq = INTR_SC7180_MASK,
 	};
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 316da2971320..7c86fdd14493 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -733,7 +733,6 @@ struct dpu_perf_cfg {
  * @cursor_formats     Supported formats for cursor pipe
  * @vig_formats        Supported formats for vig pipe
  * @mdss_irqs:         Bitmap with the irqs supported by the target
- * @obsolete_irq:       Irq types that are obsolete for a particular target
  */
 struct dpu_mdss_cfg {
 	u32 hwversion;
@@ -780,7 +779,6 @@ struct dpu_mdss_cfg {
 	const struct dpu_format_extended *vig_formats;
 
 	unsigned long mdss_irqs;
-	unsigned long obsolete_irq;
 };
 
 struct dpu_mdss_hw_cfg_handler {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index adc1f04ac257..ef16ba57aac1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -29,145 +29,6 @@
 #define MDP_INTF_1_OFF_REV_7xxx             0x35000
 #define MDP_INTF_5_OFF_REV_7xxx             0x39000
 
-/**
- * WB interrupt status bit definitions
- */
-#define DPU_INTR_WB_0_DONE BIT(0)
-#define DPU_INTR_WB_1_DONE BIT(1)
-#define DPU_INTR_WB_2_DONE BIT(4)
-
-/**
- * WDOG timer interrupt status bit definitions
- */
-#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
-#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
-#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
-#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
-#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
-
-/**
- * Pingpong interrupt status bit definitions
- */
-#define DPU_INTR_PING_PONG_0_DONE BIT(8)
-#define DPU_INTR_PING_PONG_1_DONE BIT(9)
-#define DPU_INTR_PING_PONG_2_DONE BIT(10)
-#define DPU_INTR_PING_PONG_3_DONE BIT(11)
-#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
-#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
-#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
-#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
-#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
-#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
-#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
-#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
-#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
-#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
-#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
-#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
-
-/**
- * Interface interrupt status bit definitions
- */
-#define DPU_INTR_INTF_0_UNDERRUN BIT(24)
-#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
-#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
-#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
-#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
-#define DPU_INTR_INTF_0_VSYNC BIT(25)
-#define DPU_INTR_INTF_1_VSYNC BIT(27)
-#define DPU_INTR_INTF_2_VSYNC BIT(29)
-#define DPU_INTR_INTF_3_VSYNC BIT(31)
-#define DPU_INTR_INTF_5_VSYNC BIT(23)
-
-/**
- * Pingpong Secondary interrupt status bit definitions
- */
-#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
-#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4)
-#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8)
-#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
-#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
-
-/**
- * Pingpong TEAR detection interrupt status bit definitions
- */
-#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
-#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
-#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
-#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
-
-/**
- * Pingpong TE detection interrupt status bit definitions
- */
-#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24)
-#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25)
-#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26)
-#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27)
-
-/**
- * Ctl start interrupt status bit definitions
- */
-#define DPU_INTR_CTL_0_START BIT(9)
-#define DPU_INTR_CTL_1_START BIT(10)
-#define DPU_INTR_CTL_2_START BIT(11)
-#define DPU_INTR_CTL_3_START BIT(12)
-#define DPU_INTR_CTL_4_START BIT(13)
-
-/**
- * Concurrent WB overflow interrupt status bit definitions
- */
-#define DPU_INTR_CWB_2_OVERFLOW BIT(14)
-#define DPU_INTR_CWB_3_OVERFLOW BIT(15)
-
-/**
- * Histogram VIG done interrupt status bit definitions
- */
-#define DPU_INTR_HIST_VIG_0_DONE BIT(0)
-#define DPU_INTR_HIST_VIG_1_DONE BIT(4)
-#define DPU_INTR_HIST_VIG_2_DONE BIT(8)
-#define DPU_INTR_HIST_VIG_3_DONE BIT(10)
-
-/**
- * Histogram VIG reset Sequence done interrupt status bit definitions
- */
-#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
-#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
-#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
-#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
-
-/**
- * Histogram DSPP done interrupt status bit definitions
- */
-#define DPU_INTR_HIST_DSPP_0_DONE BIT(12)
-#define DPU_INTR_HIST_DSPP_1_DONE BIT(16)
-#define DPU_INTR_HIST_DSPP_2_DONE BIT(20)
-#define DPU_INTR_HIST_DSPP_3_DONE BIT(22)
-
-/**
- * Histogram DSPP reset Sequence done interrupt status bit definitions
- */
-#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
-#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
-#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
-#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
-
-/**
- * INTF interrupt status bit definitions
- */
-#define DPU_INTR_VIDEO_INTO_STATIC BIT(0)
-#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1)
-#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2)
-#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
-#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4)
-#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
-#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6)
-#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
-#define DPU_INTR_PROG_LINE BIT(8)
-
-/**
- * AD4 interrupt status bit definitions
- */
-#define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
 /**
  * struct dpu_intr_reg - array of DPU register sets
  * @clr_off:	offset to CLEAR reg
@@ -180,20 +41,6 @@ struct dpu_intr_reg {
 	u32 status_off;
 };
 
-/**
- * struct dpu_irq_type - maps each irq with i/f
- * @intr_type:		type of interrupt listed in dpu_intr_type
- * @instance_idx:	instance index of the associated HW block in DPU
- * @irq_mask:		corresponding bit in the interrupt status reg
- * @reg_idx:		which reg set to use
- */
-struct dpu_irq_type {
-	u32 intr_type;
-	u32 instance_idx;
-	u32 irq_mask;
-	u32 reg_idx;
-};
-
 /*
  * struct dpu_intr_reg -  List of DPU interrupt registers
  *
@@ -270,1086 +117,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
 #define DPU_IRQ_REG(irq_idx)	(irq_idx / 32)
 #define DPU_IRQ_MASK(irq_idx)	(BIT(irq_idx % 32))
 
-/*
- * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this
- *			 table that have a matching interface type and
- *			 instance index.
- */
-static const struct dpu_irq_type dpu_irq_map[] = {
-	/* BEGIN MAP_RANGE: 0-31, INTR */
-	/* irq_idx: 0-3 */
-	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0},
-	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0},
-	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0},
-	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0},
-	/* irq_idx: 4-7 */
-	{ DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0},
-	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0},
-	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0},
-	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0},
-	/* irq_idx: 8-11 */
-	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_DONE, 0},
-	/* irq_idx: 12-15 */
-	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_RD_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_RD_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_RD_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_RD_PTR, 0},
-	/* irq_idx: 16-19 */
-	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_WR_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_WR_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_WR_PTR, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_WR_PTR, 0},
-	/* irq_idx: 20-23 */
-	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
-	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
-	/* irq_idx: 24-27 */
-	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0},
-	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},
-	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0},
-	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0},
-	/* irq_idx: 28-31 */
-	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0},
-	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
-	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
-	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
-	/* irq_idx:32-33 */
-	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
-	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
-	/* irq_idx:34-63 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-	/* BEGIN MAP_RANGE: 64-95, INTR2 */
-	/* irq_idx: 64-67 */
-	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
-		DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	/* irq_idx: 68-71 */
-	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
-		DPU_INTR_PING_PONG_S0_WR_PTR, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	/* irq_idx: 72 */
-	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
-		DPU_INTR_PING_PONG_S0_RD_PTR, 1},
-	/* irq_idx: 73-77 */
-	{ DPU_IRQ_TYPE_CTL_START, CTL_0,
-		DPU_INTR_CTL_0_START, 1},
-	{ DPU_IRQ_TYPE_CTL_START, CTL_1,
-		DPU_INTR_CTL_1_START, 1},
-	{ DPU_IRQ_TYPE_CTL_START, CTL_2,
-		DPU_INTR_CTL_2_START, 1},
-	{ DPU_IRQ_TYPE_CTL_START, CTL_3,
-		DPU_INTR_CTL_3_START, 1},
-	{ DPU_IRQ_TYPE_CTL_START, CTL_4,
-		DPU_INTR_CTL_4_START, 1},
-	/* irq_idx: 78-79 */
-	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
-	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
-	/* irq_idx: 80-83 */
-	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
-	/* irq_idx: 84-87 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
-		DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	/* irq_idx: 88-91 */
-	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
-		DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
-		DPU_INTR_PING_PONG_1_TE_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
-		DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
-	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
-		DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
-	/* irq_idx: 92-95 */
-	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
-		DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	/* irq_idx: 96-127 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-	/* BEGIN MAP_RANGE: 128-159 HIST */
-	/* irq_idx: 128-131 */
-	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
-		DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 132-135 */
-	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
-		DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 136-139 */
-	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
-		DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
-		DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
-	/* irq_idx: 140-143 */
-	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
-		DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 144-147 */
-	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
-		DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 148-151 */
-	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
-		DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
-	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
-		DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
-	/* irq_idx: 152-155 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 156-159 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* irq_idx: 160-191 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-	/* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
-	/* irq_idx: 192-195 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
-		DPU_INTR_VIDEO_INTO_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
-	/* irq_idx: 196-199 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 3},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
-	/* irq_idx: 200-203 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 204-207 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 208-211 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 212-215 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 216-219 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 220-223 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* irq_idx: 224-255 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-	/* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
-	/* irq_idx: 256-259 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
-		DPU_INTR_VIDEO_INTO_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
-	/* irq_idx: 260-263 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 4},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
-	/* irq_idx: 264-267 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 268-271 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 272-275 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 276-279 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 280-283 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 284-287 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* irq_idx: 288-319 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-	/* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
-	/* irq_idx: 320-323 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
-		DPU_INTR_VIDEO_INTO_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
-	/* irq_idx: 324-327 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 5},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
-	/* irq_idx: 328-331 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 332-335 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 336-339 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 340-343 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 344-347 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 348-351 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* irq_idx: 352-383 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-	/* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
-	/* irq_idx: 384-387 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
-		DPU_INTR_VIDEO_INTO_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
-	/* irq_idx: 388-391 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 6},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
-	/* irq_idx: 392-395 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 396-399 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 400-403 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 404-407 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 408-411 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 412-415 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* irq_idx: 416-447*/
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-	/* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
-	/* irq_idx: 448-451 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
-		DPU_INTR_VIDEO_INTO_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
-	/* irq_idx: 452-455 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 7},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
-	/* irq_idx: 456-459 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 460-463 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 464-467 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 468-471 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 472-475 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 476-479 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* irq_idx: 480-511 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-	/* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
-	/* irq_idx: 512-515 */
-	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 516-519 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 520-523 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 524-527 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 528-531 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 532-535 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 536-539 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 540-543 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* irq_idx: 544-575*/
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-	/* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
-	/* irq_idx: 576-579 */
-	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 580-583 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 584-587 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 588-591 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 592-595 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 596-599 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 600-603 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 604-607 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* irq_idx: 608-639 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
-	/* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
-	/* irq_idx: 640-643 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
-		DPU_INTR_VIDEO_INTO_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
-	/* irq_idx: 644-647 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 10},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
-	/* irq_idx: 648-651 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 652-655 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 656-659 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 660-663 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 664-667 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 668-671 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* irq_idx: 672-703 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
-	/* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
-	/* irq_idx: 704-707 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
-		DPU_INTR_VIDEO_INTO_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
-	/* irq_idx: 708-711 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 11},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
-	/* irq_idx: 712-715 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 716-719 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 720-723 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 724-727 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 728-731 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 732-735 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* irq_idx: 736-767 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
-	/* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
-	/* irq_idx: 768-771 */
-	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
-		DPU_INTR_VIDEO_INTO_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
-		DPU_INTR_VIDEO_OUTOF_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
-		DPU_INTR_DSICMD_0_INTO_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
-		DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
-	/* irq_idx: 772-775 */
-	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
-		DPU_INTR_DSICMD_1_INTO_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
-		DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
-		DPU_INTR_DSICMD_2_INTO_STATIC, 12},
-	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
-		DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
-	/* irq_idx: 776-779 */
-	{ DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 780-783 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 784-787 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 788-791 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 792-795 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 796-799 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	/* irq_idx: 800-831 */
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
-};
-
 static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
 		int irq_idx)
 {
@@ -1658,7 +425,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 	}
 
 	intr->irq_mask = m->mdss_irqs;
-	intr->obsolete_irq = m->obsolete_irq;
 
 	spin_lock_init(&intr->irq_lock);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index c6b3d373ce75..3c8b788d78e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -12,68 +12,6 @@
 #include "dpu_hw_util.h"
 #include "dpu_hw_mdss.h"
 
-/**
- * dpu_intr_type - HW Interrupt Type
- * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
- * @DPU_IRQ_TYPE_WB_WFD_COMP:		WB WFD done
- * @DPU_IRQ_TYPE_PING_PONG_COMP:	PingPong done
- * @DPU_IRQ_TYPE_PING_PONG_RD_PTR:	PingPong read pointer
- * @DPU_IRQ_TYPE_PING_PONG_WR_PTR:	PingPong write pointer
- * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF:	PingPong auto refresh
- * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK:	PingPong Tear check
- * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK:	PingPong TE detection
- * @DPU_IRQ_TYPE_INTF_UNDER_RUN:	INTF underrun
- * @DPU_IRQ_TYPE_INTF_VSYNC:		INTF VSYNC
- * @DPU_IRQ_TYPE_CWB_OVERFLOW:		Concurrent WB overflow
- * @DPU_IRQ_TYPE_HIST_VIG_DONE:		VIG Histogram done
- * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ:	VIG Histogram reset
- * @DPU_IRQ_TYPE_HIST_DSPP_DONE:	DSPP Histogram done
- * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ:	DSPP Histogram reset
- * @DPU_IRQ_TYPE_WD_TIMER:		Watchdog timer
- * @DPU_IRQ_TYPE_SFI_VIDEO_IN:		Video static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_VIDEO_OUT:		Video static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_0_IN:		DSI CMD0 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_0_OUT:		DSI CMD0 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_1_IN:		DSI CMD1 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_1_OUT:		DSI CMD1 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_2_IN:		DSI CMD2 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_2_OUT:		DSI CMD2 static frame INTR out-of static
- * @DPU_IRQ_TYPE_PROG_LINE:		Programmable Line interrupt
- * @DPU_IRQ_TYPE_AD4_BL_DONE:		AD4 backlight
- * @DPU_IRQ_TYPE_CTL_START:		Control start
- * @DPU_IRQ_TYPE_RESERVED:		Reserved for expansion
- */
-enum dpu_intr_type {
-	DPU_IRQ_TYPE_WB_ROT_COMP,
-	DPU_IRQ_TYPE_WB_WFD_COMP,
-	DPU_IRQ_TYPE_PING_PONG_COMP,
-	DPU_IRQ_TYPE_PING_PONG_RD_PTR,
-	DPU_IRQ_TYPE_PING_PONG_WR_PTR,
-	DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
-	DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
-	DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
-	DPU_IRQ_TYPE_INTF_UNDER_RUN,
-	DPU_IRQ_TYPE_INTF_VSYNC,
-	DPU_IRQ_TYPE_CWB_OVERFLOW,
-	DPU_IRQ_TYPE_HIST_VIG_DONE,
-	DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
-	DPU_IRQ_TYPE_HIST_DSPP_DONE,
-	DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
-	DPU_IRQ_TYPE_WD_TIMER,
-	DPU_IRQ_TYPE_SFI_VIDEO_IN,
-	DPU_IRQ_TYPE_SFI_VIDEO_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_0_IN,
-	DPU_IRQ_TYPE_SFI_CMD_0_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_1_IN,
-	DPU_IRQ_TYPE_SFI_CMD_1_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_2_IN,
-	DPU_IRQ_TYPE_SFI_CMD_2_OUT,
-	DPU_IRQ_TYPE_PROG_LINE,
-	DPU_IRQ_TYPE_AD4_BL_DONE,
-	DPU_IRQ_TYPE_CTL_START,
-	DPU_IRQ_TYPE_RESERVED,
-};
-
 /* When making changes be sure to sync with dpu_intr_set */
 enum dpu_hw_intr_reg {
 	MDP_SSPP_TOP0_INTR,
@@ -172,7 +110,6 @@ struct dpu_hw_intr_ops {
  * @save_irq_status:  array of IRQ status reg storage created during init
  * @total_irqs: total number of irq_idx mapped in the hw_interrupts
  * @irq_lock:         spinlock for accessing IRQ resources
- * @obsolete_irq:      irq types that are obsolete for a particular target
  */
 struct dpu_hw_intr {
 	struct dpu_hw_blk_reg_map hw;
@@ -182,7 +119,6 @@ struct dpu_hw_intr {
 	u32 total_irqs;
 	spinlock_t irq_lock;
 	unsigned long irq_mask;
-	unsigned long obsolete_irq;
 };
 
 /**
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling
  2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
                   ` (4 preceding siblings ...)
  2021-05-16 20:29 ` [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem Dmitry Baryshkov
@ 2021-05-16 20:29 ` Dmitry Baryshkov
  2021-05-24 22:13   ` [Freedreno] " abhinavk
  5 siblings, 1 reply; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-16 20:29 UTC (permalink / raw)
  To: Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar
  Cc: Jonathan Marek, Stephen Boyd, David Airlie, Daniel Vetter,
	linux-arm-msm, dri-devel, freedreno

Merge dpu_core_irq_enable() into dpu_core_irq_register_callback() and
dpu_core_irq_disable() into dpu_core_irq_unregister_callback(), because
they are called in pairs. There is no need to have separate
enable/disable pair, we can enable hardware IRQ when first callback is
registered and when the last callback is unregistered.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 168 +++----------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h |  30 ----
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  |  18 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h      |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h    |   8 -
 5 files changed, 27 insertions(+), 199 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
index 11c0abed21ee..4f110c428b60 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
@@ -26,10 +26,8 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 
 	pr_debug("irq_idx=%d\n", irq_idx);
 
-	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
-		DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
-			atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
-	}
+	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
+		DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
 
 	atomic_inc(&irq_obj->irq_counts[irq_idx]);
 
@@ -43,127 +41,6 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
 	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
 }
 
-/**
- * _dpu_core_irq_enable - enable core interrupt given by the index
- * @dpu_kms:		Pointer to dpu kms context
- * @irq_idx:		interrupt index
- */
-static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
-{
-	unsigned long irq_flags;
-	int ret = 0, enable_count;
-
-	if (!dpu_kms->hw_intr ||
-			!dpu_kms->irq_obj.enable_counts ||
-			!dpu_kms->irq_obj.irq_counts) {
-		DPU_ERROR("invalid params\n");
-		return -EINVAL;
-	}
-
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
-		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
-		return -EINVAL;
-	}
-
-	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
-	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
-	trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
-
-	if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) {
-		ret = dpu_kms->hw_intr->ops.enable_irq(
-				dpu_kms->hw_intr,
-				irq_idx);
-		if (ret)
-			DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
-					irq_idx);
-
-		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
-
-		spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
-		/* empty callback list but interrupt is enabled */
-		if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]))
-			DPU_ERROR("irq_idx=%d enabled with no callback\n",
-					irq_idx);
-		spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
-	}
-
-	return ret;
-}
-
-int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
-{
-	int i, ret = 0, counts;
-
-	if (!irq_idxs || !irq_count) {
-		DPU_ERROR("invalid params\n");
-		return -EINVAL;
-	}
-
-	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
-	if (counts)
-		DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
-
-	for (i = 0; (i < irq_count) && !ret; i++)
-		ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
-
-	return ret;
-}
-
-/**
- * _dpu_core_irq_disable - disable core interrupt given by the index
- * @dpu_kms:		Pointer to dpu kms context
- * @irq_idx:		interrupt index
- */
-static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
-{
-	int ret = 0, enable_count;
-
-	if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
-		DPU_ERROR("invalid params\n");
-		return -EINVAL;
-	}
-
-	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
-		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
-		return -EINVAL;
-	}
-
-	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
-	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
-	trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
-
-	if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) {
-		ret = dpu_kms->hw_intr->ops.disable_irq(
-				dpu_kms->hw_intr,
-				irq_idx);
-		if (ret)
-			DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
-					irq_idx);
-		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
-	}
-
-	return ret;
-}
-
-int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count)
-{
-	int i, ret = 0, counts;
-
-	if (!irq_idxs || !irq_count) {
-		DPU_ERROR("invalid params\n");
-		return -EINVAL;
-	}
-
-	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
-	if (counts == 2)
-		DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
-
-	for (i = 0; (i < irq_count) && !ret; i++)
-		ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
-
-	return ret;
-}
-
 u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
 {
 	if (!dpu_kms->hw_intr ||
@@ -210,6 +87,16 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx,
 	list_del_init(&register_irq_cb->list);
 	list_add_tail(&register_irq_cb->list,
 			&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
+	if (list_is_first(&register_irq_cb->list,
+			&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
+		int ret = dpu_kms->hw_intr->ops.enable_irq(
+				dpu_kms->hw_intr,
+				irq_idx);
+		if (ret)
+			DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
+					irq_idx);
+	}
+
 	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
 
 	return 0;
@@ -244,9 +131,15 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
 	trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
 	list_del_init(&register_irq_cb->list);
 	/* empty callback list but interrupt is still enabled */
-	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
-			atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]))
-		DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);
+	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
+		int ret = dpu_kms->hw_intr->ops.disable_irq(
+				dpu_kms->hw_intr,
+				irq_idx);
+		if (ret)
+			DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
+					irq_idx);
+		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
+	}
 	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
 
 	return 0;
@@ -274,23 +167,22 @@ static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
 	struct dpu_irq *irq_obj = s->private;
 	struct dpu_irq_callback *cb;
 	unsigned long irq_flags;
-	int i, irq_count, enable_count, cb_count;
+	int i, irq_count, cb_count;
 
-	if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl))
+	if (WARN_ON(!irq_obj->irq_cb_tbl))
 		return 0;
 
 	for (i = 0; i < irq_obj->total_irqs; i++) {
 		spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
 		cb_count = 0;
 		irq_count = atomic_read(&irq_obj->irq_counts[i]);
-		enable_count = atomic_read(&irq_obj->enable_counts[i]);
 		list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
 			cb_count++;
 		spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
 
-		if (irq_count || enable_count || cb_count)
-			seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",
-					i, irq_count, enable_count, cb_count);
+		if (irq_count || cb_count)
+			seq_printf(s, "idx:%d irq:%d cb:%d\n",
+					i, irq_count, cb_count);
 	}
 
 	return 0;
@@ -321,13 +213,10 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
 	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
 	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
 			sizeof(struct list_head), GFP_KERNEL);
-	dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
-			sizeof(atomic_t), GFP_KERNEL);
 	dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
 			sizeof(atomic_t), GFP_KERNEL);
 	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {
 		INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);
-		atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0);
 		atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);
 	}
 }
@@ -338,8 +227,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
 
 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
 	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
-		if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) ||
-				!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
+		if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
 			DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
 
 	dpu_clear_all_irqs(dpu_kms);
@@ -347,10 +235,8 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms)
 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
 	kfree(dpu_kms->irq_obj.irq_cb_tbl);
-	kfree(dpu_kms->irq_obj.enable_counts);
 	kfree(dpu_kms->irq_obj.irq_counts);
 	dpu_kms->irq_obj.irq_cb_tbl = NULL;
-	dpu_kms->irq_obj.enable_counts = NULL;
 	dpu_kms->irq_obj.irq_counts = NULL;
 	dpu_kms->irq_obj.total_irqs = 0;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
index d147784d5531..90ae6c9ccc95 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
@@ -29,36 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms);
  */
 irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
 
-/**
- * dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs
- * @dpu_kms:		DPU handle
- * @irq_idxs:		Array of irq index
- * @irq_count:		Number of irq_idx provided in the array
- * @return:		0 for success enabling IRQ, otherwise failure
- *
- * This function increments count on each enable and decrements on each
- * disable.  Interrupts is enabled if count is 0 before increment.
- */
-int dpu_core_irq_enable(
-		struct dpu_kms *dpu_kms,
-		int *irq_idxs,
-		uint32_t irq_count);
-
-/**
- * dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs
- * @dpu_kms:		DPU handle
- * @irq_idxs:		Array of irq index
- * @irq_count:		Number of irq_idx provided in the array
- * @return:		0 for success disabling IRQ, otherwise failure
- *
- * This function increments count on each enable and decrements on each
- * disable.  Interrupts is disabled if count is 0 after decrement.
- */
-int dpu_core_irq_disable(
-		struct dpu_kms *dpu_kms,
-		int *irq_idxs,
-		uint32_t irq_count);
-
 /**
  * dpu_core_irq_read - IRQ helper function for reading IRQ status
  * @dpu_kms:		DPU handle
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 8a9d01e3b664..18c410433bb4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -360,17 +360,6 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 		return ret;
 	}
 
-	ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
-	if (ret) {
-		DRM_ERROR("enable failed id=%u, intr=%d, irq=%d",
-			  DRMID(phys_enc->parent), intr_idx,
-			  irq->irq_idx);
-		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
-				irq->irq_idx, &irq->cb);
-		irq->irq_idx = -EINVAL;
-		return ret;
-	}
-
 	trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 				irq->irq_idx);
 
@@ -393,13 +382,6 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 		return 0;
 	}
 
-	ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
-	if (ret) {
-		DRM_ERROR("disable failed id=%u, intr=%d, irq=%d ret=%d",
-			  DRMID(phys_enc->parent), intr_idx,
-			  irq->irq_idx, ret);
-	}
-
 	ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 			&irq->cb);
 	if (ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index d6717d6672f7..f6840b1af6e4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -82,14 +82,12 @@ struct dpu_irq_callback {
  * struct dpu_irq: IRQ structure contains callback registration info
  * @total_irq:    total number of irq_idx obtained from HW interrupts mapping
  * @irq_cb_tbl:   array of IRQ callbacks setting
- * @enable_counts array of IRQ enable counts
  * @cb_lock:      callback lock
  * @debugfs_file: debugfs file for irq statistics
  */
 struct dpu_irq {
 	u32 total_irqs;
 	struct list_head *irq_cb_tbl;
-	atomic_t *enable_counts;
 	atomic_t *irq_counts;
 	spinlock_t cb_lock;
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index e349ea78a49d..00b43959f631 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -891,14 +891,6 @@ DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
 	TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
 		  __entry->enable_count)
 );
-DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
-	TP_PROTO(int irq_idx, int enable_count),
-	TP_ARGS(irq_idx, enable_count)
-);
-DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
-	TP_PROTO(int irq_idx, int enable_count),
-	TP_ARGS(irq_idx, enable_count)
-);
 
 DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
 	TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
-- 
2.30.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs
  2021-05-16 20:29 ` [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs Dmitry Baryshkov
@ 2021-05-24 21:44   ` abhinavk
  0 siblings, 0 replies; 14+ messages in thread
From: abhinavk @ 2021-05-24 21:44 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> There is little sense in reading interrupt statuses and right after 
> that
> going after the array of statuses to dispatch them. Merge both loops
> into single function doing read and dispatch.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  | 10 +--
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 66 ++++++-------------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  8 ---
>  3 files changed, 20 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index cdec3fbe6ff4..54b34746a587 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -376,15 +376,6 @@ void dpu_core_irq_uninstall(struct dpu_kms 
> *dpu_kms)
> 
>  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
>  {
> -	/*
> -	 * Read interrupt status from all sources. Interrupt status are
> -	 * stored within hw_intr.
> -	 * Function will also clear the interrupt status after reading.
> -	 * Individual interrupt status bit will only get stored if it
> -	 * is enabled.
> -	 */
> -	dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr);
> -
>  	/*
>  	 * Dispatch to HW driver to handle interrupt lookup that is being
>  	 * fired. When matching interrupt is located, HW driver will call to
> @@ -392,6 +383,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
>  	 * dpu_core_irq_callback_handler will perform the registered function
>  	 * callback, and do the interrupt status clearing once the registered
>  	 * callback is finished.
> +	 * Function will also clear the interrupt status after reading.
>  	 */
>  	dpu_kms->hw_intr->ops.dispatch_irqs(
>  			dpu_kms->hw_intr,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 48c96b812126..cf9bfd45aa59 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -1371,6 +1371,7 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  	int start_idx;
>  	int end_idx;
>  	u32 irq_status;
> +	u32 enable_mask;
>  	unsigned long irq_flags;
> 
>  	if (!intr)
> @@ -1383,8 +1384,6 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  	 */
>  	spin_lock_irqsave(&intr->irq_lock, irq_flags);
>  	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> -		irq_status = intr->save_irq_status[reg_idx];
> -
>  		/*
>  		 * Each Interrupt register has a range of 64 indexes, and
>  		 * that is static for dpu_irq_map.
> @@ -1396,6 +1395,20 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  			start_idx >= ARRAY_SIZE(dpu_irq_map))
>  			continue;
> 
> +		/* Read interrupt status */
> +		irq_status = DPU_REG_READ(&intr->hw, 
> dpu_intr_set[reg_idx].status_off);
> +
> +		/* Read enable mask */
> +		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> +
> +		/* and clear the interrupt */
> +		if (irq_status)
> +			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +				     irq_status);
> +
> +		/* Finally update IRQ status based on enable mask */
> +		irq_status &= enable_mask;
> +
>  		/*
>  		 * Search through matching intr status from irq map.
>  		 * start_idx and end_idx defined the search range in
> @@ -1429,6 +1442,10 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  				irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
>  			}
>  	}
> +
> +	/* ensure register writes go through */
> +	wmb();
> +
>  	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
>  }
> 
> @@ -1580,41 +1597,6 @@ static int dpu_hw_intr_disable_irqs(struct
> dpu_hw_intr *intr)
>  	return 0;
>  }
> 
> -static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr 
> *intr)
> -{
> -	int i;
> -	u32 enable_mask;
> -	unsigned long irq_flags;
> -
> -	if (!intr)
> -		return;
> -
> -	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> -		if (!test_bit(i, &intr->irq_mask))
> -			continue;
> -
> -		/* Read interrupt status */
> -		intr->save_irq_status[i] = DPU_REG_READ(&intr->hw,
> -				dpu_intr_set[i].status_off);
> -
> -		/* Read enable mask */
> -		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off);
> -
> -		/* and clear the interrupt */
> -		if (intr->save_irq_status[i])
> -			DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off,
> -					intr->save_irq_status[i]);
> -
> -		/* Finally update IRQ status based on enable mask */
> -		intr->save_irq_status[i] &= enable_mask;
> -	}
> -
> -	/* ensure register writes go through */
> -	wmb();
> -
> -	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
> -}
> 
>  static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
> *intr,
>  		int irq_idx)
> @@ -1673,7 +1655,6 @@ static void __setup_intr_ops(struct 
> dpu_hw_intr_ops *ops)
>  	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
>  	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
>  	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
> -	ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses;
>  	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
>  	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
>  }
> @@ -1710,14 +1691,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void 
> __iomem *addr,
>  		return ERR_PTR(-ENOMEM);
>  	}
> 
> -	intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), 
> sizeof(u32),
> -			GFP_KERNEL);
> -	if (intr->save_irq_status == NULL) {
> -		kfree(intr->cache_irq_mask);
> -		kfree(intr);
> -		return ERR_PTR(-ENOMEM);
> -	}
> -
>  	intr->irq_mask = m->mdss_irqs;
>  	intr->obsolete_irq = m->obsolete_irq;
> 
> @@ -1730,7 +1703,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr 
> *intr)
>  {
>  	if (intr) {
>  		kfree(intr->cache_irq_mask);
> -		kfree(intr->save_irq_status);
>  		kfree(intr);
>  	}
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 5d6f9a7a5195..5a1c304ba93f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -142,14 +142,6 @@ struct dpu_hw_intr_ops {
>  			void (*cbfunc)(void *arg, int irq_idx),
>  			void *arg);
> 
> -	/**
> -	 * get_interrupt_statuses - Gets and store value from all interrupt
> -	 *                          status registers that are currently 
> fired.
> -	 * @intr:	HW interrupt handle
> -	 */
> -	void (*get_interrupt_statuses)(
> -			struct dpu_hw_intr *intr);
> -
>  	/**
>  	 * clear_intr_status_nolock() - clears the HW interrupts without lock
>  	 * @intr:	HW interrupt handle

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock
  2021-05-16 20:29 ` [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock Dmitry Baryshkov
@ 2021-05-24 21:46   ` abhinavk
  0 siblings, 0 replies; 14+ messages in thread
From: abhinavk @ 2021-05-24 21:46 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> Always call dpu_hw_intr_clear_intr_status_nolock() from the
> dpu_hw_intr_dispatch_irqs(). This simplifies the callback function
> (which call clears the interrupts anyway) and enforces clearing the hw
> interrupt status.
> 
In the subject line you can remove the "hw_intr:"

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
With that nit fixed,
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  9 -----
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 39 +++++++++----------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  9 -----
>  3 files changed, 18 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index 54b34746a587..fd11a2aeab6c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -41,15 +41,6 @@ static void dpu_core_irq_callback_handler(void
> *arg, int irq_idx)
>  		if (cb->func)
>  			cb->func(cb->arg, irq_idx);
>  	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
> -
> -	/*
> -	 * Clear pending interrupt status in HW.
> -	 * NOTE: dpu_core_irq_callback_handler is protected by top-level
> -	 *       spinlock, so it is safe to clear any interrupt status here.
> -	 */
> -	dpu_kms->hw_intr->ops.clear_intr_status_nolock(
> -			dpu_kms->hw_intr,
> -			irq_idx);
>  }
> 
>  int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index cf9bfd45aa59..8bd22e060437 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -1362,6 +1362,22 @@ static int dpu_hw_intr_irqidx_lookup(struct
> dpu_hw_intr *intr,
>  	return -EINVAL;
>  }
> 
> +static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
> *intr,
> +		int irq_idx)
> +{
> +	int reg_idx;
> +
> +	if (!intr)
> +		return;
> +
> +	reg_idx = dpu_irq_map[irq_idx].reg_idx;
> +	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +			dpu_irq_map[irq_idx].irq_mask);
> +
> +	/* ensure register writes go through */
> +	wmb();
> +}
> +
>  static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
>  		void (*cbfunc)(void *, int),
>  		void *arg)
> @@ -1430,9 +1446,8 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  				 */
>  				if (cbfunc)
>  					cbfunc(arg, irq_idx);
> -				else
> -					intr->ops.clear_intr_status_nolock(
> -							intr, irq_idx);
> +
> +				dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> 
>  				/*
>  				 * When callback finish, clear the irq_status
> @@ -1597,23 +1612,6 @@ static int dpu_hw_intr_disable_irqs(struct
> dpu_hw_intr *intr)
>  	return 0;
>  }
> 
> -
> -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
> *intr,
> -		int irq_idx)
> -{
> -	int reg_idx;
> -
> -	if (!intr)
> -		return;
> -
> -	reg_idx = dpu_irq_map[irq_idx].reg_idx;
> -	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> -			dpu_irq_map[irq_idx].irq_mask);
> -
> -	/* ensure register writes go through */
> -	wmb();
> -}
> -
>  static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>  		int irq_idx, bool clear)
>  {
> @@ -1655,7 +1653,6 @@ static void __setup_intr_ops(struct 
> dpu_hw_intr_ops *ops)
>  	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
>  	ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
>  	ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
> -	ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock;
>  	ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
>  }
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 5a1c304ba93f..5bade5637ecc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -142,15 +142,6 @@ struct dpu_hw_intr_ops {
>  			void (*cbfunc)(void *arg, int irq_idx),
>  			void *arg);
> 
> -	/**
> -	 * clear_intr_status_nolock() - clears the HW interrupts without lock
> -	 * @intr:	HW interrupt handle
> -	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
> -	 */
> -	void (*clear_intr_status_nolock)(
> -			struct dpu_hw_intr *intr,
> -			int irq_idx);
> -
>  	/**
>  	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
>  	 *                        based on given lookup IRQ index.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: define interrupt register names
  2021-05-16 20:29 ` [PATCH v2 3/6] drm/msm/dpu: define interrupt register names Dmitry Baryshkov
@ 2021-05-24 21:51   ` abhinavk
  0 siblings, 0 replies; 14+ messages in thread
From: abhinavk @ 2021-05-24 21:51 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> In order to make mdss_irqs readable (and error-prone) define names for
I think you meant "less error-prone" here.
> interrupt register indices.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
With that nit fixed,
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 45 ++++++++++++++++---
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 18 ++++++++
>  2 files changed, 58 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index b569030a0847..9a77d64d3fd4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -7,6 +7,7 @@
>  #include <linux/of_address.h>
>  #include <linux/platform_device.h>
>  #include "dpu_hw_mdss.h"
> +#include "dpu_hw_interrupts.h"
>  #include "dpu_hw_catalog.h"
>  #include "dpu_kms.h"
> 
> @@ -56,6 +57,23 @@
> 
>  #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
> 
> +#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> +			 BIT(MDP_SSPP_TOP0_INTR2) | \
> +			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> +			 BIT(MDP_INTF0_INTR) | \
> +			 BIT(MDP_INTF1_INTR) | \
> +			 BIT(MDP_INTF2_INTR) | \
> +			 BIT(MDP_INTF3_INTR) | \
> +			 BIT(MDP_INTF4_INTR) | \
> +			 BIT(MDP_AD4_0_INTR) | \
> +			 BIT(MDP_AD4_1_INTR))
> +
> +#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> +			 BIT(MDP_SSPP_TOP0_INTR2) | \
> +			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> +			 BIT(MDP_INTF0_INTR) | \
> +			 BIT(MDP_INTF1_INTR))
> +
>  #define INTR_SC7180_MASK \
>  	(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
>  	BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> @@ -63,6 +81,23 @@
>  	BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
>  	BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
> 
> +#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> +			 BIT(MDP_SSPP_TOP0_INTR2) | \
> +			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> +			 BIT(MDP_INTF0_7xxx_INTR) | \
> +			 BIT(MDP_INTF1_7xxx_INTR) | \
> +			 BIT(MDP_INTF5_7xxx_INTR))
> +
> +#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> +			 BIT(MDP_SSPP_TOP0_INTR2) | \
> +			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> +			 BIT(MDP_INTF0_INTR) | \
> +			 BIT(MDP_INTF1_INTR) | \
> +			 BIT(MDP_INTF2_INTR) | \
> +			 BIT(MDP_INTF3_INTR) | \
> +			 BIT(MDP_INTF4_INTR))
> +
> +
>  #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
>  #define DEFAULT_DPU_LINE_WIDTH		2048
>  #define DEFAULT_DPU_OUTPUT_LINE_WIDTH	2560
> @@ -1060,7 +1095,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.reg_dma_count = 1,
>  		.dma_cfg = sdm845_regdma,
>  		.perf = sdm845_perf_data,
> -		.mdss_irqs = 0x3ff,
> +		.mdss_irqs = IRQ_SDM845_MASK,
>  	};
>  }
> 
> @@ -1091,7 +1126,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.reg_dma_count = 1,
>  		.dma_cfg = sdm845_regdma,
>  		.perf = sc7180_perf_data,
> -		.mdss_irqs = 0x3f,
> +		.mdss_irqs = IRQ_SC7180_MASK,
>  		.obsolete_irq = INTR_SC7180_MASK,
>  	};
>  }
> @@ -1125,7 +1160,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.reg_dma_count = 1,
>  		.dma_cfg = sm8150_regdma,
>  		.perf = sm8150_perf_data,
> -		.mdss_irqs = 0x3ff,
> +		.mdss_irqs = IRQ_SDM845_MASK,
>  	};
>  }
> 
> @@ -1158,7 +1193,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.reg_dma_count = 1,
>  		.dma_cfg = sm8250_regdma,
>  		.perf = sm8250_perf_data,
> -		.mdss_irqs = 0xff,
> +		.mdss_irqs = IRQ_SM8250_MASK,
>  	};
>  }
> 
> @@ -1181,7 +1216,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  		.vbif = sdm845_vbif,
>  		.perf = sc7280_perf_data,
> -		.mdss_irqs = 0x1c07,
> +		.mdss_irqs = IRQ_SC7280_MASK,
>  		.obsolete_irq = INTR_SC7180_MASK,
>  	};
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 5bade5637ecc..b26a3445a8eb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -74,6 +74,24 @@ enum dpu_intr_type {
>  	DPU_IRQ_TYPE_RESERVED,
>  };
> 
> +/* When making changes be sure to sync with dpu_intr_set */
> +enum dpu_hw_intr_reg {
> +	MDP_SSPP_TOP0_INTR,
> +	MDP_SSPP_TOP0_INTR2,
> +	MDP_SSPP_TOP0_HIST_INTR,
> +	MDP_INTF0_INTR,
> +	MDP_INTF1_INTR,
> +	MDP_INTF2_INTR,
> +	MDP_INTF3_INTR,
> +	MDP_INTF4_INTR,
> +	MDP_AD4_0_INTR,
> +	MDP_AD4_1_INTR,
> +	MDP_INTF0_7xxx_INTR,
> +	MDP_INTF1_7xxx_INTR,
> +	MDP_INTF5_7xxx_INTR,
> +	MDP_INTR_MAX,
> +};
> +
>  struct dpu_hw_intr;
> 
>  /**

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog
  2021-05-16 20:29 ` [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog Dmitry Baryshkov
@ 2021-05-24 21:57   ` abhinavk
  2021-05-26  2:09     ` Dmitry Baryshkov
  0 siblings, 1 reply; 14+ messages in thread
From: abhinavk @ 2021-05-24 21:57 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to
> maintain. There are only few interrupts used from that table. Newer
> generations use different IRQ locations. Move this data to hw catalog.
> 
I think you can drop the line that "only few interrupts ..." are used as 
that
was specific to sc7280 as you mentioned on IRC or give the example of 
sc7280
here to explain that as being one of the motivations for this cleanup.

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

With that fixed, I think this cleanup looks quite reasonable to me.
I computed a few of the intr offsets and the values were matching the 
prev hard-coded
offsets. Since I dont have the sc7280 HW to test this, I am checking if 
someone with that
hw in our team can test it out as well to make sure that it covers that 
hw as well.

But otherwise,

Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  20 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h  |  13 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  64 +++-----
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |   2 -
>  .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  |  36 ++---
>  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |  31 +---
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 150 +++++++++++-------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  12 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 137 +++++++---------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  17 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h     |  28 ++--
>  11 files changed, 229 insertions(+), 281 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index fd11a2aeab6c..11c0abed21ee 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -43,16 +43,6 @@ static void dpu_core_irq_callback_handler(void
> *arg, int irq_idx)
>  	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
>  }
> 
> -int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
> -		enum dpu_intr_type intr_type, u32 instance_idx)
> -{
> -	if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
> -		return -EINVAL;
> -
> -	return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
> -			intr_type, instance_idx);
> -}
> -
>  /**
>   * _dpu_core_irq_enable - enable core interrupt given by the index
>   * @dpu_kms:		Pointer to dpu kms context
> @@ -70,7 +60,7 @@ static int _dpu_core_irq_enable(struct dpu_kms
> *dpu_kms, int irq_idx)
>  		return -EINVAL;
>  	}
> 
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> +	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>  		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> @@ -133,7 +123,7 @@ static int _dpu_core_irq_disable(struct dpu_kms
> *dpu_kms, int irq_idx)
>  		return -EINVAL;
>  	}
> 
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> +	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>  		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> @@ -208,7 +198,7 @@ int dpu_core_irq_register_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
>  		return -EINVAL;
>  	}
> 
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> +	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>  		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> @@ -243,7 +233,7 @@ int dpu_core_irq_unregister_callback(struct
> dpu_kms *dpu_kms, int irq_idx,
>  		return -EINVAL;
>  	}
> 
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
> +	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>  		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> @@ -328,7 +318,7 @@ void dpu_core_irq_preinstall(struct dpu_kms 
> *dpu_kms)
>  	spin_lock_init(&dpu_kms->irq_obj.cb_lock);
> 
>  	/* Create irq callbacks for all possible irq_idx */
> -	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
> +	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
>  	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
>  			sizeof(struct list_head), GFP_KERNEL);
>  	dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> index e30775e6585b..d147784d5531 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> @@ -29,19 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms 
> *dpu_kms);
>   */
>  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
> 
> -/**
> - * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx 
> from HW
> - *                      interrupt mapping table.
> - * @dpu_kms:		DPU handle
> - * @intr_type:		DPU HW interrupt type for lookup
> - * @instance_idx:	DPU HW block instance defined in dpu_hw_mdss.h
> - * @return:		irq_idx or -EINVAL when fail to lookup
> - */
> -int dpu_core_irq_idx_lookup(
> -		struct dpu_kms *dpu_kms,
> -		enum dpu_intr_type intr_type,
> -		uint32_t instance_idx);
> -
>  /**
>   * dpu_core_irq_enable - IRQ helper function for enabling one or more 
> IRQs
>   * @dpu_kms:		DPU handle
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 8d942052db8a..8a9d01e3b664 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -253,7 +253,7 @@ void dpu_encoder_helper_report_irq_timeout(struct
> dpu_encoder_phys *phys_enc,
>  }
> 
>  static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
> -		int32_t hw_id, struct dpu_encoder_wait_info *info);
> +		u32 irq_idx, struct dpu_encoder_wait_info *info);
> 
>  int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
>  		enum dpu_intr_idx intr_idx,
> @@ -273,27 +273,27 @@ int dpu_encoder_helper_wait_for_irq(struct
> dpu_encoder_phys *phys_enc,
> 
>  	/* return EWOULDBLOCK since we know the wait isn't necessary */
>  	if (phys_enc->enable_state == DPU_ENC_DISABLED) {
> -		DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
> -			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
> +			  DRMID(phys_enc->parent), intr_idx,
>  			  irq->irq_idx);
>  		return -EWOULDBLOCK;
>  	}
> 
>  	if (irq->irq_idx < 0) {
> -		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
> -			      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
> +			      DRMID(phys_enc->parent), intr_idx,
>  			      irq->name);
>  		return 0;
>  	}
> 
> -	DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d",
> -		      DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +	DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
> +		      DRMID(phys_enc->parent), intr_idx,
>  		      irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
>  		      atomic_read(wait_info->atomic_cnt));
> 
>  	ret = dpu_encoder_helper_wait_event_timeout(
>  			DRMID(phys_enc->parent),
> -			irq->hw_idx,
> +			irq->irq_idx,
>  			wait_info);
> 
>  	if (ret <= 0) {
> @@ -303,9 +303,9 @@ int dpu_encoder_helper_wait_for_irq(struct
> dpu_encoder_phys *phys_enc,
>  			unsigned long flags;
> 
>  			DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
> -				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
> +				      "irq=%d, pp=%d, atomic_cnt=%d",
>  				      DRMID(phys_enc->parent), intr_idx,
> -				      irq->hw_idx, irq->irq_idx,
> +				      irq->irq_idx,
>  				      phys_enc->hw_pp->idx - PINGPONG_0,
>  				      atomic_read(wait_info->atomic_cnt));
>  			local_irq_save(flags);
> @@ -315,16 +315,16 @@ int dpu_encoder_helper_wait_for_irq(struct
> dpu_encoder_phys *phys_enc,
>  		} else {
>  			ret = -ETIMEDOUT;
>  			DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
> -				      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
> +				      "irq=%d, pp=%d, atomic_cnt=%d",
>  				      DRMID(phys_enc->parent), intr_idx,
> -				      irq->hw_idx, irq->irq_idx,
> +				      irq->irq_idx,
>  				      phys_enc->hw_pp->idx - PINGPONG_0,
>  				      atomic_read(wait_info->atomic_cnt));
>  		}
>  	} else {
>  		ret = 0;
>  		trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
> -			intr_idx, irq->hw_idx, irq->irq_idx,
> +			intr_idx, irq->irq_idx,
>  			phys_enc->hw_pp->idx - PINGPONG_0,
>  			atomic_read(wait_info->atomic_cnt));
>  	}
> @@ -344,19 +344,9 @@ int dpu_encoder_helper_register_irq(struct
> dpu_encoder_phys *phys_enc,
>  	}
>  	irq = &phys_enc->irq[intr_idx];
> 
> -	if (irq->irq_idx >= 0) {
> -		DPU_DEBUG_PHYS(phys_enc,
> -				"skipping already registered irq %s type %d\n",
> -				irq->name, irq->intr_type);
> -		return 0;
> -	}
> -
> -	irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
> -			irq->intr_type, irq->hw_idx);
>  	if (irq->irq_idx < 0) {
>  		DPU_ERROR_PHYS(phys_enc,
> -			"failed to lookup IRQ index for %s type:%d\n",
> -			irq->name, irq->intr_type);
> +			"invalid IRQ index:%d\n", irq->irq_idx);
>  		return -EINVAL;
>  	}
> 
> @@ -372,8 +362,8 @@ int dpu_encoder_helper_register_irq(struct
> dpu_encoder_phys *phys_enc,
> 
>  	ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
>  	if (ret) {
> -		DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
> -			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_ERROR("enable failed id=%u, intr=%d, irq=%d",
> +			  DRMID(phys_enc->parent), intr_idx,
>  			  irq->irq_idx);
>  		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
>  				irq->irq_idx, &irq->cb);
> @@ -382,7 +372,7 @@ int dpu_encoder_helper_register_irq(struct
> dpu_encoder_phys *phys_enc,
>  	}
> 
>  	trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
> -				irq->hw_idx, irq->irq_idx);
> +				irq->irq_idx);
> 
>  	return ret;
>  }
> @@ -397,31 +387,29 @@ int dpu_encoder_helper_unregister_irq(struct
> dpu_encoder_phys *phys_enc,
> 
>  	/* silently skip irqs that weren't registered */
>  	if (irq->irq_idx < 0) {
> -		DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
> -			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
> +			  DRMID(phys_enc->parent), intr_idx,
>  			  irq->irq_idx);
>  		return 0;
>  	}
> 
>  	ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
>  	if (ret) {
> -		DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
> -			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_ERROR("disable failed id=%u, intr=%d, irq=%d ret=%d",
> +			  DRMID(phys_enc->parent), intr_idx,
>  			  irq->irq_idx, ret);
>  	}
> 
>  	ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 
> irq->irq_idx,
>  			&irq->cb);
>  	if (ret) {
> -		DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
> -			  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
> +		DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
> +			  DRMID(phys_enc->parent), intr_idx,
>  			  irq->irq_idx, ret);
>  	}
> 
>  	trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), 
> intr_idx,
> -					     irq->hw_idx, irq->irq_idx);
> -
> -	irq->irq_idx = -EINVAL;
> +					     irq->irq_idx);
> 
>  	return 0;
>  }
> @@ -1537,7 +1525,7 @@ void dpu_encoder_helper_trigger_start(struct
> dpu_encoder_phys *phys_enc)
> 
>  static int dpu_encoder_helper_wait_event_timeout(
>  		int32_t drm_id,
> -		int32_t hw_id,
> +		u32 irq_idx,
>  		struct dpu_encoder_wait_info *info)
>  {
>  	int rc = 0;
> @@ -1550,7 +1538,7 @@ static int dpu_encoder_helper_wait_event_timeout(
>  				atomic_read(info->atomic_cnt) == 0, jiffies);
>  		time = ktime_to_ms(ktime_get());
> 
> -		trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
> +		trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
>  						 expected_time,
>  						 atomic_read(info->atomic_cnt));
>  	/* If we timed out, counter is valid and time is less, wait again */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index ecbc4be98980..3bd12ce45a80 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -167,7 +167,6 @@ enum dpu_intr_idx {
>   * @name:		string name of interrupt
>   * @intr_type:		Encoder interrupt type
>   * @intr_idx:		Encoder interrupt enumeration
> - * @hw_idx:		HW Block ID
>   * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
>   *			will be -EINVAL if IRQ is not registered
>   * @irq_cb:		interrupt callback
> @@ -176,7 +175,6 @@ struct dpu_encoder_irq {
>  	const char *name;
>  	enum dpu_intr_type intr_type;
>  	enum dpu_intr_idx intr_idx;
> -	int hw_idx;
>  	int irq_idx;
>  	struct dpu_irq_callback cb;
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index b2be39b9144e..6f06e379b97f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -143,28 +143,6 @@ static void
> dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
>  			phys_enc);
>  }
> 
> -static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
> -		struct dpu_encoder_phys *phys_enc)
> -{
> -	struct dpu_encoder_irq *irq;
> -
> -	irq = &phys_enc->irq[INTR_IDX_CTL_START];
> -	irq->hw_idx = phys_enc->hw_ctl->idx;
> -	irq->irq_idx = -EINVAL;
> -
> -	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
> -	irq->hw_idx = phys_enc->hw_pp->idx;
> -	irq->irq_idx = -EINVAL;
> -
> -	irq = &phys_enc->irq[INTR_IDX_RDPTR];
> -	irq->hw_idx = phys_enc->hw_pp->idx;
> -	irq->irq_idx = -EINVAL;
> -
> -	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
> -	irq->hw_idx = phys_enc->intf_idx;
> -	irq->irq_idx = -EINVAL;
> -}
> -
>  static void dpu_encoder_phys_cmd_mode_set(
>  		struct dpu_encoder_phys *phys_enc,
>  		struct drm_display_mode *mode,
> @@ -172,6 +150,7 @@ static void dpu_encoder_phys_cmd_mode_set(
>  {
>  	struct dpu_encoder_phys_cmd *cmd_enc =
>  		to_dpu_encoder_phys_cmd(phys_enc);
> +	struct dpu_encoder_irq *irq;
> 
>  	if (!mode || !adj_mode) {
>  		DPU_ERROR("invalid args\n");
> @@ -181,7 +160,17 @@ static void dpu_encoder_phys_cmd_mode_set(
>  	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
>  	drm_mode_debug_printmodeline(adj_mode);
> 
> -	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
> +	irq = &phys_enc->irq[INTR_IDX_CTL_START];
> +	irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
> +
> +	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
> +	irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
> +
> +	irq = &phys_enc->irq[INTR_IDX_RDPTR];
> +	irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
> +
> +	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
> +	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
>  }
> 
>  static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
> @@ -795,7 +784,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
>  		irq = &phys_enc->irq[i];
>  		INIT_LIST_HEAD(&irq->cb.list);
>  		irq->irq_idx = -EINVAL;
> -		irq->hw_idx = -EINVAL;
>  		irq->cb.arg = phys_enc;
>  	}
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 0e06b7e73c7a..6cdb4ecbc173 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -363,38 +363,24 @@ static bool 
> dpu_encoder_phys_vid_needs_single_flush(
>  	return phys_enc->split_role != ENC_ROLE_SOLO;
>  }
> 
> -static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
> -		struct dpu_encoder_phys *phys_enc)
> -{
> -	struct dpu_encoder_irq *irq;
> -
> -	/*
> -	 * Initialize irq->hw_idx only when irq is not registered.
> -	 * Prevent invalidating irq->irq_idx as modeset may be
> -	 * called many times during dfps.
> -	 */
> -
> -	irq = &phys_enc->irq[INTR_IDX_VSYNC];
> -	if (irq->irq_idx < 0)
> -		irq->hw_idx = phys_enc->intf_idx;
> -
> -	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
> -	if (irq->irq_idx < 0)
> -		irq->hw_idx = phys_enc->intf_idx;
> -}
> -
>  static void dpu_encoder_phys_vid_mode_set(
>  		struct dpu_encoder_phys *phys_enc,
>  		struct drm_display_mode *mode,
>  		struct drm_display_mode *adj_mode)
>  {
> +	struct dpu_encoder_irq *irq;
> +
>  	if (adj_mode) {
>  		phys_enc->cached_mode = *adj_mode;
>  		drm_mode_debug_printmodeline(adj_mode);
>  		DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
>  	}
> 
> -	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
> +	irq = &phys_enc->irq[INTR_IDX_VSYNC];
> +	irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
> +
> +	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
> +	irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
>  }
> 
>  static int dpu_encoder_phys_vid_control_vblank_irq(
> @@ -636,7 +622,7 @@ static void
> dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
> 
>  	if (enable) {
>  		ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
> -		if (ret)
> +		if (WARN_ON(ret))
>  			return;
> 
>  		dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
> @@ -738,7 +724,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
>  		irq = &phys_enc->irq[i];
>  		INIT_LIST_HEAD(&irq->cb.list);
>  		irq->irq_idx = -EINVAL;
> -		irq->hw_idx = -EINVAL;
>  		irq->cb.arg = phys_enc;
>  	}
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 9a77d64d3fd4..f929131ed260 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -350,27 +350,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
>  	{
>  	.name = "ctl_0", .id = CTL_0,
>  	.base = 0x1000, .len = 0xE4,
> -	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
> +	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>  	},
>  	{
>  	.name = "ctl_1", .id = CTL_1,
>  	.base = 0x1200, .len = 0xE4,
> -	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
> +	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>  	},
>  	{
>  	.name = "ctl_2", .id = CTL_2,
>  	.base = 0x1400, .len = 0xE4,
> -	.features = 0
> +	.features = 0,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>  	},
>  	{
>  	.name = "ctl_3", .id = CTL_3,
>  	.base = 0x1600, .len = 0xE4,
> -	.features = 0
> +	.features = 0,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>  	},
>  	{
>  	.name = "ctl_4", .id = CTL_4,
>  	.base = 0x1800, .len = 0xE4,
> -	.features = 0
> +	.features = 0,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>  	},
>  };
> 
> @@ -378,17 +383,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
>  	{
>  	.name = "ctl_0", .id = CTL_0,
>  	.base = 0x1000, .len = 0xE4,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>  	},
>  	{
>  	.name = "ctl_1", .id = CTL_1,
>  	.base = 0x1200, .len = 0xE4,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>  	},
>  	{
>  	.name = "ctl_2", .id = CTL_2,
>  	.base = 0x1400, .len = 0xE4,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>  	},
>  };
> 
> @@ -396,32 +404,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
>  	{
>  	.name = "ctl_0", .id = CTL_0,
>  	.base = 0x1000, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>  	},
>  	{
>  	.name = "ctl_1", .id = CTL_1,
>  	.base = 0x1200, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>  	},
>  	{
>  	.name = "ctl_2", .id = CTL_2,
>  	.base = 0x1400, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>  	},
>  	{
>  	.name = "ctl_3", .id = CTL_3,
>  	.base = 0x1600, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>  	},
>  	{
>  	.name = "ctl_4", .id = CTL_4,
>  	.base = 0x1800, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>  	},
>  	{
>  	.name = "ctl_5", .id = CTL_5,
>  	.base = 0x1a00, .len = 0x1e0,
> -	.features = BIT(DPU_CTL_ACTIVE_CFG)
> +	.features = BIT(DPU_CTL_ACTIVE_CFG),
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>  	},
>  };
> 
> @@ -429,22 +443,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
>  	{
>  	.name = "ctl_0", .id = CTL_0,
>  	.base = 0x15000, .len = 0x1E8,
> -	.features = CTL_SC7280_MASK
> +	.features = CTL_SC7280_MASK,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>  	},
>  	{
>  	.name = "ctl_1", .id = CTL_1,
>  	.base = 0x16000, .len = 0x1E8,
> -	.features = CTL_SC7280_MASK
> +	.features = CTL_SC7280_MASK,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>  	},
>  	{
>  	.name = "ctl_2", .id = CTL_2,
>  	.base = 0x17000, .len = 0x1E8,
> -	.features = CTL_SC7280_MASK
> +	.features = CTL_SC7280_MASK,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>  	},
>  	{
>  	.name = "ctl_3", .id = CTL_3,
>  	.base = 0x18000, .len = 0x1E8,
> -	.features = CTL_SC7280_MASK
> +	.features = CTL_SC7280_MASK,
> +	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>  	},
>  };
> 
> @@ -725,42 +743,66 @@ static const struct dpu_pingpong_sub_blks
> sc7280_pp_sblk = {
>  	.len = 0x20, .version = 0x20000},
>  };
> 
> -#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
> +#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) 
> \
>  	{\
>  	.name = _name, .id = _id, \
>  	.base = _base, .len = 0xd4, \
>  	.features = PINGPONG_SDM845_SPLIT_MASK, \
>  	.merge_3d = _merge_3d, \
> -	.sblk = &_sblk \
> +	.sblk = &_sblk, \
> +	.intr_done = _done, \
> +	.intr_rdptr = _rdptr, \
>  	}
> -#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
> +#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>  	{\
>  	.name = _name, .id = _id, \
>  	.base = _base, .len = 0xd4, \
>  	.features = PINGPONG_SDM845_MASK, \
>  	.merge_3d = _merge_3d, \
> -	.sblk = &_sblk \
> +	.sblk = &_sblk, \
> +	.intr_done = _done, \
> +	.intr_rdptr = _rdptr, \
>  	}
> 
>  static const struct dpu_pingpong_cfg sdm845_pp[] = {
> -	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
> -	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
> -	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
> -	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
> +	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> +	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> +	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> +	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
>  };
> 
>  static struct dpu_pingpong_cfg sc7180_pp[] = {
> -	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
> -	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
> +	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, 
> -1, -1),
> +	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, 
> -1, -1),
>  };
> 
>  static const struct dpu_pingpong_cfg sm8150_pp[] = {
> -	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, 
> sdm845_pp_sblk_te),
> -	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, 
> sdm845_pp_sblk_te),
> -	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, 
> sdm845_pp_sblk),
> -	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, 
> sdm845_pp_sblk),
> -	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, 
> sdm845_pp_sblk),
> -	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, 
> sdm845_pp_sblk),
> +	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, 
> sdm845_pp_sblk_te,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
> +	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, 
> sdm845_pp_sblk_te,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
> +	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
> +	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
> +	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> +			-1),
> +	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
> +			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> +			-1),
>  };
> 
>  /*************************************************************
> @@ -781,47 +823,49 @@ static const struct dpu_merge_3d_cfg 
> sm8150_merge_3d[] = {
>  };
> 
>  static const struct dpu_pingpong_cfg sc7280_pp[] = {
> -	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
> -	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
> -	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
> -	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
> +	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
> +	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
> +	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
> +	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
>  };
>  /*************************************************************
>   * INTF sub blocks config
>   *************************************************************/
> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, 
> _features) \
> +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch,
> _features, _reg, _underrun_bit, _vsync_bit) \
>  	{\
>  	.name = _name, .id = _id, \
>  	.base = _base, .len = 0x280, \
>  	.features = _features, \
>  	.type = _type, \
>  	.controller_id = _ctrl_id, \
> -	.prog_fetch_lines_worst_case = _progfetch \
> +	.prog_fetch_lines_worst_case = _progfetch, \
> +	.intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
> +	.intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
>  	}
> 
>  static const struct dpu_intf_cfg sdm845_intf[] = {
> -	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
> INTF_SDM845_MASK),
> -	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
> INTF_SDM845_MASK),
> -	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, 
> INTF_SDM845_MASK),
> -	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, 
> INTF_SDM845_MASK),
> +	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> +	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> +	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24,
> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> +	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24,
> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>  };
> 
>  static const struct dpu_intf_cfg sc7180_intf[] = {
> -	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
> INTF_SC7180_MASK),
> -	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
> INTF_SC7180_MASK),
> +	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> +	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>  };
> 
>  static const struct dpu_intf_cfg sm8150_intf[] = {
> -	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
> INTF_SC7180_MASK),
> -	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
> INTF_SC7180_MASK),
> -	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, 
> INTF_SC7180_MASK),
> -	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, 
> INTF_SC7180_MASK),
> +	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> +	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> +	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
> +	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24,
> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>  };
> 
>  static const struct dpu_intf_cfg sc7280_intf[] = {
> -	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, 
> INTF_SC7280_MASK),
> -	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, 
> INTF_SC7280_MASK),
> -	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, 
> INTF_SC7280_MASK),
> +	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24,
> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> +	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24,
> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
> +	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24,
> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>  };
> 
>  /*************************************************************
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 4dfd8a20ad5c..316da2971320 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -464,13 +464,15 @@ struct dpu_mdp_cfg {
>  	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
>  };
> 
> -/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
> +/* struct dpu_ctl_cfg : MDP CTL instance info
>   * @id:                index identifying this block
>   * @base:              register base offset to mdss
>   * @features           bit mask identifying sub-blocks/features
> + * @intr_start:        interrupt index for CTL_START
>   */
>  struct dpu_ctl_cfg {
>  	DPU_HW_BLK_INFO;
> +	s32 intr_start;
>  };
> 
>  /**
> @@ -526,11 +528,15 @@ struct dpu_dspp_cfg  {
>   * @id                 enum identifying this block
>   * @base               register offset of this block
>   * @features           bit mask identifying sub-blocks/features
> + * @intr_done:         index for PINGPONG done interrupt
> + * @intr_rdptr:        index for PINGPONG readpointer done interrupt
>   * @sblk               sub-blocks information
>   */
>  struct dpu_pingpong_cfg  {
>  	DPU_HW_BLK_INFO;
>  	u32 merge_3d;
> +	s32 intr_done;
> +	s32 intr_rdptr;
>  	const struct dpu_pingpong_sub_blks *sblk;
>  };
> 
> @@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg  {
>   * @type:              Interface type(DSI, DP, HDMI)
>   * @controller_id:     Controller Instance ID in case of multiple of 
> intf type
>   * @prog_fetch_lines_worst_case	Worst case latency num lines needed to 
> prefetch
> + * @intr_underrun:	index for INTF underrun interrupt
> + * @intr_vsync:	        index for INTF VSYNC interrupt
>   */
>  struct dpu_intf_cfg  {
>  	DPU_HW_BLK_INFO;
>  	u32 type;   /* interface type*/
>  	u32 controller_id;
>  	u32 prog_fetch_lines_worst_case;
> +	s32 intr_underrun;
> +	s32 intr_vsync;
>  };
> 
>  /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 8bd22e060437..adc1f04ac257 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -196,6 +196,8 @@ struct dpu_irq_type {
> 
>  /*
>   * struct dpu_intr_reg -  List of DPU interrupt registers
> + *
> + * When making changes be sure to sync with dpu_hw_intr_reg
>   */
>  static const struct dpu_intr_reg dpu_intr_set[] = {
>  	{
> @@ -265,6 +267,9 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>  	},
>  };
> 
> +#define DPU_IRQ_REG(irq_idx)	(irq_idx / 32)
> +#define DPU_IRQ_MASK(irq_idx)	(BIT(irq_idx % 32))
> +
>  /*
>   * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx 
> in this
>   *			 table that have a matching interface type and
> @@ -1345,23 +1350,6 @@ static const struct dpu_irq_type dpu_irq_map[] = 
> {
>  	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
>  };
> 
> -static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
> -	enum dpu_intr_type intr_type, u32 instance_idx)
> -{
> -	int i;
> -
> -	for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
> -		if (intr_type == dpu_irq_map[i].intr_type &&
> -			instance_idx == dpu_irq_map[i].instance_idx &&
> -			!(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
> -			return i;
> -	}
> -
> -	pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
> -			intr_type, instance_idx);
> -	return -EINVAL;
> -}
> -
>  static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
> *intr,
>  		int irq_idx)
>  {
> @@ -1370,9 +1358,8 @@ static void
> dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
>  	if (!intr)
>  		return;
> 
> -	reg_idx = dpu_irq_map[irq_idx].reg_idx;
> -	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> -			dpu_irq_map[irq_idx].irq_mask);
> +	reg_idx = DPU_IRQ_REG(irq_idx);
> +	DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> DPU_IRQ_MASK(irq_idx));
> 
>  	/* ensure register writes go through */
>  	wmb();
> @@ -1384,10 +1371,9 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  {
>  	int reg_idx;
>  	int irq_idx;
> -	int start_idx;
> -	int end_idx;
>  	u32 irq_status;
>  	u32 enable_mask;
> +	int bit;
>  	unsigned long irq_flags;
> 
>  	if (!intr)
> @@ -1400,15 +1386,7 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  	 */
>  	spin_lock_irqsave(&intr->irq_lock, irq_flags);
>  	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> -		/*
> -		 * Each Interrupt register has a range of 64 indexes, and
> -		 * that is static for dpu_irq_map.
> -		 */
> -		start_idx = reg_idx * 64;
> -		end_idx = start_idx + 64;
> -
> -		if (!test_bit(reg_idx, &intr->irq_mask) ||
> -			start_idx >= ARRAY_SIZE(dpu_irq_map))
> +		if (!test_bit(reg_idx, &intr->irq_mask))
>  			continue;
> 
>  		/* Read interrupt status */
> @@ -1425,37 +1403,33 @@ static void dpu_hw_intr_dispatch_irq(struct
> dpu_hw_intr *intr,
>  		/* Finally update IRQ status based on enable mask */
>  		irq_status &= enable_mask;
> 
> +		if (!irq_status)
> +			continue;
> +
>  		/*
> -		 * Search through matching intr status from irq map.
> -		 * start_idx and end_idx defined the search range in
> -		 * the dpu_irq_map.
> +		 * Search through matching intr status.
>  		 */
> -		for (irq_idx = start_idx;
> -				(irq_idx < end_idx) && irq_status;
> -				irq_idx++)
> -			if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
> -				(dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
> -				!(intr->obsolete_irq &
> -				BIT(dpu_irq_map[irq_idx].intr_type))) {
> -				/*
> -				 * Once a match on irq mask, perform a callback
> -				 * to the given cbfunc. cbfunc will take care
> -				 * the interrupt status clearing. If cbfunc is
> -				 * not provided, then the interrupt clearing
> -				 * is here.
> -				 */
> -				if (cbfunc)
> -					cbfunc(arg, irq_idx);
> -
> -				dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> -
> -				/*
> -				 * When callback finish, clear the irq_status
> -				 * with the matching mask. Once irq_status
> -				 * is all cleared, the search can be stopped.
> -				 */
> -				irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
> -			}
> +		while ((bit = ffs(irq_status)) != 0) {
> +			irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
> +			/*
> +			 * Once a match on irq mask, perform a callback
> +			 * to the given cbfunc. cbfunc will take care
> +			 * the interrupt status clearing. If cbfunc is
> +			 * not provided, then the interrupt clearing
> +			 * is here.
> +			 */
> +			if (cbfunc)
> +				cbfunc(arg, irq_idx);
> +
> +			dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> +
> +			/*
> +			 * When callback finish, clear the irq_status
> +			 * with the matching mask. Once irq_status
> +			 * is all cleared, the search can be stopped.
> +			 */
> +			irq_status &= ~BIT(bit - 1);
> +		}
>  	}
> 
>  	/* ensure register writes go through */
> @@ -1469,32 +1443,30 @@ static int dpu_hw_intr_enable_irq(struct
> dpu_hw_intr *intr, int irq_idx)
>  	int reg_idx;
>  	unsigned long irq_flags;
>  	const struct dpu_intr_reg *reg;
> -	const struct dpu_irq_type *irq;
>  	const char *dbgstr = NULL;
>  	uint32_t cache_irq_mask;
> 
>  	if (!intr)
>  		return -EINVAL;
> 
> -	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
> +	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>  		pr_err("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> 
> -	irq = &dpu_irq_map[irq_idx];
> -	reg_idx = irq->reg_idx;
> +	reg_idx = DPU_IRQ_REG(irq_idx);
>  	reg = &dpu_intr_set[reg_idx];
> 
>  	spin_lock_irqsave(&intr->irq_lock, irq_flags);
>  	cache_irq_mask = intr->cache_irq_mask[reg_idx];
> -	if (cache_irq_mask & irq->irq_mask) {
> +	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
>  		dbgstr = "DPU IRQ already set:";
>  	} else {
>  		dbgstr = "DPU IRQ enabled:";
> 
> -		cache_irq_mask |= irq->irq_mask;
> +		cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
>  		/* Cleaning any pending interrupt */
> -		DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
> +		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
>  		/* Enabling interrupts with the new mask */
>  		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
> 
> @@ -1505,8 +1477,8 @@ static int dpu_hw_intr_enable_irq(struct
> dpu_hw_intr *intr, int irq_idx)
>  	}
>  	spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
> 
> -	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
> -			irq->irq_mask, cache_irq_mask);
> +	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
> +			DPU_IRQ_MASK(irq_idx), cache_irq_mask);
> 
>  	return 0;
>  }
> @@ -1515,33 +1487,31 @@ static int
> dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
>  {
>  	int reg_idx;
>  	const struct dpu_intr_reg *reg;
> -	const struct dpu_irq_type *irq;
>  	const char *dbgstr = NULL;
>  	uint32_t cache_irq_mask;
> 
>  	if (!intr)
>  		return -EINVAL;
> 
> -	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
> +	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>  		pr_err("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> 
> -	irq = &dpu_irq_map[irq_idx];
> -	reg_idx = irq->reg_idx;
> +	reg_idx = DPU_IRQ_REG(irq_idx);
>  	reg = &dpu_intr_set[reg_idx];
> 
>  	cache_irq_mask = intr->cache_irq_mask[reg_idx];
> -	if ((cache_irq_mask & irq->irq_mask) == 0) {
> +	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
>  		dbgstr = "DPU IRQ is already cleared:";
>  	} else {
>  		dbgstr = "DPU IRQ mask disable:";
> 
> -		cache_irq_mask &= ~irq->irq_mask;
> +		cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
>  		/* Disable interrupts based on the new mask */
>  		DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
>  		/* Cleaning any pending interrupt */
> -		DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
> +		DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
> 
>  		/* ensure register write goes through */
>  		wmb();
> @@ -1549,8 +1519,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct
> dpu_hw_intr *intr, int irq_idx)
>  		intr->cache_irq_mask[reg_idx] = cache_irq_mask;
>  	}
> 
> -	pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
> -			irq->irq_mask, cache_irq_mask);
> +	pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
> +			DPU_IRQ_MASK(irq_idx), cache_irq_mask);
> 
>  	return 0;
>  }
> @@ -1562,7 +1532,7 @@ static int dpu_hw_intr_disable_irq(struct
> dpu_hw_intr *intr, int irq_idx)
>  	if (!intr)
>  		return -EINVAL;
> 
> -	if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
> +	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>  		pr_err("invalid IRQ index: [%d]\n", irq_idx);
>  		return -EINVAL;
>  	}
> @@ -1622,17 +1592,17 @@ static u32
> dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>  	if (!intr)
>  		return 0;
> 
> -	if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
> +	if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>  		pr_err("invalid IRQ index: [%d]\n", irq_idx);
>  		return 0;
>  	}
> 
>  	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> 
> -	reg_idx = dpu_irq_map[irq_idx].reg_idx;
> +	reg_idx = DPU_IRQ_REG(irq_idx);
>  	intr_status = DPU_REG_READ(&intr->hw,
>  			dpu_intr_set[reg_idx].status_off) &
> -					dpu_irq_map[irq_idx].irq_mask;
> +		DPU_IRQ_MASK(irq_idx);
>  	if (intr_status && clear)
>  		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>  				intr_status);
> @@ -1647,7 +1617,6 @@ static u32
> dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
> 
>  static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
>  {
> -	ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
>  	ops->enable_irq = dpu_hw_intr_enable_irq;
>  	ops->disable_irq = dpu_hw_intr_disable_irq;
>  	ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
> @@ -1679,7 +1648,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem 
> *addr,
>  	__intr_offset(m, addr, &intr->hw);
>  	__setup_intr_ops(&intr->ops);
> 
> -	intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
> +	intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
> 
>  	intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32),
>  			GFP_KERNEL);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index b26a3445a8eb..c6b3d373ce75 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -92,23 +92,14 @@ enum dpu_hw_intr_reg {
>  	MDP_INTR_MAX,
>  };
> 
> +#define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
> +
>  struct dpu_hw_intr;
> 
>  /**
>   * Interrupt operations.
>   */
>  struct dpu_hw_intr_ops {
> -	/**
> -	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
> -	 *                 Used for all irq related ops
> -	 * @intr:		HW interrupt handle
> -	 * @intr_type:		Interrupt type defined in dpu_intr_type
> -	 * @instance_idx:	HW interrupt block instance
> -	 * @return:		irq_idx or -EINVAL for lookup fail
> -	 */
> -	int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
> -			enum dpu_intr_type intr_type,
> -			u32 instance_idx);
> 
>  	/**
>  	 * enable_irq - Enable IRQ based on lookup IRQ index
> @@ -179,7 +170,7 @@ struct dpu_hw_intr_ops {
>   * @ops:              function pointer mapping for IRQ handling
>   * @cache_irq_mask:   array of IRQ enable masks reg storage created 
> during init
>   * @save_irq_status:  array of IRQ status reg storage created during 
> init
> - * @irq_idx_tbl_size: total number of irq_idx mapped in the 
> hw_interrupts
> + * @total_irqs: total number of irq_idx mapped in the hw_interrupts
>   * @irq_lock:         spinlock for accessing IRQ resources
>   * @obsolete_irq:      irq types that are obsolete for a particular 
> target
>   */
> @@ -188,7 +179,7 @@ struct dpu_hw_intr {
>  	struct dpu_hw_intr_ops ops;
>  	u32 *cache_irq_mask;
>  	u32 *save_irq_status;
> -	u32 irq_idx_tbl_size;
> +	u32 total_irqs;
>  	spinlock_t irq_lock;
>  	unsigned long irq_mask;
>  	unsigned long obsolete_irq;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index 6714b088970f..e349ea78a49d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -188,24 +188,23 @@ DECLARE_EVENT_CLASS(dpu_enc_irq_template,
>  		  __entry->irq_idx)
>  );
>  DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
> -	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
> +	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>  		 int irq_idx),
> -	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
> +	TP_ARGS(drm_id, intr_idx, irq_idx)
>  );
>  DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
> -	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
> +	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>  		 int irq_idx),
> -	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
> +	TP_ARGS(drm_id, intr_idx, irq_idx)
>  );
> 
>  TRACE_EVENT(dpu_enc_irq_wait_success,
> -	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
> +	TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>  		 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
>  	TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
>  	TP_STRUCT__entry(
>  		__field(	uint32_t,		drm_id		)
>  		__field(	enum dpu_intr_idx,	intr_idx	)
> -		__field(	int,			hw_idx		)
>  		__field(	int,			irq_idx		)
>  		__field(	enum dpu_pingpong,	pp_idx		)
>  		__field(	int,			atomic_cnt	)
> @@ -213,13 +212,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success,
>  	TP_fast_assign(
>  		__entry->drm_id = drm_id;
>  		__entry->intr_idx = intr_idx;
> -		__entry->hw_idx = hw_idx;
>  		__entry->irq_idx = irq_idx;
>  		__entry->pp_idx = pp_idx;
>  		__entry->atomic_cnt = atomic_cnt;
>  	),
> -	TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
> -		  __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
> +	TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
> +		  __entry->drm_id, __entry->hw_idx,
>  		  __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
>  );
> 
> @@ -514,12 +512,12 @@ DEFINE_EVENT(dpu_id_event_template,
> dpu_crtc_frame_event_more_pending,
>  );
> 
>  TRACE_EVENT(dpu_enc_wait_event_timeout,
> -	TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
> +	TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
>  		 s64 expected_time, int atomic_cnt),
> -	TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
> +	TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
>  	TP_STRUCT__entry(
>  		__field(	uint32_t,	drm_id		)
> -		__field(	int32_t,	hw_id		)
> +		__field(	int,		irq_idx		)
>  		__field(	int,		rc		)
>  		__field(	s64,		time		)
>  		__field(	s64,		expected_time	)
> @@ -527,14 +525,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
>  	),
>  	TP_fast_assign(
>  		__entry->drm_id = drm_id;
> -		__entry->hw_id = hw_id;
> +		__entry->irq_idx = irq_idx;
>  		__entry->rc = rc;
>  		__entry->time = time;
>  		__entry->expected_time = expected_time;
>  		__entry->atomic_cnt = atomic_cnt;
>  	),
> -	TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
> -		  __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
> +	TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld 
> cnt=%d",
> +		  __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
>  		  __entry->expected_time, __entry->atomic_cnt)
>  );

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem
  2021-05-16 20:29 ` [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem Dmitry Baryshkov
@ 2021-05-24 21:58   ` abhinavk
  0 siblings, 0 replies; 14+ messages in thread
From: abhinavk @ 2021-05-24 21:58 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> There is no more need for the dpu_intr_type types, dpu_irq_map table,
> individual intr defines and obsolete_irq field. Drop all of them now.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |    2 -
>  .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  |    4 -
>  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |    2 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |    9 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |    2 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1234 -----------------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |   64 -
>  7 files changed, 1317 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index 3bd12ce45a80..e7270eb6b84b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -165,7 +165,6 @@ enum dpu_intr_idx {
>  /**
>   * dpu_encoder_irq - tracking structure for interrupts
>   * @name:		string name of interrupt
> - * @intr_type:		Encoder interrupt type
>   * @intr_idx:		Encoder interrupt enumeration
>   * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
>   *			will be -EINVAL if IRQ is not registered
> @@ -173,7 +172,6 @@ enum dpu_intr_idx {
>   */
>  struct dpu_encoder_irq {
>  	const char *name;
> -	enum dpu_intr_type intr_type;
>  	enum dpu_intr_idx intr_idx;
>  	int irq_idx;
>  	struct dpu_irq_callback cb;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 6f06e379b97f..36064004d6ff 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -789,25 +789,21 @@ struct dpu_encoder_phys 
> *dpu_encoder_phys_cmd_init(
> 
>  	irq = &phys_enc->irq[INTR_IDX_CTL_START];
>  	irq->name = "ctl_start";
> -	irq->intr_type = DPU_IRQ_TYPE_CTL_START;
>  	irq->intr_idx = INTR_IDX_CTL_START;
>  	irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq;
> 
>  	irq = &phys_enc->irq[INTR_IDX_PINGPONG];
>  	irq->name = "pp_done";
> -	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP;
>  	irq->intr_idx = INTR_IDX_PINGPONG;
>  	irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq;
> 
>  	irq = &phys_enc->irq[INTR_IDX_RDPTR];
>  	irq->name = "pp_rd_ptr";
> -	irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR;
>  	irq->intr_idx = INTR_IDX_RDPTR;
>  	irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq;
> 
>  	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>  	irq->name = "underrun";
> -	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
>  	irq->intr_idx = INTR_IDX_UNDERRUN;
>  	irq->cb.func = dpu_encoder_phys_cmd_underrun_irq;
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 6cdb4ecbc173..4ef3d7357c2d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -729,13 +729,11 @@ struct dpu_encoder_phys 
> *dpu_encoder_phys_vid_init(
> 
>  	irq = &phys_enc->irq[INTR_IDX_VSYNC];
>  	irq->name = "vsync_irq";
> -	irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC;
>  	irq->intr_idx = INTR_IDX_VSYNC;
>  	irq->cb.func = dpu_encoder_phys_vid_vblank_irq;
> 
>  	irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>  	irq->name = "underrun";
> -	irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN;
>  	irq->intr_idx = INTR_IDX_UNDERRUN;
>  	irq->cb.func = dpu_encoder_phys_vid_underrun_irq;
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index f929131ed260..d01c4c919504 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -74,13 +74,6 @@
>  			 BIT(MDP_INTF0_INTR) | \
>  			 BIT(MDP_INTF1_INTR))
> 
> -#define INTR_SC7180_MASK \
> -	(BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\
> -	BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\
> -	BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\
> -	BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\
> -	BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK))
> -
>  #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
>  			 BIT(MDP_SSPP_TOP0_INTR2) | \
>  			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> @@ -1171,7 +1164,6 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.dma_cfg = sdm845_regdma,
>  		.perf = sc7180_perf_data,
>  		.mdss_irqs = IRQ_SC7180_MASK,
> -		.obsolete_irq = INTR_SC7180_MASK,
>  	};
>  }
> 
> @@ -1261,7 +1253,6 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg 
> *dpu_cfg)
>  		.vbif = sdm845_vbif,
>  		.perf = sc7280_perf_data,
>  		.mdss_irqs = IRQ_SC7280_MASK,
> -		.obsolete_irq = INTR_SC7180_MASK,
>  	};
>  }
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 316da2971320..7c86fdd14493 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -733,7 +733,6 @@ struct dpu_perf_cfg {
>   * @cursor_formats     Supported formats for cursor pipe
>   * @vig_formats        Supported formats for vig pipe
>   * @mdss_irqs:         Bitmap with the irqs supported by the target
> - * @obsolete_irq:       Irq types that are obsolete for a particular 
> target
>   */
>  struct dpu_mdss_cfg {
>  	u32 hwversion;
> @@ -780,7 +779,6 @@ struct dpu_mdss_cfg {
>  	const struct dpu_format_extended *vig_formats;
> 
>  	unsigned long mdss_irqs;
> -	unsigned long obsolete_irq;
>  };
> 
>  struct dpu_mdss_hw_cfg_handler {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index adc1f04ac257..ef16ba57aac1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -29,145 +29,6 @@
>  #define MDP_INTF_1_OFF_REV_7xxx             0x35000
>  #define MDP_INTF_5_OFF_REV_7xxx             0x39000
> 
> -/**
> - * WB interrupt status bit definitions
> - */
> -#define DPU_INTR_WB_0_DONE BIT(0)
> -#define DPU_INTR_WB_1_DONE BIT(1)
> -#define DPU_INTR_WB_2_DONE BIT(4)
> -
> -/**
> - * WDOG timer interrupt status bit definitions
> - */
> -#define DPU_INTR_WD_TIMER_0_DONE BIT(2)
> -#define DPU_INTR_WD_TIMER_1_DONE BIT(3)
> -#define DPU_INTR_WD_TIMER_2_DONE BIT(5)
> -#define DPU_INTR_WD_TIMER_3_DONE BIT(6)
> -#define DPU_INTR_WD_TIMER_4_DONE BIT(7)
> -
> -/**
> - * Pingpong interrupt status bit definitions
> - */
> -#define DPU_INTR_PING_PONG_0_DONE BIT(8)
> -#define DPU_INTR_PING_PONG_1_DONE BIT(9)
> -#define DPU_INTR_PING_PONG_2_DONE BIT(10)
> -#define DPU_INTR_PING_PONG_3_DONE BIT(11)
> -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12)
> -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13)
> -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14)
> -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15)
> -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16)
> -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17)
> -#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18)
> -#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19)
> -#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
> -#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
> -#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
> -#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23)
> -
> -/**
> - * Interface interrupt status bit definitions
> - */
> -#define DPU_INTR_INTF_0_UNDERRUN BIT(24)
> -#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
> -#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
> -#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
> -#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
> -#define DPU_INTR_INTF_0_VSYNC BIT(25)
> -#define DPU_INTR_INTF_1_VSYNC BIT(27)
> -#define DPU_INTR_INTF_2_VSYNC BIT(29)
> -#define DPU_INTR_INTF_3_VSYNC BIT(31)
> -#define DPU_INTR_INTF_5_VSYNC BIT(23)
> -
> -/**
> - * Pingpong Secondary interrupt status bit definitions
> - */
> -#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
> -#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4)
> -#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8)
> -#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
> -#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
> -
> -/**
> - * Pingpong TEAR detection interrupt status bit definitions
> - */
> -#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
> -#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
> -#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
> -#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
> -
> -/**
> - * Pingpong TE detection interrupt status bit definitions
> - */
> -#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24)
> -#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25)
> -#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26)
> -#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27)
> -
> -/**
> - * Ctl start interrupt status bit definitions
> - */
> -#define DPU_INTR_CTL_0_START BIT(9)
> -#define DPU_INTR_CTL_1_START BIT(10)
> -#define DPU_INTR_CTL_2_START BIT(11)
> -#define DPU_INTR_CTL_3_START BIT(12)
> -#define DPU_INTR_CTL_4_START BIT(13)
> -
> -/**
> - * Concurrent WB overflow interrupt status bit definitions
> - */
> -#define DPU_INTR_CWB_2_OVERFLOW BIT(14)
> -#define DPU_INTR_CWB_3_OVERFLOW BIT(15)
> -
> -/**
> - * Histogram VIG done interrupt status bit definitions
> - */
> -#define DPU_INTR_HIST_VIG_0_DONE BIT(0)
> -#define DPU_INTR_HIST_VIG_1_DONE BIT(4)
> -#define DPU_INTR_HIST_VIG_2_DONE BIT(8)
> -#define DPU_INTR_HIST_VIG_3_DONE BIT(10)
> -
> -/**
> - * Histogram VIG reset Sequence done interrupt status bit definitions
> - */
> -#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1)
> -#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5)
> -#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9)
> -#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11)
> -
> -/**
> - * Histogram DSPP done interrupt status bit definitions
> - */
> -#define DPU_INTR_HIST_DSPP_0_DONE BIT(12)
> -#define DPU_INTR_HIST_DSPP_1_DONE BIT(16)
> -#define DPU_INTR_HIST_DSPP_2_DONE BIT(20)
> -#define DPU_INTR_HIST_DSPP_3_DONE BIT(22)
> -
> -/**
> - * Histogram DSPP reset Sequence done interrupt status bit definitions
> - */
> -#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13)
> -#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17)
> -#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21)
> -#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23)
> -
> -/**
> - * INTF interrupt status bit definitions
> - */
> -#define DPU_INTR_VIDEO_INTO_STATIC BIT(0)
> -#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1)
> -#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2)
> -#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3)
> -#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4)
> -#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5)
> -#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6)
> -#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7)
> -#define DPU_INTR_PROG_LINE BIT(8)
> -
> -/**
> - * AD4 interrupt status bit definitions
> - */
> -#define DPU_INTR_BACKLIGHT_UPDATED BIT(0)
>  /**
>   * struct dpu_intr_reg - array of DPU register sets
>   * @clr_off:	offset to CLEAR reg
> @@ -180,20 +41,6 @@ struct dpu_intr_reg {
>  	u32 status_off;
>  };
> 
> -/**
> - * struct dpu_irq_type - maps each irq with i/f
> - * @intr_type:		type of interrupt listed in dpu_intr_type
> - * @instance_idx:	instance index of the associated HW block in DPU
> - * @irq_mask:		corresponding bit in the interrupt status reg
> - * @reg_idx:		which reg set to use
> - */
> -struct dpu_irq_type {
> -	u32 intr_type;
> -	u32 instance_idx;
> -	u32 irq_mask;
> -	u32 reg_idx;
> -};
> -
>  /*
>   * struct dpu_intr_reg -  List of DPU interrupt registers
>   *
> @@ -270,1086 +117,6 @@ static const struct dpu_intr_reg dpu_intr_set[] 
> = {
>  #define DPU_IRQ_REG(irq_idx)	(irq_idx / 32)
>  #define DPU_IRQ_MASK(irq_idx)	(BIT(irq_idx % 32))
> 
> -/*
> - * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx 
> in this
> - *			 table that have a matching interface type and
> - *			 instance index.
> - */
> -static const struct dpu_irq_type dpu_irq_map[] = {
> -	/* BEGIN MAP_RANGE: 0-31, INTR */
> -	/* irq_idx: 0-3 */
> -	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0},
> -	{ DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0},
> -	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0},
> -	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0},
> -	/* irq_idx: 4-7 */
> -	{ DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0},
> -	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0},
> -	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0},
> -	{ DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0},
> -	/* irq_idx: 8-11 */
> -	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_DONE, 0},
> -	/* irq_idx: 12-15 */
> -	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_RD_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_RD_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_RD_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_RD_PTR, 0},
> -	/* irq_idx: 16-19 */
> -	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_WR_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_WR_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_WR_PTR, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_WR_PTR, 0},
> -	/* irq_idx: 20-23 */
> -	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0},
> -	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0},
> -	/* irq_idx: 24-27 */
> -	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0},
> -	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0},
> -	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0},
> -	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0},
> -	/* irq_idx: 28-31 */
> -	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0},
> -	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
> -	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
> -	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
> -	/* irq_idx:32-33 */
> -	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
> -	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
> -	/* irq_idx:34-63 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
> -	/* BEGIN MAP_RANGE: 64-95, INTR2 */
> -	/* irq_idx: 64-67 */
> -	{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
> -		DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	/* irq_idx: 68-71 */
> -	{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
> -		DPU_INTR_PING_PONG_S0_WR_PTR, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	/* irq_idx: 72 */
> -	{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
> -		DPU_INTR_PING_PONG_S0_RD_PTR, 1},
> -	/* irq_idx: 73-77 */
> -	{ DPU_IRQ_TYPE_CTL_START, CTL_0,
> -		DPU_INTR_CTL_0_START, 1},
> -	{ DPU_IRQ_TYPE_CTL_START, CTL_1,
> -		DPU_INTR_CTL_1_START, 1},
> -	{ DPU_IRQ_TYPE_CTL_START, CTL_2,
> -		DPU_INTR_CTL_2_START, 1},
> -	{ DPU_IRQ_TYPE_CTL_START, CTL_3,
> -		DPU_INTR_CTL_3_START, 1},
> -	{ DPU_IRQ_TYPE_CTL_START, CTL_4,
> -		DPU_INTR_CTL_4_START, 1},
> -	/* irq_idx: 78-79 */
> -	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
> -	{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
> -	/* irq_idx: 80-83 */
> -	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
> -	/* irq_idx: 84-87 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
> -		DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	/* irq_idx: 88-91 */
> -	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
> -		DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
> -		DPU_INTR_PING_PONG_1_TE_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
> -		DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
> -		DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
> -	/* irq_idx: 92-95 */
> -	{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
> -		DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	/* irq_idx: 96-127 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
> -	/* BEGIN MAP_RANGE: 128-159 HIST */
> -	/* irq_idx: 128-131 */
> -	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 
> 2},
> -	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
> -		DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 132-135 */
> -	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 
> 2},
> -	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
> -		DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 136-139 */
> -	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 
> 2},
> -	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
> -		DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 
> 2},
> -	{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
> -		DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
> -	/* irq_idx: 140-143 */
> -	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
> -		DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 144-147 */
> -	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
> -		DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 148-151 */
> -	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
> -		DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
> -	{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
> -		DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
> -	/* irq_idx: 152-155 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 156-159 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* irq_idx: 160-191 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
> -	/* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
> -	/* irq_idx: 192-195 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
> -		DPU_INTR_VIDEO_INTO_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
> -	/* irq_idx: 196-199 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 3},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
> -	/* irq_idx: 200-203 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 204-207 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 208-211 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 212-215 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 216-219 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 220-223 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* irq_idx: 224-255 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
> -	/* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
> -	/* irq_idx: 256-259 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
> -		DPU_INTR_VIDEO_INTO_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
> -	/* irq_idx: 260-263 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 4},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
> -	/* irq_idx: 264-267 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 268-271 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 272-275 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 276-279 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 280-283 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 284-287 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* irq_idx: 288-319 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
> -	/* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
> -	/* irq_idx: 320-323 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
> -		DPU_INTR_VIDEO_INTO_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
> -	/* irq_idx: 324-327 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 5},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
> -	/* irq_idx: 328-331 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 332-335 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 336-339 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 340-343 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 344-347 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 348-351 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* irq_idx: 352-383 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
> -	/* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
> -	/* irq_idx: 384-387 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
> -		DPU_INTR_VIDEO_INTO_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
> -	/* irq_idx: 388-391 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 6},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
> -	/* irq_idx: 392-395 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 396-399 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 400-403 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 404-407 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 408-411 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 412-415 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* irq_idx: 416-447*/
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
> -	/* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
> -	/* irq_idx: 448-451 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
> -		DPU_INTR_VIDEO_INTO_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
> -	/* irq_idx: 452-455 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 7},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
> -	/* irq_idx: 456-459 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 460-463 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 464-467 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 468-471 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 472-475 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 476-479 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* irq_idx: 480-511 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
> -	/* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
> -	/* irq_idx: 512-515 */
> -	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 516-519 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 520-523 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 524-527 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 528-531 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 532-535 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 536-539 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 540-543 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* irq_idx: 544-575*/
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
> -	/* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
> -	/* irq_idx: 576-579 */
> -	{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 580-583 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 584-587 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 588-591 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 592-595 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 596-599 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 600-603 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 604-607 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* irq_idx: 608-639 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
> -	/* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
> -	/* irq_idx: 640-643 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
> -		DPU_INTR_VIDEO_INTO_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
> -	/* irq_idx: 644-647 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 10},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
> -	/* irq_idx: 648-651 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 652-655 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 656-659 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 660-663 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 664-667 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 668-671 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* irq_idx: 672-703 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
> -	/* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
> -	/* irq_idx: 704-707 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
> -		DPU_INTR_VIDEO_INTO_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
> -	/* irq_idx: 708-711 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 11},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
> -	/* irq_idx: 712-715 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 716-719 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 720-723 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 724-727 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 728-731 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 732-735 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* irq_idx: 736-767 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
> -	/* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
> -	/* irq_idx: 768-771 */
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
> -		DPU_INTR_VIDEO_INTO_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
> -		DPU_INTR_VIDEO_OUTOF_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
> -		DPU_INTR_DSICMD_0_INTO_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
> -		DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
> -	/* irq_idx: 772-775 */
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
> -		DPU_INTR_DSICMD_1_INTO_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
> -		DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
> -		DPU_INTR_DSICMD_2_INTO_STATIC, 12},
> -	{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
> -		DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
> -	/* irq_idx: 776-779 */
> -	{ DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 780-783 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 784-787 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 788-791 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 792-795 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 796-799 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	/* irq_idx: 800-831 */
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
> -};
> -
>  static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
> *intr,
>  		int irq_idx)
>  {
> @@ -1658,7 +425,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem 
> *addr,
>  	}
> 
>  	intr->irq_mask = m->mdss_irqs;
> -	intr->obsolete_irq = m->obsolete_irq;
> 
>  	spin_lock_init(&intr->irq_lock);
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index c6b3d373ce75..3c8b788d78e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -12,68 +12,6 @@
>  #include "dpu_hw_util.h"
>  #include "dpu_hw_mdss.h"
> 
> -/**
> - * dpu_intr_type - HW Interrupt Type
> - * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
> - * @DPU_IRQ_TYPE_WB_WFD_COMP:		WB WFD done
> - * @DPU_IRQ_TYPE_PING_PONG_COMP:	PingPong done
> - * @DPU_IRQ_TYPE_PING_PONG_RD_PTR:	PingPong read pointer
> - * @DPU_IRQ_TYPE_PING_PONG_WR_PTR:	PingPong write pointer
> - * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF:	PingPong auto refresh
> - * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK:	PingPong Tear check
> - * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK:	PingPong TE detection
> - * @DPU_IRQ_TYPE_INTF_UNDER_RUN:	INTF underrun
> - * @DPU_IRQ_TYPE_INTF_VSYNC:		INTF VSYNC
> - * @DPU_IRQ_TYPE_CWB_OVERFLOW:		Concurrent WB overflow
> - * @DPU_IRQ_TYPE_HIST_VIG_DONE:		VIG Histogram done
> - * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ:	VIG Histogram reset
> - * @DPU_IRQ_TYPE_HIST_DSPP_DONE:	DSPP Histogram done
> - * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ:	DSPP Histogram reset
> - * @DPU_IRQ_TYPE_WD_TIMER:		Watchdog timer
> - * @DPU_IRQ_TYPE_SFI_VIDEO_IN:		Video static frame INTR into static
> - * @DPU_IRQ_TYPE_SFI_VIDEO_OUT:		Video static frame INTR out-of static
> - * @DPU_IRQ_TYPE_SFI_CMD_0_IN:		DSI CMD0 static frame INTR into static
> - * @DPU_IRQ_TYPE_SFI_CMD_0_OUT:		DSI CMD0 static frame INTR out-of 
> static
> - * @DPU_IRQ_TYPE_SFI_CMD_1_IN:		DSI CMD1 static frame INTR into static
> - * @DPU_IRQ_TYPE_SFI_CMD_1_OUT:		DSI CMD1 static frame INTR out-of 
> static
> - * @DPU_IRQ_TYPE_SFI_CMD_2_IN:		DSI CMD2 static frame INTR into static
> - * @DPU_IRQ_TYPE_SFI_CMD_2_OUT:		DSI CMD2 static frame INTR out-of 
> static
> - * @DPU_IRQ_TYPE_PROG_LINE:		Programmable Line interrupt
> - * @DPU_IRQ_TYPE_AD4_BL_DONE:		AD4 backlight
> - * @DPU_IRQ_TYPE_CTL_START:		Control start
> - * @DPU_IRQ_TYPE_RESERVED:		Reserved for expansion
> - */
> -enum dpu_intr_type {
> -	DPU_IRQ_TYPE_WB_ROT_COMP,
> -	DPU_IRQ_TYPE_WB_WFD_COMP,
> -	DPU_IRQ_TYPE_PING_PONG_COMP,
> -	DPU_IRQ_TYPE_PING_PONG_RD_PTR,
> -	DPU_IRQ_TYPE_PING_PONG_WR_PTR,
> -	DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
> -	DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
> -	DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
> -	DPU_IRQ_TYPE_INTF_UNDER_RUN,
> -	DPU_IRQ_TYPE_INTF_VSYNC,
> -	DPU_IRQ_TYPE_CWB_OVERFLOW,
> -	DPU_IRQ_TYPE_HIST_VIG_DONE,
> -	DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
> -	DPU_IRQ_TYPE_HIST_DSPP_DONE,
> -	DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
> -	DPU_IRQ_TYPE_WD_TIMER,
> -	DPU_IRQ_TYPE_SFI_VIDEO_IN,
> -	DPU_IRQ_TYPE_SFI_VIDEO_OUT,
> -	DPU_IRQ_TYPE_SFI_CMD_0_IN,
> -	DPU_IRQ_TYPE_SFI_CMD_0_OUT,
> -	DPU_IRQ_TYPE_SFI_CMD_1_IN,
> -	DPU_IRQ_TYPE_SFI_CMD_1_OUT,
> -	DPU_IRQ_TYPE_SFI_CMD_2_IN,
> -	DPU_IRQ_TYPE_SFI_CMD_2_OUT,
> -	DPU_IRQ_TYPE_PROG_LINE,
> -	DPU_IRQ_TYPE_AD4_BL_DONE,
> -	DPU_IRQ_TYPE_CTL_START,
> -	DPU_IRQ_TYPE_RESERVED,
> -};
> -
>  /* When making changes be sure to sync with dpu_intr_set */
>  enum dpu_hw_intr_reg {
>  	MDP_SSPP_TOP0_INTR,
> @@ -172,7 +110,6 @@ struct dpu_hw_intr_ops {
>   * @save_irq_status:  array of IRQ status reg storage created during 
> init
>   * @total_irqs: total number of irq_idx mapped in the hw_interrupts
>   * @irq_lock:         spinlock for accessing IRQ resources
> - * @obsolete_irq:      irq types that are obsolete for a particular 
> target
>   */
>  struct dpu_hw_intr {
>  	struct dpu_hw_blk_reg_map hw;
> @@ -182,7 +119,6 @@ struct dpu_hw_intr {
>  	u32 total_irqs;
>  	spinlock_t irq_lock;
>  	unsigned long irq_mask;
> -	unsigned long obsolete_irq;
>  };
> 
>  /**

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling
  2021-05-16 20:29 ` [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling Dmitry Baryshkov
@ 2021-05-24 22:13   ` abhinavk
  0 siblings, 0 replies; 14+ messages in thread
From: abhinavk @ 2021-05-24 22:13 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 2021-05-16 13:29, Dmitry Baryshkov wrote:
> Merge dpu_core_irq_enable() into dpu_core_irq_register_callback() and
> dpu_core_irq_disable() into dpu_core_irq_unregister_callback(), because
> they are called in pairs. There is no need to have separate
> enable/disable pair, we can enable hardware IRQ when first callback is
> registered and when the last callback is unregistered.
> 
Since this change also removes the enable_counts atomic counter, I was a 
bit hesitant
because its helpful to protect against vblank discrepancies from 
usermode during enable/disable
but i think we have more protection for blank using vblank_refcount

413 	if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
414 		ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC);
415 	else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) 
== 0)
416 		ret = dpu_encoder_helper_unregister_irq(phys_enc,
417 				INTR_IDX_VSYNC);
418
419 end:

So this should still be okay. Hence
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 168 +++----------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h |  30 ----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  |  18 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h      |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h    |   8 -
>  5 files changed, 27 insertions(+), 199 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> index 11c0abed21ee..4f110c428b60 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
> @@ -26,10 +26,8 @@ static void dpu_core_irq_callback_handler(void
> *arg, int irq_idx)
> 
>  	pr_debug("irq_idx=%d\n", irq_idx);
> 
> -	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) {
> -		DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx,
> -			atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]));
> -	}
> +	if (list_empty(&irq_obj->irq_cb_tbl[irq_idx]))
> +		DRM_ERROR("no registered cb, idx:%d\n", irq_idx);
> 
>  	atomic_inc(&irq_obj->irq_counts[irq_idx]);
> 
> @@ -43,127 +41,6 @@ static void dpu_core_irq_callback_handler(void
> *arg, int irq_idx)
>  	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
>  }
> 
> -/**
> - * _dpu_core_irq_enable - enable core interrupt given by the index
> - * @dpu_kms:		Pointer to dpu kms context
> - * @irq_idx:		interrupt index
> - */
> -static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx)
> -{
> -	unsigned long irq_flags;
> -	int ret = 0, enable_count;
> -
> -	if (!dpu_kms->hw_intr ||
> -			!dpu_kms->irq_obj.enable_counts ||
> -			!dpu_kms->irq_obj.irq_counts) {
> -		DPU_ERROR("invalid params\n");
> -		return -EINVAL;
> -	}
> -
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> -		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> -		return -EINVAL;
> -	}
> -
> -	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
> -	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
> -	trace_dpu_core_irq_enable_idx(irq_idx, enable_count);
> -
> -	if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) 
> {
> -		ret = dpu_kms->hw_intr->ops.enable_irq(
> -				dpu_kms->hw_intr,
> -				irq_idx);
> -		if (ret)
> -			DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
> -					irq_idx);
> -
> -		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
> -
> -		spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
> -		/* empty callback list but interrupt is enabled */
> -		if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]))
> -			DPU_ERROR("irq_idx=%d enabled with no callback\n",
> -					irq_idx);
> -		spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
> -	}
> -
> -	return ret;
> -}
> -
> -int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 
> irq_count)
> -{
> -	int i, ret = 0, counts;
> -
> -	if (!irq_idxs || !irq_count) {
> -		DPU_ERROR("invalid params\n");
> -		return -EINVAL;
> -	}
> -
> -	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
> -	if (counts)
> -		DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
> -
> -	for (i = 0; (i < irq_count) && !ret; i++)
> -		ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]);
> -
> -	return ret;
> -}
> -
> -/**
> - * _dpu_core_irq_disable - disable core interrupt given by the index
> - * @dpu_kms:		Pointer to dpu kms context
> - * @irq_idx:		interrupt index
> - */
> -static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx)
> -{
> -	int ret = 0, enable_count;
> -
> -	if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) {
> -		DPU_ERROR("invalid params\n");
> -		return -EINVAL;
> -	}
> -
> -	if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
> -		DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
> -		return -EINVAL;
> -	}
> -
> -	enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]);
> -	DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count);
> -	trace_dpu_core_irq_disable_idx(irq_idx, enable_count);
> -
> -	if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) 
> {
> -		ret = dpu_kms->hw_intr->ops.disable_irq(
> -				dpu_kms->hw_intr,
> -				irq_idx);
> -		if (ret)
> -			DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
> -					irq_idx);
> -		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
> -	}
> -
> -	return ret;
> -}
> -
> -int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 
> irq_count)
> -{
> -	int i, ret = 0, counts;
> -
> -	if (!irq_idxs || !irq_count) {
> -		DPU_ERROR("invalid params\n");
> -		return -EINVAL;
> -	}
> -
> -	counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]);
> -	if (counts == 2)
> -		DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts);
> -
> -	for (i = 0; (i < irq_count) && !ret; i++)
> -		ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]);
> -
> -	return ret;
> -}
> -
>  u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool 
> clear)
>  {
>  	if (!dpu_kms->hw_intr ||
> @@ -210,6 +87,16 @@ int dpu_core_irq_register_callback(struct dpu_kms
> *dpu_kms, int irq_idx,
>  	list_del_init(&register_irq_cb->list);
>  	list_add_tail(&register_irq_cb->list,
>  			&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
> +	if (list_is_first(&register_irq_cb->list,
> +			&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
> +		int ret = dpu_kms->hw_intr->ops.enable_irq(
> +				dpu_kms->hw_intr,
> +				irq_idx);
> +		if (ret)
> +			DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
> +					irq_idx);
> +	}
> +
>  	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
> 
>  	return 0;
> @@ -244,9 +131,15 @@ int dpu_core_irq_unregister_callback(struct
> dpu_kms *dpu_kms, int irq_idx,
>  	trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
>  	list_del_init(&register_irq_cb->list);
>  	/* empty callback list but interrupt is still enabled */
> -	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) &&
> -			atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]))
> -		DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx);
> +	if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
> +		int ret = dpu_kms->hw_intr->ops.disable_irq(
> +				dpu_kms->hw_intr,
> +				irq_idx);
> +		if (ret)
> +			DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n",
> +					irq_idx);
> +		DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret);
> +	}
>  	spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
> 
>  	return 0;
> @@ -274,23 +167,22 @@ static int dpu_debugfs_core_irq_show(struct
> seq_file *s, void *v)
>  	struct dpu_irq *irq_obj = s->private;
>  	struct dpu_irq_callback *cb;
>  	unsigned long irq_flags;
> -	int i, irq_count, enable_count, cb_count;
> +	int i, irq_count, cb_count;
> 
> -	if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl))
> +	if (WARN_ON(!irq_obj->irq_cb_tbl))
>  		return 0;
> 
>  	for (i = 0; i < irq_obj->total_irqs; i++) {
>  		spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
>  		cb_count = 0;
>  		irq_count = atomic_read(&irq_obj->irq_counts[i]);
> -		enable_count = atomic_read(&irq_obj->enable_counts[i]);
>  		list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
>  			cb_count++;
>  		spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
> 
> -		if (irq_count || enable_count || cb_count)
> -			seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n",
> -					i, irq_count, enable_count, cb_count);
> +		if (irq_count || cb_count)
> +			seq_printf(s, "idx:%d irq:%d cb:%d\n",
> +					i, irq_count, cb_count);
>  	}
> 
>  	return 0;
> @@ -321,13 +213,10 @@ void dpu_core_irq_preinstall(struct dpu_kms 
> *dpu_kms)
>  	dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
>  	dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
>  			sizeof(struct list_head), GFP_KERNEL);
> -	dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
> -			sizeof(atomic_t), GFP_KERNEL);
>  	dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs,
>  			sizeof(atomic_t), GFP_KERNEL);
>  	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) {
>  		INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]);
> -		atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0);
>  		atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0);
>  	}
>  }
> @@ -338,8 +227,7 @@ void dpu_core_irq_uninstall(struct dpu_kms 
> *dpu_kms)
> 
>  	pm_runtime_get_sync(&dpu_kms->pdev->dev);
>  	for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++)
> -		if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) ||
> -				!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
> +		if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i]))
>  			DPU_ERROR("irq_idx=%d still enabled/registered\n", i);
> 
>  	dpu_clear_all_irqs(dpu_kms);
> @@ -347,10 +235,8 @@ void dpu_core_irq_uninstall(struct dpu_kms 
> *dpu_kms)
>  	pm_runtime_put_sync(&dpu_kms->pdev->dev);
> 
>  	kfree(dpu_kms->irq_obj.irq_cb_tbl);
> -	kfree(dpu_kms->irq_obj.enable_counts);
>  	kfree(dpu_kms->irq_obj.irq_counts);
>  	dpu_kms->irq_obj.irq_cb_tbl = NULL;
> -	dpu_kms->irq_obj.enable_counts = NULL;
>  	dpu_kms->irq_obj.irq_counts = NULL;
>  	dpu_kms->irq_obj.total_irqs = 0;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> index d147784d5531..90ae6c9ccc95 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
> @@ -29,36 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms 
> *dpu_kms);
>   */
>  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
> 
> -/**
> - * dpu_core_irq_enable - IRQ helper function for enabling one or more 
> IRQs
> - * @dpu_kms:		DPU handle
> - * @irq_idxs:		Array of irq index
> - * @irq_count:		Number of irq_idx provided in the array
> - * @return:		0 for success enabling IRQ, otherwise failure
> - *
> - * This function increments count on each enable and decrements on 
> each
> - * disable.  Interrupts is enabled if count is 0 before increment.
> - */
> -int dpu_core_irq_enable(
> -		struct dpu_kms *dpu_kms,
> -		int *irq_idxs,
> -		uint32_t irq_count);
> -
> -/**
> - * dpu_core_irq_disable - IRQ helper function for disabling one of 
> more IRQs
> - * @dpu_kms:		DPU handle
> - * @irq_idxs:		Array of irq index
> - * @irq_count:		Number of irq_idx provided in the array
> - * @return:		0 for success disabling IRQ, otherwise failure
> - *
> - * This function increments count on each enable and decrements on 
> each
> - * disable.  Interrupts is disabled if count is 0 after decrement.
> - */
> -int dpu_core_irq_disable(
> -		struct dpu_kms *dpu_kms,
> -		int *irq_idxs,
> -		uint32_t irq_count);
> -
>  /**
>   * dpu_core_irq_read - IRQ helper function for reading IRQ status
>   * @dpu_kms:		DPU handle
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 8a9d01e3b664..18c410433bb4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -360,17 +360,6 @@ int dpu_encoder_helper_register_irq(struct
> dpu_encoder_phys *phys_enc,
>  		return ret;
>  	}
> 
> -	ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
> -	if (ret) {
> -		DRM_ERROR("enable failed id=%u, intr=%d, irq=%d",
> -			  DRMID(phys_enc->parent), intr_idx,
> -			  irq->irq_idx);
> -		dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
> -				irq->irq_idx, &irq->cb);
> -		irq->irq_idx = -EINVAL;
> -		return ret;
> -	}
> -
>  	trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
>  				irq->irq_idx);
> 
> @@ -393,13 +382,6 @@ int dpu_encoder_helper_unregister_irq(struct
> dpu_encoder_phys *phys_enc,
>  		return 0;
>  	}
> 
> -	ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
> -	if (ret) {
> -		DRM_ERROR("disable failed id=%u, intr=%d, irq=%d ret=%d",
> -			  DRMID(phys_enc->parent), intr_idx,
> -			  irq->irq_idx, ret);
> -	}
> -
>  	ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 
> irq->irq_idx,
>  			&irq->cb);
>  	if (ret) {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index d6717d6672f7..f6840b1af6e4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -82,14 +82,12 @@ struct dpu_irq_callback {
>   * struct dpu_irq: IRQ structure contains callback registration info
>   * @total_irq:    total number of irq_idx obtained from HW interrupts 
> mapping
>   * @irq_cb_tbl:   array of IRQ callbacks setting
> - * @enable_counts array of IRQ enable counts
>   * @cb_lock:      callback lock
>   * @debugfs_file: debugfs file for irq statistics
>   */
>  struct dpu_irq {
>  	u32 total_irqs;
>  	struct list_head *irq_cb_tbl;
> -	atomic_t *enable_counts;
>  	atomic_t *irq_counts;
>  	spinlock_t cb_lock;
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index e349ea78a49d..00b43959f631 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -891,14 +891,6 @@ DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
>  	TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
>  		  __entry->enable_count)
>  );
> -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
> -	TP_PROTO(int irq_idx, int enable_count),
> -	TP_ARGS(irq_idx, enable_count)
> -);
> -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
> -	TP_PROTO(int irq_idx, int enable_count),
> -	TP_ARGS(irq_idx, enable_count)
> -);
> 
>  DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
>  	TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Freedreno] [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog
  2021-05-24 21:57   ` [Freedreno] " abhinavk
@ 2021-05-26  2:09     ` Dmitry Baryshkov
  0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2021-05-26  2:09 UTC (permalink / raw)
  To: abhinavk
  Cc: Bjorn Andersson, Rob Clark, Sean Paul, Jonathan Marek,
	Stephen Boyd, linux-arm-msm, dri-devel, David Airlie,
	Daniel Vetter, freedreno

On 25/05/2021 00:57, abhinavk@codeaurora.org wrote:
> On 2021-05-16 13:29, Dmitry Baryshkov wrote:
>> The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to
>> maintain. There are only few interrupts used from that table. Newer
>> generations use different IRQ locations. Move this data to hw catalog.
>>
> I think you can drop the line that "only few interrupts ..." are used as 
> that
> was specific to sc7280 as you mentioned on IRC or give the example of 
> sc7280
> here to explain that as being one of the motivations for this cleanup.

I've had this before sc7280 (but it intensified the necessity for these 
changes). Regarding "only few", e.g. DSPP, VIG, PP_WR_PTR, 
PP_AUTOREFRESH interrupts are not used.

> 
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> With that fixed, I think this cleanup looks quite reasonable to me.
> I computed a few of the intr offsets and the values were matching the 
> prev hard-coded
> offsets. Since I dont have the sc7280 HW to test this, I am checking if 
> someone with that
> hw in our team can test it out as well to make sure that it covers that 
> hw as well.
> 
> But otherwise,
> 
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c  |  20 +--
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h  |  13 --
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  64 +++-----
>>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |   2 -
>>  .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  |  36 ++---
>>  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |  31 +---
>>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 150 +++++++++++-------
>>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  12 +-
>>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 137 +++++++---------
>>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  17 +-
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h     |  28 ++--
>>  11 files changed, 229 insertions(+), 281 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
>> index fd11a2aeab6c..11c0abed21ee 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
>> @@ -43,16 +43,6 @@ static void dpu_core_irq_callback_handler(void
>> *arg, int irq_idx)
>>      spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
>>  }
>>
>> -int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms,
>> -        enum dpu_intr_type intr_type, u32 instance_idx)
>> -{
>> -    if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup)
>> -        return -EINVAL;
>> -
>> -    return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr,
>> -            intr_type, instance_idx);
>> -}
>> -
>>  /**
>>   * _dpu_core_irq_enable - enable core interrupt given by the index
>>   * @dpu_kms:        Pointer to dpu kms context
>> @@ -70,7 +60,7 @@ static int _dpu_core_irq_enable(struct dpu_kms
>> *dpu_kms, int irq_idx)
>>          return -EINVAL;
>>      }
>>
>> -    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
>> +    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>>          DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>> @@ -133,7 +123,7 @@ static int _dpu_core_irq_disable(struct dpu_kms
>> *dpu_kms, int irq_idx)
>>          return -EINVAL;
>>      }
>>
>> -    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
>> +    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>>          DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>> @@ -208,7 +198,7 @@ int dpu_core_irq_register_callback(struct dpu_kms
>> *dpu_kms, int irq_idx,
>>          return -EINVAL;
>>      }
>>
>> -    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
>> +    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>>          DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>> @@ -243,7 +233,7 @@ int dpu_core_irq_unregister_callback(struct
>> dpu_kms *dpu_kms, int irq_idx,
>>          return -EINVAL;
>>      }
>>
>> -    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) {
>> +    if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) {
>>          DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>> @@ -328,7 +318,7 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
>>      spin_lock_init(&dpu_kms->irq_obj.cb_lock);
>>
>>      /* Create irq callbacks for all possible irq_idx */
>> -    dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size;
>> +    dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
>>      dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
>>              sizeof(struct list_head), GFP_KERNEL);
>>      dpu_kms->irq_obj.enable_counts = 
>> kcalloc(dpu_kms->irq_obj.total_irqs,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
>> index e30775e6585b..d147784d5531 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
>> @@ -29,19 +29,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms);
>>   */
>>  irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms);
>>
>> -/**
>> - * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx 
>> from HW
>> - *                      interrupt mapping table.
>> - * @dpu_kms:        DPU handle
>> - * @intr_type:        DPU HW interrupt type for lookup
>> - * @instance_idx:    DPU HW block instance defined in dpu_hw_mdss.h
>> - * @return:        irq_idx or -EINVAL when fail to lookup
>> - */
>> -int dpu_core_irq_idx_lookup(
>> -        struct dpu_kms *dpu_kms,
>> -        enum dpu_intr_type intr_type,
>> -        uint32_t instance_idx);
>> -
>>  /**
>>   * dpu_core_irq_enable - IRQ helper function for enabling one or more 
>> IRQs
>>   * @dpu_kms:        DPU handle
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 8d942052db8a..8a9d01e3b664 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -253,7 +253,7 @@ void dpu_encoder_helper_report_irq_timeout(struct
>> dpu_encoder_phys *phys_enc,
>>  }
>>
>>  static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
>> -        int32_t hw_id, struct dpu_encoder_wait_info *info);
>> +        u32 irq_idx, struct dpu_encoder_wait_info *info);
>>
>>  int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
>>          enum dpu_intr_idx intr_idx,
>> @@ -273,27 +273,27 @@ int dpu_encoder_helper_wait_for_irq(struct
>> dpu_encoder_phys *phys_enc,
>>
>>      /* return EWOULDBLOCK since we know the wait isn't necessary */
>>      if (phys_enc->enable_state == DPU_ENC_DISABLED) {
>> -        DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx);
>>          return -EWOULDBLOCK;
>>      }
>>
>>      if (irq->irq_idx < 0) {
>> -        DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s",
>> -                  DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
>> +                  DRMID(phys_enc->parent), intr_idx,
>>                    irq->name);
>>          return 0;
>>      }
>>
>> -    DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, 
>> pending_cnt=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +    DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
>>                atomic_read(wait_info->atomic_cnt));
>>
>>      ret = dpu_encoder_helper_wait_event_timeout(
>>              DRMID(phys_enc->parent),
>> -            irq->hw_idx,
>> +            irq->irq_idx,
>>              wait_info);
>>
>>      if (ret <= 0) {
>> @@ -303,9 +303,9 @@ int dpu_encoder_helper_wait_for_irq(struct
>> dpu_encoder_phys *phys_enc,
>>              unsigned long flags;
>>
>>              DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
>> -                      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
>> +                      "irq=%d, pp=%d, atomic_cnt=%d",
>>                        DRMID(phys_enc->parent), intr_idx,
>> -                      irq->hw_idx, irq->irq_idx,
>> +                      irq->irq_idx,
>>                        phys_enc->hw_pp->idx - PINGPONG_0,
>>                        atomic_read(wait_info->atomic_cnt));
>>              local_irq_save(flags);
>> @@ -315,16 +315,16 @@ int dpu_encoder_helper_wait_for_irq(struct
>> dpu_encoder_phys *phys_enc,
>>          } else {
>>              ret = -ETIMEDOUT;
>>              DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
>> -                      "hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
>> +                      "irq=%d, pp=%d, atomic_cnt=%d",
>>                        DRMID(phys_enc->parent), intr_idx,
>> -                      irq->hw_idx, irq->irq_idx,
>> +                      irq->irq_idx,
>>                        phys_enc->hw_pp->idx - PINGPONG_0,
>>                        atomic_read(wait_info->atomic_cnt));
>>          }
>>      } else {
>>          ret = 0;
>>          trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
>> -            intr_idx, irq->hw_idx, irq->irq_idx,
>> +            intr_idx, irq->irq_idx,
>>              phys_enc->hw_pp->idx - PINGPONG_0,
>>              atomic_read(wait_info->atomic_cnt));
>>      }
>> @@ -344,19 +344,9 @@ int dpu_encoder_helper_register_irq(struct
>> dpu_encoder_phys *phys_enc,
>>      }
>>      irq = &phys_enc->irq[intr_idx];
>>
>> -    if (irq->irq_idx >= 0) {
>> -        DPU_DEBUG_PHYS(phys_enc,
>> -                "skipping already registered irq %s type %d\n",
>> -                irq->name, irq->intr_type);
>> -        return 0;
>> -    }
>> -
>> -    irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms,
>> -            irq->intr_type, irq->hw_idx);
>>      if (irq->irq_idx < 0) {
>>          DPU_ERROR_PHYS(phys_enc,
>> -            "failed to lookup IRQ index for %s type:%d\n",
>> -            irq->name, irq->intr_type);
>> +            "invalid IRQ index:%d\n", irq->irq_idx);
>>          return -EINVAL;
>>      }
>>
>> @@ -372,8 +362,8 @@ int dpu_encoder_helper_register_irq(struct
>> dpu_encoder_phys *phys_enc,
>>
>>      ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1);
>>      if (ret) {
>> -        DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_ERROR("enable failed id=%u, intr=%d, irq=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx);
>>          dpu_core_irq_unregister_callback(phys_enc->dpu_kms,
>>                  irq->irq_idx, &irq->cb);
>> @@ -382,7 +372,7 @@ int dpu_encoder_helper_register_irq(struct
>> dpu_encoder_phys *phys_enc,
>>      }
>>
>>      trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), 
>> intr_idx,
>> -                irq->hw_idx, irq->irq_idx);
>> +                irq->irq_idx);
>>
>>      return ret;
>>  }
>> @@ -397,31 +387,29 @@ int dpu_encoder_helper_unregister_irq(struct
>> dpu_encoder_phys *phys_enc,
>>
>>      /* silently skip irqs that weren't registered */
>>      if (irq->irq_idx < 0) {
>> -        DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx);
>>          return 0;
>>      }
>>
>>      ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1);
>>      if (ret) {
>> -        DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_ERROR("disable failed id=%u, intr=%d, irq=%d ret=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx, ret);
>>      }
>>
>>      ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 
>> irq->irq_idx,
>>              &irq->cb);
>>      if (ret) {
>> -        DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d",
>> -              DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
>> +        DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
>> +              DRMID(phys_enc->parent), intr_idx,
>>                irq->irq_idx, ret);
>>      }
>>
>>      trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), 
>> intr_idx,
>> -                         irq->hw_idx, irq->irq_idx);
>> -
>> -    irq->irq_idx = -EINVAL;
>> +                         irq->irq_idx);
>>
>>      return 0;
>>  }
>> @@ -1537,7 +1525,7 @@ void dpu_encoder_helper_trigger_start(struct
>> dpu_encoder_phys *phys_enc)
>>
>>  static int dpu_encoder_helper_wait_event_timeout(
>>          int32_t drm_id,
>> -        int32_t hw_id,
>> +        u32 irq_idx,
>>          struct dpu_encoder_wait_info *info)
>>  {
>>      int rc = 0;
>> @@ -1550,7 +1538,7 @@ static int dpu_encoder_helper_wait_event_timeout(
>>                  atomic_read(info->atomic_cnt) == 0, jiffies);
>>          time = ktime_to_ms(ktime_get());
>>
>> -        trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time,
>> +        trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
>>                           expected_time,
>>                           atomic_read(info->atomic_cnt));
>>      /* If we timed out, counter is valid and time is less, wait again */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> index ecbc4be98980..3bd12ce45a80 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> @@ -167,7 +167,6 @@ enum dpu_intr_idx {
>>   * @name:        string name of interrupt
>>   * @intr_type:        Encoder interrupt type
>>   * @intr_idx:        Encoder interrupt enumeration
>> - * @hw_idx:        HW Block ID
>>   * @irq_idx:        IRQ interface lookup index from DPU IRQ framework
>>   *            will be -EINVAL if IRQ is not registered
>>   * @irq_cb:        interrupt callback
>> @@ -176,7 +175,6 @@ struct dpu_encoder_irq {
>>      const char *name;
>>      enum dpu_intr_type intr_type;
>>      enum dpu_intr_idx intr_idx;
>> -    int hw_idx;
>>      int irq_idx;
>>      struct dpu_irq_callback cb;
>>  };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> index b2be39b9144e..6f06e379b97f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> @@ -143,28 +143,6 @@ static void
>> dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
>>              phys_enc);
>>  }
>>
>> -static void _dpu_encoder_phys_cmd_setup_irq_hw_idx(
>> -        struct dpu_encoder_phys *phys_enc)
>> -{
>> -    struct dpu_encoder_irq *irq;
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_CTL_START];
>> -    irq->hw_idx = phys_enc->hw_ctl->idx;
>> -    irq->irq_idx = -EINVAL;
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_PINGPONG];
>> -    irq->hw_idx = phys_enc->hw_pp->idx;
>> -    irq->irq_idx = -EINVAL;
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_RDPTR];
>> -    irq->hw_idx = phys_enc->hw_pp->idx;
>> -    irq->irq_idx = -EINVAL;
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>> -    irq->hw_idx = phys_enc->intf_idx;
>> -    irq->irq_idx = -EINVAL;
>> -}
>> -
>>  static void dpu_encoder_phys_cmd_mode_set(
>>          struct dpu_encoder_phys *phys_enc,
>>          struct drm_display_mode *mode,
>> @@ -172,6 +150,7 @@ static void dpu_encoder_phys_cmd_mode_set(
>>  {
>>      struct dpu_encoder_phys_cmd *cmd_enc =
>>          to_dpu_encoder_phys_cmd(phys_enc);
>> +    struct dpu_encoder_irq *irq;
>>
>>      if (!mode || !adj_mode) {
>>          DPU_ERROR("invalid args\n");
>> @@ -181,7 +160,17 @@ static void dpu_encoder_phys_cmd_mode_set(
>>      DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
>>      drm_mode_debug_printmodeline(adj_mode);
>>
>> -    _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
>> +    irq = &phys_enc->irq[INTR_IDX_CTL_START];
>> +    irq->irq_idx = phys_enc->hw_ctl->caps->intr_start;
>> +
>> +    irq = &phys_enc->irq[INTR_IDX_PINGPONG];
>> +    irq->irq_idx = phys_enc->hw_pp->caps->intr_done;
>> +
>> +    irq = &phys_enc->irq[INTR_IDX_RDPTR];
>> +    irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr;
>> +
>> +    irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>> +    irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
>>  }
>>
>>  static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
>> @@ -795,7 +784,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
>>          irq = &phys_enc->irq[i];
>>          INIT_LIST_HEAD(&irq->cb.list);
>>          irq->irq_idx = -EINVAL;
>> -        irq->hw_idx = -EINVAL;
>>          irq->cb.arg = phys_enc;
>>      }
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> index 0e06b7e73c7a..6cdb4ecbc173 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> @@ -363,38 +363,24 @@ static bool 
>> dpu_encoder_phys_vid_needs_single_flush(
>>      return phys_enc->split_role != ENC_ROLE_SOLO;
>>  }
>>
>> -static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
>> -        struct dpu_encoder_phys *phys_enc)
>> -{
>> -    struct dpu_encoder_irq *irq;
>> -
>> -    /*
>> -     * Initialize irq->hw_idx only when irq is not registered.
>> -     * Prevent invalidating irq->irq_idx as modeset may be
>> -     * called many times during dfps.
>> -     */
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_VSYNC];
>> -    if (irq->irq_idx < 0)
>> -        irq->hw_idx = phys_enc->intf_idx;
>> -
>> -    irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>> -    if (irq->irq_idx < 0)
>> -        irq->hw_idx = phys_enc->intf_idx;
>> -}
>> -
>>  static void dpu_encoder_phys_vid_mode_set(
>>          struct dpu_encoder_phys *phys_enc,
>>          struct drm_display_mode *mode,
>>          struct drm_display_mode *adj_mode)
>>  {
>> +    struct dpu_encoder_irq *irq;
>> +
>>      if (adj_mode) {
>>          phys_enc->cached_mode = *adj_mode;
>>          drm_mode_debug_printmodeline(adj_mode);
>>          DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n");
>>      }
>>
>> -    _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
>> +    irq = &phys_enc->irq[INTR_IDX_VSYNC];
>> +    irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync;
>> +
>> +    irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
>> +    irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun;
>>  }
>>
>>  static int dpu_encoder_phys_vid_control_vblank_irq(
>> @@ -636,7 +622,7 @@ static void
>> dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
>>
>>      if (enable) {
>>          ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true);
>> -        if (ret)
>> +        if (WARN_ON(ret))
>>              return;
>>
>>          dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN);
>> @@ -738,7 +724,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
>>          irq = &phys_enc->irq[i];
>>          INIT_LIST_HEAD(&irq->cb.list);
>>          irq->irq_idx = -EINVAL;
>> -        irq->hw_idx = -EINVAL;
>>          irq->cb.arg = phys_enc;
>>      }
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 9a77d64d3fd4..f929131ed260 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -350,27 +350,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
>>      {
>>      .name = "ctl_0", .id = CTL_0,
>>      .base = 0x1000, .len = 0xE4,
>> -    .features = BIT(DPU_CTL_SPLIT_DISPLAY)
>> +    .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>>      },
>>      {
>>      .name = "ctl_1", .id = CTL_1,
>>      .base = 0x1200, .len = 0xE4,
>> -    .features = BIT(DPU_CTL_SPLIT_DISPLAY)
>> +    .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>>      },
>>      {
>>      .name = "ctl_2", .id = CTL_2,
>>      .base = 0x1400, .len = 0xE4,
>> -    .features = 0
>> +    .features = 0,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>>      },
>>      {
>>      .name = "ctl_3", .id = CTL_3,
>>      .base = 0x1600, .len = 0xE4,
>> -    .features = 0
>> +    .features = 0,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>>      },
>>      {
>>      .name = "ctl_4", .id = CTL_4,
>>      .base = 0x1800, .len = 0xE4,
>> -    .features = 0
>> +    .features = 0,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>>      },
>>  };
>>
>> @@ -378,17 +383,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
>>      {
>>      .name = "ctl_0", .id = CTL_0,
>>      .base = 0x1000, .len = 0xE4,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>>      },
>>      {
>>      .name = "ctl_1", .id = CTL_1,
>>      .base = 0x1200, .len = 0xE4,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>>      },
>>      {
>>      .name = "ctl_2", .id = CTL_2,
>>      .base = 0x1400, .len = 0xE4,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>>      },
>>  };
>>
>> @@ -396,32 +404,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
>>      {
>>      .name = "ctl_0", .id = CTL_0,
>>      .base = 0x1000, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>>      },
>>      {
>>      .name = "ctl_1", .id = CTL_1,
>>      .base = 0x1200, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>>      },
>>      {
>>      .name = "ctl_2", .id = CTL_2,
>>      .base = 0x1400, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>>      },
>>      {
>>      .name = "ctl_3", .id = CTL_3,
>>      .base = 0x1600, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>>      },
>>      {
>>      .name = "ctl_4", .id = CTL_4,
>>      .base = 0x1800, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>>      },
>>      {
>>      .name = "ctl_5", .id = CTL_5,
>>      .base = 0x1a00, .len = 0x1e0,
>> -    .features = BIT(DPU_CTL_ACTIVE_CFG)
>> +    .features = BIT(DPU_CTL_ACTIVE_CFG),
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>>      },
>>  };
>>
>> @@ -429,22 +443,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
>>      {
>>      .name = "ctl_0", .id = CTL_0,
>>      .base = 0x15000, .len = 0x1E8,
>> -    .features = CTL_SC7280_MASK
>> +    .features = CTL_SC7280_MASK,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>>      },
>>      {
>>      .name = "ctl_1", .id = CTL_1,
>>      .base = 0x16000, .len = 0x1E8,
>> -    .features = CTL_SC7280_MASK
>> +    .features = CTL_SC7280_MASK,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>>      },
>>      {
>>      .name = "ctl_2", .id = CTL_2,
>>      .base = 0x17000, .len = 0x1E8,
>> -    .features = CTL_SC7280_MASK
>> +    .features = CTL_SC7280_MASK,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>>      },
>>      {
>>      .name = "ctl_3", .id = CTL_3,
>>      .base = 0x18000, .len = 0x1E8,
>> -    .features = CTL_SC7280_MASK
>> +    .features = CTL_SC7280_MASK,
>> +    .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>>      },
>>  };
>>
>> @@ -725,42 +743,66 @@ static const struct dpu_pingpong_sub_blks
>> sc7280_pp_sblk = {
>>      .len = 0x20, .version = 0x20000},
>>  };
>>
>> -#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \
>> +#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>>      {\
>>      .name = _name, .id = _id, \
>>      .base = _base, .len = 0xd4, \
>>      .features = PINGPONG_SDM845_SPLIT_MASK, \
>>      .merge_3d = _merge_3d, \
>> -    .sblk = &_sblk \
>> +    .sblk = &_sblk, \
>> +    .intr_done = _done, \
>> +    .intr_rdptr = _rdptr, \
>>      }
>> -#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \
>> +#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
>>      {\
>>      .name = _name, .id = _id, \
>>      .base = _base, .len = 0xd4, \
>>      .features = PINGPONG_SDM845_MASK, \
>>      .merge_3d = _merge_3d, \
>> -    .sblk = &_sblk \
>> +    .sblk = &_sblk, \
>> +    .intr_done = _done, \
>> +    .intr_rdptr = _rdptr, \
>>      }
>>
>>  static const struct dpu_pingpong_cfg sdm845_pp[] = {
>> -    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
>> -    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
>> -    PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk),
>> -    PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk),
>> +    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
>> +    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
>> +    PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
>> +    PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
>>  };
>>
>>  static struct dpu_pingpong_cfg sc7180_pp[] = {
>> -    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te),
>> -    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te),
>> +    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, 
>> sdm845_pp_sblk_te, -1, -1),
>> +    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, 
>> sdm845_pp_sblk_te, -1, -1),
>>  };
>>
>>  static const struct dpu_pingpong_cfg sm8150_pp[] = {
>> -    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, 
>> sdm845_pp_sblk_te),
>> -    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, 
>> sdm845_pp_sblk_te),
>> -    PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, 
>> sdm845_pp_sblk),
>> -    PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, 
>> sdm845_pp_sblk),
>> -    PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, 
>> sdm845_pp_sblk),
>> -    PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, 
>> sdm845_pp_sblk),
>> +    PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, 
>> sdm845_pp_sblk_te,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
>> +    PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, 
>> sdm845_pp_sblk_te,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
>> +    PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, 
>> sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
>> +    PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, 
>> sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
>> +    PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, 
>> sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
>> +            -1),
>> +    PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, 
>> sdm845_pp_sblk,
>> +            DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
>> +            -1),
>>  };
>>
>>  /*************************************************************
>> @@ -781,47 +823,49 @@ static const struct dpu_merge_3d_cfg 
>> sm8150_merge_3d[] = {
>>  };
>>
>>  static const struct dpu_pingpong_cfg sc7280_pp[] = {
>> -    PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk),
>> -    PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk),
>> -    PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk),
>> -    PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk),
>> +    PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, 
>> -1),
>> +    PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, 
>> -1),
>> +    PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, 
>> -1),
>> +    PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, 
>> -1),
>>  };
>>  /*************************************************************
>>   * INTF sub blocks config
>>   *************************************************************/
>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, 
>> _features) \
>> +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch,
>> _features, _reg, _underrun_bit, _vsync_bit) \
>>      {\
>>      .name = _name, .id = _id, \
>>      .base = _base, .len = 0x280, \
>>      .features = _features, \
>>      .type = _type, \
>>      .controller_id = _ctrl_id, \
>> -    .prog_fetch_lines_worst_case = _progfetch \
>> +    .prog_fetch_lines_worst_case = _progfetch, \
>> +    .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
>> +    .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
>>      }
>>
>>  static const struct dpu_intf_cfg sdm845_intf[] = {
>> -    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
>> INTF_SDM845_MASK),
>> -    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
>> INTF_SDM845_MASK),
>> -    INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, 
>> INTF_SDM845_MASK),
>> -    INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, 
>> INTF_SDM845_MASK),
>> +    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
>> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> +    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
>> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> +    INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24,
>> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> +    INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24,
>> INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>>  };
>>
>>  static const struct dpu_intf_cfg sc7180_intf[] = {
>> -    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
>> INTF_SC7180_MASK),
>> -    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
>> INTF_SC7180_MASK),
>> +    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> +    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>>  };
>>
>>  static const struct dpu_intf_cfg sm8150_intf[] = {
>> -    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, 
>> INTF_SC7180_MASK),
>> -    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, 
>> INTF_SC7180_MASK),
>> -    INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, 
>> INTF_SC7180_MASK),
>> -    INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, 
>> INTF_SC7180_MASK),
>> +    INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> +    INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> +    INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
>> +    INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24,
>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
>>  };
>>
>>  static const struct dpu_intf_cfg sc7280_intf[] = {
>> -    INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, 
>> INTF_SC7280_MASK),
>> -    INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, 
>> INTF_SC7280_MASK),
>> -    INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, 
>> INTF_SC7280_MASK),
>> +    INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24,
>> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
>> +    INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24,
>> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
>> +    INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24,
>> INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
>>  };
>>
>>  /*************************************************************
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 4dfd8a20ad5c..316da2971320 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -464,13 +464,15 @@ struct dpu_mdp_cfg {
>>      struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
>>  };
>>
>> -/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
>> +/* struct dpu_ctl_cfg : MDP CTL instance info
>>   * @id:                index identifying this block
>>   * @base:              register base offset to mdss
>>   * @features           bit mask identifying sub-blocks/features
>> + * @intr_start:        interrupt index for CTL_START
>>   */
>>  struct dpu_ctl_cfg {
>>      DPU_HW_BLK_INFO;
>> +    s32 intr_start;
>>  };
>>
>>  /**
>> @@ -526,11 +528,15 @@ struct dpu_dspp_cfg  {
>>   * @id                 enum identifying this block
>>   * @base               register offset of this block
>>   * @features           bit mask identifying sub-blocks/features
>> + * @intr_done:         index for PINGPONG done interrupt
>> + * @intr_rdptr:        index for PINGPONG readpointer done interrupt
>>   * @sblk               sub-blocks information
>>   */
>>  struct dpu_pingpong_cfg  {
>>      DPU_HW_BLK_INFO;
>>      u32 merge_3d;
>> +    s32 intr_done;
>> +    s32 intr_rdptr;
>>      const struct dpu_pingpong_sub_blks *sblk;
>>  };
>>
>> @@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg  {
>>   * @type:              Interface type(DSI, DP, HDMI)
>>   * @controller_id:     Controller Instance ID in case of multiple of 
>> intf type
>>   * @prog_fetch_lines_worst_case    Worst case latency num lines 
>> needed to prefetch
>> + * @intr_underrun:    index for INTF underrun interrupt
>> + * @intr_vsync:            index for INTF VSYNC interrupt
>>   */
>>  struct dpu_intf_cfg  {
>>      DPU_HW_BLK_INFO;
>>      u32 type;   /* interface type*/
>>      u32 controller_id;
>>      u32 prog_fetch_lines_worst_case;
>> +    s32 intr_underrun;
>> +    s32 intr_vsync;
>>  };
>>
>>  /**
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>> index 8bd22e060437..adc1f04ac257 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>> @@ -196,6 +196,8 @@ struct dpu_irq_type {
>>
>>  /*
>>   * struct dpu_intr_reg -  List of DPU interrupt registers
>> + *
>> + * When making changes be sure to sync with dpu_hw_intr_reg
>>   */
>>  static const struct dpu_intr_reg dpu_intr_set[] = {
>>      {
>> @@ -265,6 +267,9 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>>      },
>>  };
>>
>> +#define DPU_IRQ_REG(irq_idx)    (irq_idx / 32)
>> +#define DPU_IRQ_MASK(irq_idx)    (BIT(irq_idx % 32))
>> +
>>  /*
>>   * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx 
>> in this
>>   *             table that have a matching interface type and
>> @@ -1345,23 +1350,6 @@ static const struct dpu_irq_type dpu_irq_map[] = {
>>      { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
>>  };
>>
>> -static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
>> -    enum dpu_intr_type intr_type, u32 instance_idx)
>> -{
>> -    int i;
>> -
>> -    for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
>> -        if (intr_type == dpu_irq_map[i].intr_type &&
>> -            instance_idx == dpu_irq_map[i].instance_idx &&
>> -            !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
>> -            return i;
>> -    }
>> -
>> -    pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n",
>> -            intr_type, instance_idx);
>> -    return -EINVAL;
>> -}
>> -
>>  static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr 
>> *intr,
>>          int irq_idx)
>>  {
>> @@ -1370,9 +1358,8 @@ static void
>> dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr,
>>      if (!intr)
>>          return;
>>
>> -    reg_idx = dpu_irq_map[irq_idx].reg_idx;
>> -    DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>> -            dpu_irq_map[irq_idx].irq_mask);
>> +    reg_idx = DPU_IRQ_REG(irq_idx);
>> +    DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>> DPU_IRQ_MASK(irq_idx));
>>
>>      /* ensure register writes go through */
>>      wmb();
>> @@ -1384,10 +1371,9 @@ static void dpu_hw_intr_dispatch_irq(struct
>> dpu_hw_intr *intr,
>>  {
>>      int reg_idx;
>>      int irq_idx;
>> -    int start_idx;
>> -    int end_idx;
>>      u32 irq_status;
>>      u32 enable_mask;
>> +    int bit;
>>      unsigned long irq_flags;
>>
>>      if (!intr)
>> @@ -1400,15 +1386,7 @@ static void dpu_hw_intr_dispatch_irq(struct
>> dpu_hw_intr *intr,
>>       */
>>      spin_lock_irqsave(&intr->irq_lock, irq_flags);
>>      for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
>> -        /*
>> -         * Each Interrupt register has a range of 64 indexes, and
>> -         * that is static for dpu_irq_map.
>> -         */
>> -        start_idx = reg_idx * 64;
>> -        end_idx = start_idx + 64;
>> -
>> -        if (!test_bit(reg_idx, &intr->irq_mask) ||
>> -            start_idx >= ARRAY_SIZE(dpu_irq_map))
>> +        if (!test_bit(reg_idx, &intr->irq_mask))
>>              continue;
>>
>>          /* Read interrupt status */
>> @@ -1425,37 +1403,33 @@ static void dpu_hw_intr_dispatch_irq(struct
>> dpu_hw_intr *intr,
>>          /* Finally update IRQ status based on enable mask */
>>          irq_status &= enable_mask;
>>
>> +        if (!irq_status)
>> +            continue;
>> +
>>          /*
>> -         * Search through matching intr status from irq map.
>> -         * start_idx and end_idx defined the search range in
>> -         * the dpu_irq_map.
>> +         * Search through matching intr status.
>>           */
>> -        for (irq_idx = start_idx;
>> -                (irq_idx < end_idx) && irq_status;
>> -                irq_idx++)
>> -            if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
>> -                (dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
>> -                !(intr->obsolete_irq &
>> -                BIT(dpu_irq_map[irq_idx].intr_type))) {
>> -                /*
>> -                 * Once a match on irq mask, perform a callback
>> -                 * to the given cbfunc. cbfunc will take care
>> -                 * the interrupt status clearing. If cbfunc is
>> -                 * not provided, then the interrupt clearing
>> -                 * is here.
>> -                 */
>> -                if (cbfunc)
>> -                    cbfunc(arg, irq_idx);
>> -
>> -                dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
>> -
>> -                /*
>> -                 * When callback finish, clear the irq_status
>> -                 * with the matching mask. Once irq_status
>> -                 * is all cleared, the search can be stopped.
>> -                 */
>> -                irq_status &= ~dpu_irq_map[irq_idx].irq_mask;
>> -            }
>> +        while ((bit = ffs(irq_status)) != 0) {
>> +            irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1);
>> +            /*
>> +             * Once a match on irq mask, perform a callback
>> +             * to the given cbfunc. cbfunc will take care
>> +             * the interrupt status clearing. If cbfunc is
>> +             * not provided, then the interrupt clearing
>> +             * is here.
>> +             */
>> +            if (cbfunc)
>> +                cbfunc(arg, irq_idx);
>> +
>> +            dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
>> +
>> +            /*
>> +             * When callback finish, clear the irq_status
>> +             * with the matching mask. Once irq_status
>> +             * is all cleared, the search can be stopped.
>> +             */
>> +            irq_status &= ~BIT(bit - 1);
>> +        }
>>      }
>>
>>      /* ensure register writes go through */
>> @@ -1469,32 +1443,30 @@ static int dpu_hw_intr_enable_irq(struct
>> dpu_hw_intr *intr, int irq_idx)
>>      int reg_idx;
>>      unsigned long irq_flags;
>>      const struct dpu_intr_reg *reg;
>> -    const struct dpu_irq_type *irq;
>>      const char *dbgstr = NULL;
>>      uint32_t cache_irq_mask;
>>
>>      if (!intr)
>>          return -EINVAL;
>>
>> -    if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
>> +    if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>>          pr_err("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>>
>> -    irq = &dpu_irq_map[irq_idx];
>> -    reg_idx = irq->reg_idx;
>> +    reg_idx = DPU_IRQ_REG(irq_idx);
>>      reg = &dpu_intr_set[reg_idx];
>>
>>      spin_lock_irqsave(&intr->irq_lock, irq_flags);
>>      cache_irq_mask = intr->cache_irq_mask[reg_idx];
>> -    if (cache_irq_mask & irq->irq_mask) {
>> +    if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
>>          dbgstr = "DPU IRQ already set:";
>>      } else {
>>          dbgstr = "DPU IRQ enabled:";
>>
>> -        cache_irq_mask |= irq->irq_mask;
>> +        cache_irq_mask |= DPU_IRQ_MASK(irq_idx);
>>          /* Cleaning any pending interrupt */
>> -        DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
>> +        DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
>>          /* Enabling interrupts with the new mask */
>>          DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
>>
>> @@ -1505,8 +1477,8 @@ static int dpu_hw_intr_enable_irq(struct
>> dpu_hw_intr *intr, int irq_idx)
>>      }
>>      spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
>>
>> -    pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
>> -            irq->irq_mask, cache_irq_mask);
>> +    pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
>> +            DPU_IRQ_MASK(irq_idx), cache_irq_mask);
>>
>>      return 0;
>>  }
>> @@ -1515,33 +1487,31 @@ static int
>> dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
>>  {
>>      int reg_idx;
>>      const struct dpu_intr_reg *reg;
>> -    const struct dpu_irq_type *irq;
>>      const char *dbgstr = NULL;
>>      uint32_t cache_irq_mask;
>>
>>      if (!intr)
>>          return -EINVAL;
>>
>> -    if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
>> +    if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>>          pr_err("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>>
>> -    irq = &dpu_irq_map[irq_idx];
>> -    reg_idx = irq->reg_idx;
>> +    reg_idx = DPU_IRQ_REG(irq_idx);
>>      reg = &dpu_intr_set[reg_idx];
>>
>>      cache_irq_mask = intr->cache_irq_mask[reg_idx];
>> -    if ((cache_irq_mask & irq->irq_mask) == 0) {
>> +    if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
>>          dbgstr = "DPU IRQ is already cleared:";
>>      } else {
>>          dbgstr = "DPU IRQ mask disable:";
>>
>> -        cache_irq_mask &= ~irq->irq_mask;
>> +        cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx);
>>          /* Disable interrupts based on the new mask */
>>          DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
>>          /* Cleaning any pending interrupt */
>> -        DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
>> +        DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx));
>>
>>          /* ensure register write goes through */
>>          wmb();
>> @@ -1549,8 +1519,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct
>> dpu_hw_intr *intr, int irq_idx)
>>          intr->cache_irq_mask[reg_idx] = cache_irq_mask;
>>      }
>>
>> -    pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
>> -            irq->irq_mask, cache_irq_mask);
>> +    pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
>> +            DPU_IRQ_MASK(irq_idx), cache_irq_mask);
>>
>>      return 0;
>>  }
>> @@ -1562,7 +1532,7 @@ static int dpu_hw_intr_disable_irq(struct
>> dpu_hw_intr *intr, int irq_idx)
>>      if (!intr)
>>          return -EINVAL;
>>
>> -    if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
>> +    if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>>          pr_err("invalid IRQ index: [%d]\n", irq_idx);
>>          return -EINVAL;
>>      }
>> @@ -1622,17 +1592,17 @@ static u32
>> dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>>      if (!intr)
>>          return 0;
>>
>> -    if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) {
>> +    if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
>>          pr_err("invalid IRQ index: [%d]\n", irq_idx);
>>          return 0;
>>      }
>>
>>      spin_lock_irqsave(&intr->irq_lock, irq_flags);
>>
>> -    reg_idx = dpu_irq_map[irq_idx].reg_idx;
>> +    reg_idx = DPU_IRQ_REG(irq_idx);
>>      intr_status = DPU_REG_READ(&intr->hw,
>>              dpu_intr_set[reg_idx].status_off) &
>> -                    dpu_irq_map[irq_idx].irq_mask;
>> +        DPU_IRQ_MASK(irq_idx);
>>      if (intr_status && clear)
>>          DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>>                  intr_status);
>> @@ -1647,7 +1617,6 @@ static u32
>> dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
>>
>>  static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
>>  {
>> -    ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup;
>>      ops->enable_irq = dpu_hw_intr_enable_irq;
>>      ops->disable_irq = dpu_hw_intr_disable_irq;
>>      ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
>> @@ -1679,7 +1648,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void 
>> __iomem *addr,
>>      __intr_offset(m, addr, &intr->hw);
>>      __setup_intr_ops(&intr->ops);
>>
>> -    intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map);
>> +    intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32;
>>
>>      intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), 
>> sizeof(u32),
>>              GFP_KERNEL);
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>> index b26a3445a8eb..c6b3d373ce75 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>> @@ -92,23 +92,14 @@ enum dpu_hw_intr_reg {
>>      MDP_INTR_MAX,
>>  };
>>
>> +#define DPU_IRQ_IDX(reg_idx, offset)    (reg_idx * 32 + offset)
>> +
>>  struct dpu_hw_intr;
>>
>>  /**
>>   * Interrupt operations.
>>   */
>>  struct dpu_hw_intr_ops {
>> -    /**
>> -     * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
>> -     *                 Used for all irq related ops
>> -     * @intr:        HW interrupt handle
>> -     * @intr_type:        Interrupt type defined in dpu_intr_type
>> -     * @instance_idx:    HW interrupt block instance
>> -     * @return:        irq_idx or -EINVAL for lookup fail
>> -     */
>> -    int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
>> -            enum dpu_intr_type intr_type,
>> -            u32 instance_idx);
>>
>>      /**
>>       * enable_irq - Enable IRQ based on lookup IRQ index
>> @@ -179,7 +170,7 @@ struct dpu_hw_intr_ops {
>>   * @ops:              function pointer mapping for IRQ handling
>>   * @cache_irq_mask:   array of IRQ enable masks reg storage created 
>> during init
>>   * @save_irq_status:  array of IRQ status reg storage created during 
>> init
>> - * @irq_idx_tbl_size: total number of irq_idx mapped in the 
>> hw_interrupts
>> + * @total_irqs: total number of irq_idx mapped in the hw_interrupts
>>   * @irq_lock:         spinlock for accessing IRQ resources
>>   * @obsolete_irq:      irq types that are obsolete for a particular 
>> target
>>   */
>> @@ -188,7 +179,7 @@ struct dpu_hw_intr {
>>      struct dpu_hw_intr_ops ops;
>>      u32 *cache_irq_mask;
>>      u32 *save_irq_status;
>> -    u32 irq_idx_tbl_size;
>> +    u32 total_irqs;
>>      spinlock_t irq_lock;
>>      unsigned long irq_mask;
>>      unsigned long obsolete_irq;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> index 6714b088970f..e349ea78a49d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
>> @@ -188,24 +188,23 @@ DECLARE_EVENT_CLASS(dpu_enc_irq_template,
>>            __entry->irq_idx)
>>  );
>>  DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
>> -    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
>> +    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>>           int irq_idx),
>> -    TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
>> +    TP_ARGS(drm_id, intr_idx, irq_idx)
>>  );
>>  DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
>> -    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
>> +    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>>           int irq_idx),
>> -    TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
>> +    TP_ARGS(drm_id, intr_idx, irq_idx)
>>  );
>>
>>  TRACE_EVENT(dpu_enc_irq_wait_success,
>> -    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
>> +    TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx,
>>           int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
>>      TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
>>      TP_STRUCT__entry(
>>          __field(    uint32_t,        drm_id        )
>>          __field(    enum dpu_intr_idx,    intr_idx    )
>> -        __field(    int,            hw_idx        )
>>          __field(    int,            irq_idx        )
>>          __field(    enum dpu_pingpong,    pp_idx        )
>>          __field(    int,            atomic_cnt    )
>> @@ -213,13 +212,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success,
>>      TP_fast_assign(
>>          __entry->drm_id = drm_id;
>>          __entry->intr_idx = intr_idx;
>> -        __entry->hw_idx = hw_idx;
>>          __entry->irq_idx = irq_idx;
>>          __entry->pp_idx = pp_idx;
>>          __entry->atomic_cnt = atomic_cnt;
>>      ),
>> -    TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
>> -          __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
>> +    TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d",
>> +          __entry->drm_id, __entry->hw_idx,
>>            __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
>>  );
>>
>> @@ -514,12 +512,12 @@ DEFINE_EVENT(dpu_id_event_template,
>> dpu_crtc_frame_event_more_pending,
>>  );
>>
>>  TRACE_EVENT(dpu_enc_wait_event_timeout,
>> -    TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
>> +    TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time,
>>           s64 expected_time, int atomic_cnt),
>> -    TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
>> +    TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt),
>>      TP_STRUCT__entry(
>>          __field(    uint32_t,    drm_id        )
>> -        __field(    int32_t,    hw_id        )
>> +        __field(    int,        irq_idx        )
>>          __field(    int,        rc        )
>>          __field(    s64,        time        )
>>          __field(    s64,        expected_time    )
>> @@ -527,14 +525,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout,
>>      ),
>>      TP_fast_assign(
>>          __entry->drm_id = drm_id;
>> -        __entry->hw_id = hw_id;
>> +        __entry->irq_idx = irq_idx;
>>          __entry->rc = rc;
>>          __entry->time = time;
>>          __entry->expected_time = expected_time;
>>          __entry->atomic_cnt = atomic_cnt;
>>      ),
>> -    TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
>> -          __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
>> +    TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld 
>> cnt=%d",
>> +          __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time,
>>            __entry->expected_time, __entry->atomic_cnt)
>>  );


-- 
With best wishes
Dmitry

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2021-05-26  2:09 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-16 20:29 [PATCH v2 0/6] drm/msm/dpu: rework irq handling Dmitry Baryshkov
2021-05-16 20:29 ` [PATCH v2 1/6] drm/msm/dpu: merge dpu_hw_intr_get_interrupt_statuses into dpu_hw_intr_dispatch_irqs Dmitry Baryshkov
2021-05-24 21:44   ` [Freedreno] " abhinavk
2021-05-16 20:29 ` [PATCH v2 2/6] drm/msm/dpu: hw_intr: always call dpu_hw_intr_clear_intr_status_nolock Dmitry Baryshkov
2021-05-24 21:46   ` [Freedreno] " abhinavk
2021-05-16 20:29 ` [PATCH v2 3/6] drm/msm/dpu: define interrupt register names Dmitry Baryshkov
2021-05-24 21:51   ` [Freedreno] " abhinavk
2021-05-16 20:29 ` [PATCH v2 4/6] drm/msm/dpu: replace IRQ lookup with the data in hw catalog Dmitry Baryshkov
2021-05-24 21:57   ` [Freedreno] " abhinavk
2021-05-26  2:09     ` Dmitry Baryshkov
2021-05-16 20:29 ` [PATCH v2 5/6] drm/msm/dpu: drop remains of old irq lookup subsystem Dmitry Baryshkov
2021-05-24 21:58   ` [Freedreno] " abhinavk
2021-05-16 20:29 ` [PATCH v2 6/6] drm/msm/dpu: simplify IRQ enabling/disabling Dmitry Baryshkov
2021-05-24 22:13   ` [Freedreno] " abhinavk

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).