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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Bhaumik Bhatt <bbhatt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org,
	jhugo@codeaurora.org, linux-kernel@vger.kernel.org,
	loic.poulain@linaro.org, linux-wireless@vger.kernel.org,
	kvalo@codeaurora.org, ath11k@lists.infradead.org
Subject: Re: [PATCH v4 5/6] bus: mhi: pci_generic: Set register access length for MHI driver
Date: Fri, 21 May 2021 19:22:18 +0530	[thread overview]
Message-ID: <20210521135218.GM70095@thinkpad> (raw)
In-Reply-To: <1620330705-40192-6-git-send-email-bbhatt@codeaurora.org>

On Thu, May 06, 2021 at 12:51:44PM -0700, Bhaumik Bhatt wrote:
> MHI driver requires register space length to add range checks and
> prevent memory region accesses outside of that for MMIO space.
> Set it from the PCI generic controller driver before registering
> the MHI controller.
> 
> Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
> Reviewed-by: Loic Poulain <loic.poulain@linaro.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  drivers/bus/mhi/pci_generic.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> index 7c810f0..fb7889f 100644
> --- a/drivers/bus/mhi/pci_generic.c
> +++ b/drivers/bus/mhi/pci_generic.c
> @@ -463,6 +463,7 @@ static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
>  		return err;
>  	}
>  	mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
> +	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
>  
>  	err = pci_set_dma_mask(pdev, dma_mask);
>  	if (err) {
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

  reply	other threads:[~2021-05-21 13:52 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-06 19:51 [PATCH v4 0/6] BHI/BHIe improvements for MHI power purposes Bhaumik Bhatt
2021-05-06 19:51 ` [PATCH v4 1/6] bus: mhi: core: Set BHI/BHIe offsets on power up preparation Bhaumik Bhatt
2021-05-21 13:36   ` Manivannan Sadhasivam
2021-05-06 19:51 ` [PATCH v4 2/6] bus: mhi: core: Set BHI and BHIe pointers to NULL in clean-up Bhaumik Bhatt
2021-05-21 13:37   ` Manivannan Sadhasivam
2021-05-06 19:51 ` [PATCH v4 3/6] bus: mhi: Add MMIO region length to controller structure Bhaumik Bhatt
2021-05-21 13:38   ` Manivannan Sadhasivam
2021-05-06 19:51 ` [PATCH v4 4/6] ath11k: set register access length for MHI driver Bhaumik Bhatt
2021-05-21 13:51   ` Manivannan Sadhasivam
2021-06-14 16:02     ` Kalle Valo
2021-06-14 17:49       ` Bhaumik Bhatt
2021-06-16 17:38         ` Bhaumik Bhatt
2021-06-18  6:45           ` Manivannan Sadhasivam
2021-06-23 17:29             ` Kalle Valo
2021-06-24  6:09               ` Manivannan Sadhasivam
2021-06-23 17:34         ` Kalle Valo
2021-06-23 21:33           ` Bhaumik Bhatt
2021-05-06 19:51 ` [PATCH v4 5/6] bus: mhi: pci_generic: Set " Bhaumik Bhatt
2021-05-21 13:52   ` Manivannan Sadhasivam [this message]
2021-05-06 19:51 ` [PATCH v4 6/6] bus: mhi: core: Add range checks for BHI and BHIe Bhaumik Bhatt
2021-05-07  2:33   ` Hemant Kumar
2021-05-21 13:54   ` Manivannan Sadhasivam
2021-06-25  5:28 ` [PATCH v4 0/6] BHI/BHIe improvements for MHI power purposes Manivannan Sadhasivam
  -- strict thread matches above, loose matches on Subject: below --
2021-05-06 19:32 Bhaumik Bhatt
2021-05-06 19:32 ` [PATCH v4 5/6] bus: mhi: pci_generic: Set register access length for MHI driver Bhaumik Bhatt

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